Design And Implementation Of Multiple Output Switch Mode Power Supply

Transcription

1 Inernaional Journal of Engineering Trends and Technology (IJETT) Volume Issue 0-Oc 0 Design And Implemenaion Of Muliple Oupu Swich Mode Power Supply Ami, Dr. Manoj Kumar Suden of final year B.Tech. E.C.E., Guru Jambheshwar Universiy Of Science & Technology, Hisar Assisan Professor, E.C.E. Dep., Guru Jambheshwar Universiy Of Science & Technology, Hisar Haryana-India ami_sangwan@live.in Absrac In his paper, he design of muliple oupu power supply is presened. An Embedded sysem requires differen volage levels for is proper funcioning because he componens used in any embedded sysem required differen volage levels as per heir specificaions, so his paper proposed a power supply ha includes V, -V, V, -V,.V, V Isolaed volage levels. The inpu for his power supply is 8V DC which is available a all elecom sies. This power supply is capable of providing approximae 0W oupu power wih 80% efficiency. The power supply design opology seleced for his paper is flyback converer because flyback converer is a beer opion as compare o oher opologies for low power design and for generaing muliple oupu volage levels. This power supply is designed by low cos and highly efficien discree componens and he paper also describes he crieria of choosing hese componens. This supply designed here can be used for almos all applicaions in elecom embedded producs due o is versaile range of consan oupu volage levels. Keywords Swich Mode Power Supplies, flyback converers, DC- DC converers I. INTRODUCTION Modern embedded elecronic sysems require high qualiy, small, lighweigh, reliable, and efficien power supplies []. SMPS are widely used in Telecommunicaion applicaions []. The main applicaions of hese SMPS are o provide supply o he various conrol pars, sensors, acuaors/relay drives and of course o he differen elecronic IC s wih high power densiy, high efficiency and consan operaional frequency. SMPS opologies can be classified according o he mehod of power ransfer from he inpu o oupu and are classified in flyback and forward groups. In he forward group, power is ransferred o he oupu when he main swich conducs i.e. during ON sae, whereas in he flyback group, he power is ransferred o he oupu when he main swich opens i.e. during OFF sae []. The flyback SMPS opology has been aracive for a long ime because of is simpliciy when compared wih oher opologies used in low power applicaions []. Fig. Simplified flyback converer The inpu dc source V DC and swich Q is conneced in series wih he primary ransformer. The diode D and he RC oupu circui are conneced in series wih he secondary of he flyback ransformer. The Do-ends of inducors deermines he operaion of he DC-DC converer. Polariy of primary (L p ) and secondary (L s ) are no same. When he swich Q is on, he curren in he magneizing inducance increases linearly and he primary curren I p raises o peak value []. A his inerval, secondary is opposiely polarized o he primary inducor as a resul diode D is off and here is no curren in he ideal ransformer s. This is shown below in fig. V DC V DC Q V P TXA TXA TXB V S TXB D C C R R II. TOPOLOGY OVERVIEW The flyback SMPS opology is based on Flyback DC-DC Converers. DC-DC Converers can be classified as isolaed and non-isolaed. Flyback converer is one of he simple opology in isolaed converers []. Fig. shows he ypical opology of flyback DC-DC converers. Fig. Swich Q in ON sae When swich Q is urned-off, sored energy a he air gap and magneic core are ransferred o secondary and magneizing inducance curren is supplied o he RC load. This is shown below in fig. ISSN: -8 hp:// Page 0

2 Inernaional Journal of Engineering Trends and Technology (IJETT) Volume Issue 0-Oc 0 Volage Volage V DC V P TXA V S TXB C R TON TOFF TON TOFF (a) (b) (c) Fig. Swich Q in OFF sae The dc volage ransfer funcion defined as he raio of he oupu volage o he inpu volage of he flyback converer is M = V D = V n( D) D is duy raio of he swich defined as a raio of he ON ime of he swich o he sum of he ON and he OFF imes. For a consan frequency operaion, D = n is he urns raio given by n = Where N and N are he primary and secondary urns. Flyback Converer can easily operae in wo modes, Coninuous Conducion Mode (CCM), Disconinuous Conducion Mode (DCM) []. As shown in figure, during he Q on ime, here is a fixed volage across he primary so primary curren will ramps up linearly. As secondary diode is reverse biased so here is no secondary curren during T. Primary curren is maximum a he end of T period. When Q urns-off, he magneizing curren in he primary sops and he volage of secondary will reverse, o creae he flyback acion. Due o his reverse secondary volage diode sar conducing and a decreasing secondary curren flows in he secondary as shown in figure. During his off period, primary is no conducing and so primary curren does no exis. In Disconinuous mode, he oupu curren goes o zero before he end of he T period, so ha all he sored energy is ransferred o he load. In Coninuous mode, he secondary curren is greaer han zero when Q urns-on for he nex period hence Secondary curren couldn fully discharge a any ime, so here is some residual energy sored in he ransformer a he end of he every ON and OFF periods. Fig. Flyback converer waveform: Disconinuous Mode vs. Coninuous Mode (a) Q Command Volage (b) Primary Volage (c) Primary Curren (d) Secondary Volage (e) Secondary Curren. III. BLOCK DIAGRAM OF THE SYSTEM The dc dc converer provides a regulaed dc oupu volage under varying load and inpu volage condiions. The converer componen values are also changing wih ime, emperaure, pressure, ec. Hence, he conrol of he oupu volage should be performed in a closed-loop manner using principles of negaive feedback. Two mos common closedloop conrol mehods for PWM dc dc converers, namely, he volage-mode conrol and he curren-mode conrol. Currenmode conrol is presened in he Fig.. REFERENCE VOLTAGE ERROR AMPLIFIER COMPARATOR SWITCH OR INDUCTOR CURRENT OUTPUT Fig. Block Diagram DC-DC CONVERTER The converer oupu volage is sensed and subraced from an exernal reference volage in an error amplifier. An inner conrol loop feeds back an inducor curren signal. This curren signal, convered ino is volage Analog, is compared o he conrol volage. The duy raio of he PWM signal depends on he value of he conrol volage. The frequency of he PWM signal is he same as he frequency of he curren signal. The comparaor produces a PWM signal which is fed o drivers of conrollable swiches in he dc dc converer. (d) (e) IV. SYSTEM DESIGN TECHNIQUE This secion of he paper covers he basics of PWM conroller and magneic design used in SMPS applicaions. ISSN: -8 hp:// Page

3 Inernaional Journal of Engineering Trends and Technology (IJETT) Volume Issue 0-Oc 0 VDC C C N7 KV N7 KV C VDC- N7 KV V R K R K R K7 C7 00NF R K7 TL R7 K L LB N C N C D C8 0.uF R K9 C 00uF/00V C9 R 00K R9 7K L N007 D 0nF C C9 0.uF NF C8 N R9 00K C8 00NF U R 8K 8 N COMP FB VREF OSC SG8 VOUT 7 R8 0K C0 NF D 7 V C C C0 0.uF R R R0 D v C C0 OUT CS -V 00uF/V 00N C nf R BYV7/00V RRR D TXA R R R0 Q IRF0 VOUT C 7 0UF C MC79L0AC 0uf U K D N007 C D7 R0 nf R D8 v R R R 0KR R -V C 0uf 7 8 R R TXD R7 7R C nf C7 9 0 nf/kv D L V C9 0UF/V TXB C7 0.uF D0 BYV7/00V C 00uF C0 0.uF D L BYV7/00V C R7 0K C C 0.uF C 0.uF 00uF L 0.uF C 00uF C 0.uF C 0.uF R 0K D N007 N VOUT R8 0K D9 N007 N VOUT GND 780 C 0.uF ISOV GND C7 780 C8 00uF 0.uF ISOGND V C C9 00uF 00nF TSP77 V IN OUT EN R8 FB U C 00nF C 00nF Fig. SMPS Circui Diagram Afer selecing he opology ha is bes suied o he power supply specificaion, he nex choice is o fix he swiching frequency and ransformer parameers. To do his, i is necessary o know he numerical relaion beween maximum available power and ransformer parameers such as magneic core area, magneic lengh, window area, bobbin area, peak flux densiy and coil curren densiy. A. PWM Conroller PWM conroller used in his design is UC8B which conrol he swiching ime of MOSFET power swich. I makes efficiency and sabiliy of SMPS higher and a he same ime makes he sysem cos, volume and weigh lower [7].This inegraed circui has an oscillaor, a emperaure compensaed reference, high gain error amplifier, curren sensing comparaor, and a high curren oem pole oupu ideally suied for driving a power MOSFET swich. The oscillaor frequency of his PWM conroller is programmed by he values seleced for he iming componens R and C. Capacior C is charged from he.0 V reference hrough resisor R o approximaely.8 V and discharged o. V by an inernal curren sink. f =.7 R C =.7 8.k nf = 09KHz f is he inpu frequency of PWM conroller and oupu frequency provided by PWM conroller is = 0.KHz which used as he swiching pulse of MOSFET swich. The duy cycle of pulse is conrolled by he feedback conrol loop. B. Transformer Design The ransformer design parameers were seleced such ha he SMPS could provide oupus according o he specificaion able given below TABLE I OUTPUT CURRENT AND VOLTAGES THROUGH DIFFERENT WINDINGS Oupu volage V 8V 8V V 8V Oupu curren A 0.A 0.A 0.A 0.A So he oal Oupu Power, P which we ge, is (V I) 0 W. This power supply is designed wih efficiency (η) of 80 %. For deliver his much oupu power wih his much efficiency we require our Inpu Power o be Inpu Power, P = Oupu Power Efficiency(in %)/00 0W The minimum Inpu Volage, V o he ransformer is Vdc and he maximum Volage, V o ransformer is 7Vdc. We choose maximum Duy cycle, D o be 0.7 and our sampling frequency, F as calculaed earlier was 0. KHz. ISSN: -8 hp:// Page

4 Inernaional Journal of Engineering Trends and Technology (IJETT) Volume Issue 0-Oc 0 From all hese parameers he Primary Inducance can be found using formula which gives L = 7 µh. L = (V D ) η P F Design ransformer is a course of repeaing calculaion. For cuing down he works of design, Power Inegraions Inc. offers a se of Excel able o design he ransformer [7]. So according o ha Excel able we found our secondary urns. C. Curren Sensing Feedback Loop The SMPS is made such ha maximum load is on V supply so we have used ha secion o provide feedback o he PWM conroller. The V supply is conneced o he inpu of TL which is hree-erminal adjusable shun regulaor, whose oupu volage can be se o any value beween V ref (approximaely. V) and V according o he inpu supplied. We have used a volage divider such ha he inpu o TL is.v when our supply gives V. A his volage he TL is fully shor and he opocoupler drives very high curren due o which feedback o he UC8 s FB pin is very high which will cause he oupu PWM o swich off and he MOSFET will no ge riggered and no EMF will be induced in he primary. When he V falls below V hen he inpu o TL will fall below. V and i will ge fully shored bu will have some resisance due o which small amoun of curren will flow hrough opocoupler and feedback o he PWM conroller will be small and i will generae oupu pulse of high duy cycle o he MOSFET. Similarly when he V has supply greaer han V he PWM will remain swich off and our MOSFET will remains off. D. Proecion ) Curren Proecion UC8 has an inernal curren comparaor which has a reference of V. Whenever inpu o he CS pin of UC8 which is oher inpu of CS comparaor ges beyond a limi of V he oupu of he IC auomaically ges swiched off. So we have fed back he CS pin from he MOSFET source hrough a volage divider such ha he inpu o he CS pin is less han V. If he oupu supply a secondary sides ge shored han he MOSFET will drive very large amoun of curren due o which volage a he CS pin will ge above V and he UC8 will sop generaing PWM pulses and our SMPS will ge swich off and our circui will remain proeced. ) Snubbers - There are wo basic ways o solve he problem of a semiconducor device ha is sressed beyond is raing. Eiher he device can be replaced wih a higher raed device o mee he sress level, or a snubber circui can be added o reduce he sress o a safe level. Boh opions are rade-offs beween cos, availabiliy of he higher raed device, complexiy, componen coun and he cos of using a snubber circui. A snubber circui is ypically used o limi he rae of rise of volage (ΔV/Δ), he volage applied across he device during urn-off, he rae of rise of curren (ΔI/Δ) and he curren hrough he device during urn-on. We have used snubber proecion for our MOSFET because when he MOSFET ges swiched ON, i ges a very high peck volage which ges sabilized afer some ime. To save our MOSFET from his volage peak we have used a snubber circui in parallel o MOSFET so ha he snubber suppresses he peak and our MOSFET remains proeced. E. Selecion of oher Componens used The MOSFET ha is being used as a swich in his SMPS design is IRF0. This is an N-Channel enhancemen mode silicon gae power field effec ransisor. This power MOSFET is designed for applicaions such as swiching regulaors, swiching converers, moor drivers, relay drivers, and drivers for high power bipolar swiching ransisors requiring high speed and low gae drive power. This MOSFET can be operaed direcly from IC s. Following IC s have been used o provide differen regulaed volages ) IC780- This is a posiive Volage regulaor which provides an oupu volage of V when is inpu ranges from 7 V o V. ) IC7809- This is a negaive Volage regulaor which provides an oupu volage of -V when is inpu ranges from -7V o - V. ) IC79- This is a negaive Volage regulaor which provides an oupu volage of -V when is inpu ranges from -7.V o -0 V. ) TSP77- The TPS77xx family of linear lowdropou (LDO) volage regulaors which uses an NMOS pass elemen in a volage-follower configuraion o provide an oupu volage 0f. V when is inpu volage ranges beween. o.v. V. RESULTS This sysem designed in his paper is very efficien, reliable, easy o implemen, low cos and generae maximum number of muliple consan oupus ha are required for any elecom embedded sysem. This SMPS designed in his paper is so reliable ha i can be used in elecom indusry for heir embedded producs. The various waveforms a differen poins in he sysem are as shown below. The waveform in fig 7(B) shows he oupu oscillaions produced by he PWM Conroller which has frequency of 0. KHz as described in Secion IV (A). The fig 7(B) shows he MOSFET drain oupu. ISSN: -8 hp:// Page

5 Inernaional Journal of Engineering Trends and Technology (IJETT) Volume Issue 0-Oc 0 Figure 8 shows he hardware implemenaion of muliple oupu SMPS. The nex waveforms shown here in, Fig. 9, Fig. 0, Fig., Fig. and Fig are of differen oupu volages. The differen volage levels obained can be seen clearly from he respecive figures shown below. Fig.7 PWM Conroller and MOSFET oupu Fig.9 Oupu Volage (Isolaed V) Fig.0 Oupu Volage (V) Fig. Oupu Volage (V) Fig. Oupu Volage (.V) Fig.8 Hardware Design ISSN: -8 hp:// Page

6 Inernaional Journal of Engineering Trends and Technology (IJETT) Volume Issue 0-Oc 0 Fig. Oupu Volage (V) REFERENCES [] Muhammad H. Rashid, Power Elecronics Handbook, Second Ediion Devices, Circuis and Applicaions, Academic Press. [] Abraham I. Pressman, Swiching Power Supply Design, McGraw- Hill. [] Babak Abdi, Jafar Milimonfared, Ahmad Mahin Fallah, A High- Performance. KW SMPS wih Single Swich Forward Topology, 9h Inernaional Muliopic Conference, IEEE INMIC 00, pg.. [] Vishnu P.Nambiar, Azli Yahya and Thayala R. Selvaduray, SPICE Modelling of a Valley Swiching Flyback Power Supply Conroller for Improved Efficiency in Low Cos Devices, Circuis and Sysems (ICCAS), 0 IEEE Inernaional Conference, pg. 0- [] Nasir Coruh, Sailmis Urgun, Tarik Erfidan, Design and Implemenaion of Flyback Converers, Indusrial Elecronics and Applicaions (ICIEA), h IEEE Conference, 00, pg [] Pressman A.I., "Swiching Power Supply Design", Second Ed. McGraw-Hill, 998, pp [7] Yang Li, Chen Ying, Xiao Qianhua, A Small Power Swiching Mode Power Supply Based on TOP Swich, 009 Inernaional Join Conference on Arificial Inelligence, pg ISSN: -8 hp:// Page