A 30nA Quiescent 80nW to 14mW Power Range Shock-Optimized SECE-based Piezoelectric Harvesting Interface. with 420% Harvested Energy Improvement

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1 A 30nA Quiescen 80nW o 14mW Power Range -Opimized SECE-based Piezoelecric Harvesing Inerface wih 420% Harvesed Energy Improvemen Anhony Quelen, Adrien Morel, Pierre Gasnier, Romain Grézaud, Séphane Monfray, Gaël Pillonne Univ. Grenoble Alpes, CEA, LETI, MINATEC, F Grenoble, France. STMicroelecronics, Grenoble, France. Piezoelecric Energy Harvesers (PEH) are usually used o conver mechanical energy (vibraion, shocks) ino elecrical energy, in order o supply energy-auonomous sensor nodes in indusrial, biomedical or domoic applicaions. Non-linear exracion sraegies such as Synchronous Elecrical Charge Exracion (SECE) [1-2], energy invesing [3] or Synchronized Swich Harvesing on Inducor (SSHI) [4] have been developed o maximize he exraced energy from harmonic exciaions. However, in mos of oday s applicaions, vibraions are no periodic and mechanical shocks occur a unpredicable raes [4]. SSHI inerfaces naurally seemed o be he mos appropriae candidae for harvesing shocks as hey exhibi ousanding performance in periodic exciaions [4]. However, he SSHI sraegy presens inheren weaknesses while harvesing shocks, since he invesed energy sored in he piezoelecric capaciance canno be recovered. In his work, we propose a self-saring, baery-less, 0.55mm 2 inegraed energy harvesing inerface based on SECE sraegy which has been opimized o work under shock simulus. Due o he sporadic naure of mechanical shocks which imply long periods of inaciviy and brief energy peaks, he inerface s average consumpion is opimized by minimizing he quiescen power. A dedicaed energy saving sequencing has hus been designed, reducing he saic curren o 30nA and enabling energy o be exraced wih only one single 8µJ shock occurring every 100s. Our SECE-based circui feaures a shock FoM 1.6x greaer han previous SSHI-based inerfaces [4]. The proposed sysem depiced in Fig.1 is made of a negaive volage converer recifying he PEH oupu volage, and a SECE power pah conrolled by a sequenced circui. The sequencing is divided in 4 phases and he associaed ime diagrams are illusraed in Fig.2. During he sleeping mode T1, all blocks excep he shock deecion (SD) are urned off. During he saring phase, he energy is sored in CASIC hrough a cold-sar pah, increasing ASIC. This will progressively urn on he SD. Nex, when sress applied o he piezoelecric maerial leads o an increase in, he SD checks if he elecrical energy

2 convered by he piezoelecric ransducer is sufficienly high o be harvesed (>ASIC). By seing FlagSHOCK, he SD enables he ASIC deecion which deermines wheher he cold sar pah should be acivaed. If ASIC is below 1.5, we consider ha he sored energy is insufficien o sar he SECE operaion, and he cold sar pah remains conneced in order o keep on charging CASIC. If his is no he case, he deecion block sends he FlagSTART signal which disables he cold sar, enables he peak deecion and sars he maximum volage deecion phase T2. When reaches is maximum, he sysem eners is harvesing phase T3. N1 is se high, which connecs he inducance L wih he piezoelecric capaciance, CP. The dual mode comparaor (DMC) is used in is zero crossing deecion (ZCD) configuraion, and deecs when goes below TL=-14m, which means ha almos all he energy previously sored in CP has been exraced in L. Then, he sysem sars is soring phase T4. N1 is urned off, while P2 and N2 are urned on. The insan IL reaches zero, which is deeced by he same DMC used in is Reverse Curren Deecion (RCD) configuraion, indicaes ha all he energy ha was sored in L during T3 has been ransferred in CSTORE. Ulimaely, he sysem reurns o is sleep mode T1, waiing he nex energy even. N3 acs as a freewheeling diode and provides a pah o dissipae he remaining energy in L. Fig.3 shows deailed ransisor-level schemaics of he DMC and he and ASIC Deecions. During T3, he DMC is enabled in is ZCD configuraion. M2 and M4 consiue a differenial pair allowing o be compared wih he ground volage. Due o M1, when is high, only ¼ of he bias curren flows hrough M1 and M2. As decreases (hanks o he charge ransfer occurring beween CP and L), he curren in M2 is increased, which improves he deecion accuracy. Furhermore, he circui consumpion is reduced when is high, since i is only useful o increase he comparaor performances when ges close o 0. HYST is iniially high, which creaes a -14m offse on he inpu of he comparaor. The circui also includes a comparaor which is used o accuraely implemen he zero crossing deecion. During T4, he DMC swiches o is RCD configuraion. HYST is se low, which suppresses he -14m offse. In his phase, is proporional o IL, as N2 is urned on. Therefore, when IL decreases, increases unil i reaches 0. Then, T1 sars. The DCM is disabled in order o avoid any unnecessary energy consumpion, and only he SD is powered. Therefore, during T1, he 30nA@1.5 curren drawn from CASIC is he one flowing hrough M17, as shown in Fig.3. When increases, curren sars flowing hrough M14 which forces M16 s drain poenial o increase. If >ASIC, hen Flag becomes high, which consequenly enables he ASIC Deecor by forcing M20 conducion. To avoid any ringing, a resisance RHYS is used o creae a difference beween he

3 high (1.5) and low (1.4) hreshold. The inegraed resisances R1 and R2 enable he minimum of ASIC o be seleced, o ensure he self-operaion of he chip. In our case, we fixed his minimum ASIC a 1.5. When his condiion is saisfied, FlagSar is se high, hanks o a wo-sage comparaor. Our chip was fabricaed in CMOS 40nm echnology including 10 devices, and occupies a 0.55mm 2 core area (Fig.7). In order o emulae boh periodic and shock exciaions, a MIDE piezoelecric generaor (PPA1011) wih a 5.67g mobile mass and a resonan frequency of 75.4 Hz has been placed on a shaker. The harveser has an inrinsic capaciance CP of 43nF. Fig.4 shows muliscale experimenal waveforms of he inerface circui undergoing shocks wih CSTORE and CASIC iniially discharged. The shocks are applied every second, wih various acceleraions from 5 o 16G. The off-chip inducance L and capaciances CSTORE and CASIC values are 2.2mH, 100µF, and 10µF, respecively. Afer he firs hree shocks, which are used o sore enough energy in CASIC hanks o he cold sar power pah, he sysem operaes auonomously in is opimized mode and he energy is sored in CSTORE. For es purposes, when STORE reaches 2.8, he energy monioring block inermienly connecs a 1kΩ load resisance o emulae he consumpion of a sensor. The power sored in CSTORE was measured under shock and periodic vibraions for many STORE as shown in Fig.5. From weak o srong shocks, our chip harvesed 2.8x o 4.2x more han he maximal energy harvesed using an on-chip full bridge recifier inerface, while i reached a FoM of 3.14 under periodic exciaion. In Fig.6, he performance of our chip is compared o prior ar. We obained a 1.6x shock FoM enhancemen in comparison o previous work [4]. Our sysem also shows he bes FoM under periodic exciaion compared o oher SECE inerfaces [1-2]. The measured maximum end-o-end efficiency of our circui is 94% under periodic exciaion a 82µW which is he highes end-o-end efficiency compared o former work [1-4]. The measured quiescen curren in sleeping mode is 30nA@1.5. This allows self-operaion of our circui wih an inpu power as low as 80nW. We were able (using various PEH) o mainain an efficiency over 70% for inpu power below 14mW. The proposed IC in 40nm echnology allows o add harvesing funcionaliies wihin a microconroller die.

4 References: [1] P. Gasnier e al., An Auonomous Piezoelecric Energy Harvesing IC Based on a Synchronous Muli-Sho Technique, IEEE Journal of Solid-Sae Circuis, vol. 49, no. 7, pp , [2] T. Hehn e al., A Fully Auonomous Inegraed Inerface Circui for Piezoelecric Harvesers, IEEE Journal of Solid- Sae Circuis, vol. 47, no. 9, pp , [3] D. Kwon e al., A single-inducor 0.35-µm CMOS energy-invesing piezoelecric harveser, IEEE Inernaional Solid- Sae Circuis Conference, pp , [4] D. A. Sanchez e al., 21.2 A 4µW-o-1mW parallel-sshi recifier for piezoelecric energy harvesing of periodic and shock exciaions wih inducor sharing, cold sar-up and up o 681% power exracion improvemen, IEEE Inernaional Solid-Sae Circuis Conference, pp , 2016.

5 Piezo. Harveser I * -. Negaive olage Converer *+ Cold sar Deecion Flag '(8"( Bulk reg. Flag 'CDEC Flag '>?@A Bulk reg. ASIC Deecion % "#$ I G C 8'B$ 789 8'B$ Bulk reg. '()"# I L T + T, Zoom I L Peak Deecion Zero Crossing Deecion Reverse Curren Deecion *, Peak Deecion Load )4 SECE Conrol DMC 5 X R G)8H 5 Y N Circui L Flag 9 U =>?@A Even 5 C '()"# Based Gaes Y Drivers 5 Wake up X 5 N 6 1 Conroller * Y Flag =CDEC Load )4 Power pah 789 '()"# Cold )4 Maximum Selecion I =max {I JKL NOPQR, TLU, I } KNW L 9 U 8'B$ Energy Monioring for Sensor N 3 * Y P 2 Flag %&'() Blocks\Timings T + T, T - T. Peak Deecion Off On Off Off Deecion On On On On Zero Crossing Deecion Off Off On Off Reverse Curren Deecion Off Off Off On Maximum Selecion On On On On ASIC Deecion Off On On On 1, , 2 + T / T - T. T, T - T. T + Figure 1: Piezoelecric inerface overview. Figure 2: Waveforms, chronograms and sequencing of he conrol circui. ASIC M5 6I 2I 3I I Dual Mode Comparaor ZCD & RCD M10 HYST ZCD/RCD every second WSN powering Single M1 M 2 M4 8R M6 M7 M11 HYST T " T # T $ RCD ASIC TH=0 HYST M 3 ASIC R0 2R M 14 M 8 M 9 M12 10R M17 M na Flag M13 TL=-14m ZCD Deecion and ASIC Deecion M23 Peak deecion Zoom R3 M 25 ASIC M15 M20 M 27 R HYS ASIC_OK M22 M24 Flag M16 M19 M18 R 1 M26 M 28 FlagSar R 2 Figure 3: Dual mode comparaor and shock deecor schemaics Figure 4: Measured ransien waveforms of he proposed inerface. 28.$%& 8'.!%& 26.$%&!. #$%& Harvesing p,oc =6 & a ex =12g Harvesing periodic vibraions@ p,oc =2.85 & f=75.4hz 8.16%& FOM MAX = 4.2 '. (#%& Harvesing p,oc =3.4 & a ex =5g FOM from weak o srong shocks every 1s [1] [2] [3] [4] This Work Uni Technology nm Chip Size mm 2 Scheme Type SECE SECE Energy Invesing SSHI SECE - Piezoelecric MIDE MIDE 21B MIDE Muraa MIDE 22B Harveser 22B & 22B PPA C P nf Exciaion ype Periodic Periodic Operaion Frequency Hz FOM (periodic) (2) 170 (1) % FOM (shocks) (3) N/A N/A % Cold Sarup Yes Yes No Yes Yes - End-o-end Efficiency (1) 94 % Inpu power range µw Quiescen curren (1) 0.03 µa (1) Calculaed from he paper (2) FOM (periodic) = "#$ (P ou ) 2 (3) FOM (shocks) = 01 f oc - max(p ou ) max(p ou FBD ) Figure 5: Measured harvesed power comparison beween our inerface and using an acive sandalone full bridge recifier (FBR). Figure 6: Performances comparison wih prior ar.

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