ESD. What is ESD? Lightning to the buildings. ESD to IC s. ESD protection circuit for IC s. Lightning Rod for Buildings

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Hope Houston
5 years ago
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1 007/Dec/9

2 Wha is ESD? ESD ElecroSaic Discharge ESD is a high-curren (~mps) and shor-duraion ime (~ns) even ESD even due o ribo-elecrically generaed charges. ESD o IC s Lighning o he buildings ESD proecion circui for IC s Lighning Rod for Buildings

3 ESD Is ESD so wors? Means of saic generaion Person walking across carpe Person walking across Vinyi floor Worker a a bench Ceramic DIP in plasic ube Ceramic DIP in Vinyi se-up Tray IC packs as bubble plasic cover is removed IC packs as packed in foam lined shipping box ElecroSaic Volage 0% 40% 55% 5,000V 5,000V 7,500V,000V 5,000V,000V 6,000V 500V 400V,000V 700V 400V,500V 4,000V,000V 6,000V 0,000V 7,000V,000V,000V 5,500V Yes, be more worse han wha you expeced!

4 ESD MS CMOS.,.0, 0.8µm 0.60, 0.50µm 0.45, 0.5µm 0.5, 0.8µm CM0.V/.5V CMN90 ( ).0V/.5V RF CMOS CM05.5V/.V CM08.8V/.V CM0.V/.5V CMN90 ( ).0V/.5V SiGe BiCMOS SG05.V SG08.8/.V vailable Technologies Lef edge of each box represens risk producion schedule MiM is offered for CM05 and below and SiGe echnologies. 4

5 ESD Models of ESD : Human Body Model (HBM) Sandard:. MIL-STD-8C Mehod ESD STM 5. (998). EI/JEDEC V ESD Rg B.5 kω 00 pf Device Under Tes I HBM () Time (ns) I peak. ( kv HBM) Tr = ~ 0 ns; Tduraion = 0 ns 5

6 ESD Models of ESD : Machine Model (MM) Sandard:. ESD STM 5. (EOS/ESD, 999). EI/JEDEC- 5- (997) 4 R g B I 0 MM () V ESD 00 pf Device Under Tes Time (ns) I peak.8 (00 V MM) Resonance Freq. 6 MHz 6

7 ESD Models of ESD : Charged Device Model (CDM) Sandard:. ESD STM 5. (EOS/ESD, 999). JESD-C 0- (JEDEC 000) R g B V ESD R d L d C d Device Under Tes 5 I CDM () Time (ns) I peak 5, R, L d d : parameers of he package T r < 00 ps (kv 4 pf) 7

8 ESD Comparison of HBM, MM and CDM pulse 0 5 I () 0 5 kv CDM (4pF) 00V MM (0Ω) 0-5 kv HBM Time (ns) 8

9 ESD ESD Zapping esing (HBM/MM) V VDD 0V VDD 0V V VDD 0V -V VSS VSS VSS VDD VDD 0V -V VDD V 0V 0V -V VSS VSS VSS 9

10 ESD ESD Zapping esing Funcion Tes V VDD 0V VDD I/V curve 0V VSS -V VSS ESD Zap I/V curve V VDD 0V VDD Good Fail 0V OP VSS -V OP VSS Funcion Tes noher One Lower ESD level Zap Funcion Tes 0

11 CDM es ESD Posiive-mode: ll pins floa; subsrae is charged by a posiive volage filed; hen discharge hrough one pin. Negaive-mode: ll pins floa; subsrae is charged by a negaive volage filed; hen discharge hrough one pin. Inpu Pad ESD Clamp D G N Poly S Subsrae Conac N N P P-subsrae

12 ESD Basic Proecion Design Concern Provide ESD proecion wih efficien discharging pahs o bypass any ESD sress. Pass he normal I/O signals and keep inacive while he IC is in normal operaion condiion Low inpu capaciance and resisance o mee accepable I/O signal delay (as small as possible) Have a high ESD robusness wihin a reasonable layou area Wihou increasing he addiional mask layer or modifying he process seps as possible Device Process Layou Circui

13 ESD

14 ESD Example of Sharing Clamping across Muliple Power Domains Clamping 4

15 ESD Proecion for RF Pin ESD Low parasiic capaciance Consan inpu capaciance Low subsrae coupling noise Good ESD performance (> kv, HBM) ESD Conclusion On chip ESD proecion is he design for all pins (I/O as well as VDD, VSS, ec.) Whole chip ESD proecion scheme become more imporan in deepsubmicron CMOS IC s. Wih a good VDD o VSS (GND) ESD clamping proecion, i can sill have a grea ESD level greaer han kv(hbm), 00V(MM), kv(cdm) Wach ou he paerns! 5

16 Transceiver rchiecures The primary crieria in selecing ransceiver archiecures: Complexiy Cos Power dissipaion The number of exernal componens General Consideraions IC echnology available Specrum allocaion o each user (BW vs. daa rae; channel vs. band) TX / RX bands are in proximiy; adjacen channel signals should also be reaed as in-band inerferers (lineariy) The loss of he fron-end BPF Transmied specral mask Dynamic Range Noise immuniy and supply rejecion (especially for P) 6

17 Transceiver rchiecures Power mplifier Transmied Channel BPF (a) djacen Channel Inerferers BPF Low Noise mplifier Desired Channel (b) Figure 5. (a) Transmier and (b) receiver from ends of a wireless ransceiver. 7

18 Transceiver rchiecures Bandpass Filer nd order LC filer, Q~0 7 45kHz TX Band RX Band 0kHz 60 db 0dB/div. 900MHz f Figure 5. Rejecion required of a hypoheical fron-end bandpass filer. 0MHz/div. Figure 5.4 Typical duplexer characerisic. Desired Channel BPF LN Receive Band Figure 5. Band selecion a he fron end of a receiver. f f 8

19 Transceiver rchiecures Inerferers Desired Channel LN BPF Figure 5.5 Effec of nonlineariy in he fron end. LN Duplexer 0V P Figure 5.6 Desensiizaion of LN by P oupu leakage. 9

20 0 Receiver rchiecures Inermodulaion producs: (due o nonlineariy) ) cos( 4 ) cos( 4 : ) cos( 4 ) cos( 4 : ) cos( ) cos( : α α α α α α ± = ± = ± = (.) (.) (.4). cos 4 cos 4 :, α α α α α α = (.5) IM IM (). cos cos ssume x = () ( ) ( ) ( ) (.). cos cos cos cos cos cos Thus y α α α =

21 Receiver rchiecures Heerodyne Receivers LPF cos 0 0 (a) 0 LN LPF cos 0 0 (b) Figure 5.7 (a) Simple heerodyne down-conversion, (b) inclusion of an LN o lower he noise figure.

22 Receiver rchiecures Heerodyne Receivers Problem of Image IF LO IF im cos LO LPF IF Figure 5.8 Problem of image in heerodyne recepion. LN Image Rejec Filer cos LO im IF Figure 5.9 Image rejecion by means of a filer.

23 Receiver rchiecures Heerodyne Receivers Problem of Image Inerferer Desired Channel LN Image Rejec Filer cos LO Channel Selec Filer higher Q filer IF im (a) 0 If higher image IF im Figure 5.0 Rejecion of image versus suppression of inerferers for (a) high IF and (b) low IF. (b) 0 If

24 Receiver rchiecures Heerodyne Receivers Problem of Half IF Desired Band in in LO LO LN Image Rejec Filer cos LO Heerodyne Receivers Dual-IF Topology Band Selec Filer Inerferer LN 0 IF IF Figure 5. Problem of half IF in heerodyne recepion. Image Rejec Filer Channel Selec Filer BPF BPF BPF BPF 4 B C D E F G H Channel Selec Filer IF mplifier LO LO Figure 5. Dual-IF heerodyne receiver. 4

25 Receiver rchiecures Heerodyne Receivers Dual-IF Topology Desired Channel Image B f f C D f f E F f f G H f f Figure 5. Dual-IF heerodyne receiver. 5

26 Receiver rchiecures Heerodyne Receivers Dual-IF Topology ( θ ) a( )cos C b( )sin θ ( ) C cos C sin C LPF LPF I Q a() cosθ Channel Selec Filer b() sinθ Figure 5. Quadraure down-conversion. 6

27 Receiver rchiecures Homodyne Receivers LN 0 cos 0 (a) LPF 0 LPF I LN cos 0 sin 0 LPF (b) Figure 5.4 (a) Simple homodyne receiver, (b) homodyne receiver wih quadraure down-conversion. Q 7

28 Receiver rchiecures Homodyne Receivers Channel Selecion Channel Selec Filer mp (a) DC mp Channel Selec Filer (b) DC mp DC (c) Channel Selec Filer Figure 5.5 (a) Three permuaions of baseband funcions. 8

29 Receiver rchiecures Homodyne Receivers DC Offses LN B C X LPF DC LO Leakage cos LO (a) LN B C X LPF DC Inerferer cos LO Leakage (b) Figure 5.6 Self-mixing of (a) LO signal, (b) a srong inerferer. 9

30 Receiver rchiecures Homodyne Receivers I/Q Mismach LPF I LPF I 90 o 90 o V RF V LO V RF V LO LPF Q LPF Q (a) Figure 5.8 Quadraure generaion in (a) RF pah, (b) LO pah. (b) 0

31 Receiver rchiecures Homodyne Receivers I/Q Mismach Phase and Gain Error LPF I Q ideal Q ideal V RF V LO 90 o Phase and Gain Error Phase and Gain Error I I LPF Phase and Gain Error Q Figure 5.9 I/Q mismach conribuion by various sages. (a) (b) Figure 5.0 Effec of I/Q mismach on QPSK signal consellaion: (a) gain error, (b) phase error.

32 Receiver rchiecures Homodyne Receivers Even-Order Disorion Inerferers 0 Desired Channel LN Feedhrough cos LO 0 Figure 5. Effec of even-order disorion on inerferers.

Receiver Architectures

Receiver Architectures 27/Dec/26 1 Receiver Archiecures Image-Rejec Receivers Shif-by-9 o For narrowband signal: sin cos +j /2 +j (a) T / 4 X = j j /2 G( ) = j sgn( ) 1/2 (b) Figure 5.23 Shif by 9 o in (a) ime and (b) frequency