Lecture Frequency Synthesizers - I (6/25/03) Page 170-1

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1 Lecure 170 Frequency Synhesizers I (6/25/03) Page 1701 LECTURE 170 APPLICATIONS OF PLLS AN FREQUENCY IVIERS (PRESCALERS) (References [2, 3, 4, 6, 11]) Objecive The objecive of his presenaion is: 1.) Examine he applicaions of PLLs 2.) evelop and characerize he echniques used for frequency division Ouline Applicaions of PLLs Inegraed Circui Frequency Synhesizers Archiecures and Techniques ividers for Frequency Synhesizers NoiseShaping Techniques Summary Lecure 170 Frequency Synhesizers I (6/25/03) Page 1702 APPLICATIONS OF PLLS The PLL The PLL is a very versaile building block and is suiable for a variey of applicaions including: 1.) emodulaion and modulaion 2.) Signal condiioning 3.) Frequency synhesis 4.) Clock and daa recovery 5.) Frequency ranslaion

2 Lecure 170 Frequency Synhesizers I (6/25/03) Page 1703 FM emodulaion When he PLL is locked on a frequency modulaed signal, he conrolling volage o he VCO becomes proporional o he frequency. v in Phase eecor Loop Filer Posdeecion Filer v ou VCO v c v in f 1 f 2 f 1 V 2 v ou V 1 Fig Can be used for frequency shif keying (FSK) if a volage discriminaor is placed a he oupu. Lecure 170 Frequency Synhesizers I (6/25/03) Page 1704 FM emodulaion Example If K o = 2π(1kHz/Vol), K v = 500 (sec1) and ω o = 1000π rads/sec ( = 500Hz) for he FM demodulaor on he previous slide, (a.) Find V o for f i = 250Hz and 1000Hz. (b.) Wha is he ime consan of V o for a sep change beween hese wo frequencies? Soluion (a.) We know ha ω i ω o ω osc = ω i = ω o K o V o V o = K o V o (250Hz) = = 0.25V V o (1000Hz) = = 0.5V (b.) τ = 1 K v = 2ms We noe ha he riseimes of he square wave on he previous page would no longer be zero bu ake abou 10ms o go from one level o anoher.

3 Lecure 170 Frequency Synhesizers I (6/25/03) Page 1705 FM emodulaor Example Coninued Example: For he PLL of he previous example, find v o () if he inpu signal is frequency modulaed so ha ω i () = 2π(500Hz)[10.1sin(2πx102)]. Soluion V o (jω) ω i (jω) = 1 K v K o K v jω = 1 K v K o K v j2πx100 ω=200π = 2000π 500j628 = π (0.39j0.48) ω i (jω) = 0.1(1000π) = 100π = 50(2π) V o (jω) = (0.39j0.48) = /51 = 0.031/51 or v o () = sin[(2πx102)51 ] Lecure 170 Frequency Synhesizers I (6/25/03) Page 1706 Phase Modulaor When he PLL is locked on a fixed frequency, a slowly varying signal, v m (), can be used o cause he phase shif he VCO o shif achieving a phase modulaor. Phase modulaion signal v m () Phase eecor Loop Filer vc VCO v ou Fig v ou () = V ou cos[ω ref θ m ()] where θ m () = 1 K d v m()

4 Lecure 170 Frequency Synhesizers I (6/25/03) Page 1707 Signal Condiioning The PLL can operae as a narrowband filer wih an exremely high Q o selec a desired signal in he presence of undesired signals. v in Phase eecor Loop Filer v c VCO v ou ω c ω c Fig This applicaion represens a radeoff in he capure range and he loop bandwidh. If he loop bandwidh is small, he SNR of he oupu can be much greaer han he inpu. If he loop bandwidh is large, he capure range for he desired signal is larger (can rack he desired signal beer). Lecure 170 Frequency Synhesizers I (6/25/03) Page 1708 Frequency Synhesis ividers placed in he feedback and/or inpu allow he generaion of frequencies based on a sable reference frequency. M Volage which makes f = LO M N M Phase eecor Loop Filer VCO u = M N f LO N N Oscillaor conrol volage Fig A When he phase deecor is locked, he wo incoming frequencies are equal. Therefore, M = u N u = N M

5 Lecure 170 Frequency Synhesizers I (6/25/03) Page 1709 Clock and aa Recovery The funcion of a clock and daa recovery circui is o produce a sable iming signal from a sream of binary daa. Clock recovery consiss of wo basic funcions: 1.) Edge deecion 2.) Generaion of a sable periodic oupu in Edge eecor Phase eecor Loop Filer v c VCO Clock Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page Jier Suppression In digial communicaions, ransmier or rerieved daa may suffer from iming jier. A PLL clock recovery circui can be used o regenerae he signal and eliminae he jier as shown below. Flipflop in Q ou Clock Recovery Circui in Clock ou Fig

6 Lecure 170 Frequency Synhesizers I (6/25/03) Page Frequency Translaion The PLL can be used o ranslae he frequency of a highly sable bu fixed frequency oscillaor by a small amoun in frequency. Someimes called frequency offse loop. sc ± fosc f 1 Mixer LPF Phase eecor Loop Filer vc VCO u = f 1 sc Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page IC FREQUENCY SYNTHESIZERS ARCHITECTURES AN TECHNIQUES Synhesizer Specificaions for Various Wireless Sandards Wireless Sandard Frequency Range (MHz) Channel Spacing Number of Channels Swiching Time GSM Rx: kHz µs Tx: CS1800 Rx: kHz µs Tx: PCS1900 Rx: kHz 800µs Tx: ECT MHz µs AMPS Rx: kHz 832 Slow Tx: CMA Rx: MHz 20 Tx: PHS1900 Rx: kHz ms IS54 Rx: kHz 832 Slow Tx: WLAN MHz 79 Several µs

7 Lecure 170 Frequency Synhesizers I (6/25/03) Page Componens of a Frequency Synhesizer Funcion of a frequency synhesizer is o generae a frequency from a reference frequency. Block diagram: Reference Frequency Phase Frequency eecor (PF) LPF VCO Componens: Phase/frequency deecor oupus a /N ivider (1/N) Fig signal ha is proporional o he difference beween he frequency/phase of wo inpu periodic signals. The lowpass filer is use o reduce he phase noise and enhance he specral puriy of he oupu. The volageconrolled oscillaor akes he filered oupu of he PF and generaes an oupu frequency which is conrolled by he applied volage. The divider scales he oupu frequency by a facor of N. = N = N Lecure 170 Frequency Synhesizers I (6/25/03) Page Basic Frequency Synhesizer Archiecure Simple frequency synhesizer: Reference Frequency Phase Frequency eecor (PF) LPF VCO /N ivider (1/N) Fig Commens: Frequency sep size is equal o. Thus, for small channel spacing,, is small which makes N large. Large N resuls in an increase in he inband phase noise of he VCO signal by 20log(N). = N

8 Lecure 170 Frequency Synhesizers I (6/25/03) Page Basic Frequency Synhesizer Archiecure Coninued Frequency Synhesizer wih a SingleModulus Prescaler: PF LPF VCO Programmable ivider 1/N p Commens: = N P P Only he prescaler needs o run a very high speed Prescaler 1/P Fig Since P is fixed, he value of N P is smaller causing increased channel spacing resuls in increased lockon ime and sidebands a undesirable frequencies Soluion: 1/P /P PF LPF VCO Programmable ivider 1/N p Prescaler 1/P Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page Basic Frequency Synhesizer Archiecure Coninued Frequency Synhesizer wih a ualmodulus Prescaler: Operaion: 1.) The modulus conrol signal is low a he beginning of a coun cycle enabling he prescaler o divide by P 1 unil he A couner couns o zero. 2.) The modulus conrol signal goes high enabling he prescaler o divide by P, unil he N P couner couns down he res of he way o zero (N P A). 3.) Thus, N = (N P A)P A(P1) = N P A = (N P A). 4.) The modulus conrol is se back low, he couners are rese o heir respecive programmed values and he sequence is repeaed. Commens: N P > A The value of P divided by he maximum frequency of he VCO mus no exceed he frequency capabiliy of he N P and A couners. P imes he period of he maximum VCO frequency > he sum of he propagaion delay hrough he dualmodulus prescaler plus he prescaler seup or release ime relaive o is conrol signal plus he propagaion delay of o he modulus conrol. PLL N P Couner ualmodulus 1/N Prescaler P 1/P or 1/(P1) A Couner Conrol Logic Fig

9 Lecure 170 Frequency Synhesizers I (6/25/03) Page Example ual Modulus Frequency Synhesizer A block diagram for a dual modulus frequency synhesizer is shown. (a.) If his synhesizer divides he VCO oupu by N1 every K VCO cycles and by N for he res of he ime, express he oupu frequency, u, as a funcion of N, K, and. (b.) If you waned o use his frequency synhesizer o generae an oupu frequency of MHz from a reference frequency of 100kHz, wha would be he value of N and how many cycles ou of 100 would you divide by N1 where he remaining cycles you would divide by N? Soluion (a.) The average divide facor is expressed as N eff = (N1)xuy cycle for N1 Nxuy cycle for N PLL N,N1 Modulus Conrol u F00FE01 1 = (N1) K N 1 1 K = N1 K f ou = N eff = N 1 K f ref (b.) ividing MHz by 100kHz gives Therefore, choose N = 271 and divide by N1 or 272 for 35 cycles ou of 100 and by N for he remaining 65 cycles. Thus, N = 271 and K = 35 cycles for every 100 cycles Lecure 170 Frequency Synhesizers I (6/25/03) Page FracionalN Frequency Synhesizer The oupu frequency can be finer han because division raio in he feedback loop does no have o be an ineger. Operaion: Make he division raio alernae beween N or N 1 in a conrolled and repeiive fashion o average an inermediae value beween N and N 1. For example, assume ha he synhesizer divides by N 1 every L cycles and by N he res of he ime. The average division raion is N aver = N 1 L. Therefore, 1 = (N1) L N 1 1 L f ref = N 1 L f ref FracionalN Techniques: Technique Feaure Problem AC phase esimaion Cancel spurs by AC Analog mismach Random Jiering Randomize divider Frequency jier Σ modulaion Modulae he divider raio Quanizaion noise Phase inerpolaion Inheren fracional divider Inerpolaion jier Pulse generaion Inser pulses Inerpolaion jier PF LPF VCO k mbis ivide by N or N1 Overflow mbi Accumulaor Fig

10 Lecure 170 Frequency Synhesizers I (6/25/03) Page A 1 GHz FracionalN Frequency Synhesizer Block diagram: PF/CP LPF Mulimodulus Prescaler N2, N1, N, N1, N2, N3 LC VCO Buffer Oupu Conrol nbis N2 N1 N N1 N2 N3 Mode Conrol Logic C 1 C 2 1 C 3 2 ab ab ab Fig Experimenal Resuls: Carrier Phase Noise, Phase Noise, Phase Noise, Phase Noise, Phase Noise, Frequency 10kHz offse 100kHz offse 200kHz offse 600kHz offse 1MHz offse 972 MHz 83.1dBc/Hz 104.1dBc/Hz 110dBc/Hz 188dBc/Hz 122.4dBc/Hz 916MHz 84.6dBc/Hz 104.4dBc/Hz 110.4dBc/Hz 118.2dBc/Hz 122.7dBc/Hz Sideband spurs < 70dBc, power supply range of 2.7 o 4.5V (5.2mA a 3V), uning range 0.881GHz Lecure 170 Frequency Synhesizers I (6/25/03) Page A LowNoise, 1.6 GHz CMOS Frequency Synhesizer A CMOS PLL used o design he fronend RF funcion of frequency synhesizer. Block iagram: = 61.5MHz PF Charge Pump Loop Filer LC VCO ivide by 1/26 Circui iagram of he LC Oscillaor: C Tune L 1 M1 V Bias M3 M2 I SS V L 2 C var C AC CTune C AC C var R R To Loop Filer Fig Performance: Power supply 2.7V o 5V Power dissipaion a 3V is 90mW Phase noise of 105dBc/Hz a 200kHz offse Tuning range of 1.6GHz±100MHz 1.5mm2 in 0.6µm CMOS echnology Fig J.Parker and.ray, A LowNoise 1.6 GHz CMOS PLL wih OnChip Loop Filer, Proc. of 1997 Conf. on Cusom Inegraed Circuis, May 1997.

11 Lecure 170 Frequency Synhesizers I (6/25/03) Page Comparison of Recen CMOS VCO Noise Resuls Auhor Craninckx, Seyar, ISSCC95 Rael, Abidi, ISSCC96 Souyer, ISSCC96 Thamsirianu, CICC94 Weigand, ISCAS94 Parker, Ray, CICC97 Power issipaion P Frequency f 0 Phase Noise o Carrier Raio Offse Freq. (f) Esimaed Open Loop Q 1.8 GHz 85dBc 10kHz 10 4x mW@3V 900MHz 100dBc/Hz 100kHz 4 1.7x mW@3V 4GHz 106dBc/Hz 1MHz 7 1.2x mW@3V 900MHz 93dBc/Hz 100kHz 1 (Class B ring osc.) 0.3x mW@3V 1GHz 85dBc/Hz 100kHz 1 (Class A ring osc.) 2.5x mW@3V 1.6GHz 105dBc/Hz 200kHz 7 0.6x1015 Park, CICC98 17mW@3V 980MHz 109dBc/Hz 200kHz 8 0.2x1015 Phase Noise Carrier Ampliude = K f 0 0 f 2 1 PQ K 0 Lecure 170 Frequency Synhesizers I (6/25/03) Page IVIERS FOR FREQUENCY SYNTHESIZERS Inroducion We have seen ha in he previous maerial ha dividers can be eiher fixed or programmable. In his secion we will focus on circuis and conceps suiable for fixed, ineger and fracionaln dividers. In addiion, we shall consider noiseshaping echniques using delasigma mehods applied o he fracionaln echnique.

12 Lecure 170 Frequency Synhesizers I (6/25/03) Page Fixed ividers ToggleFlipflop based divideby2: v osc v osc Q Q v div v div ToggleFlipflop v osc Flipflop Implemenaion: Proper sizing of he ransisors resuls in reasonable powerspeed radeoffs a GHz raes. evice mismaches can resul in phase imbalances as large as 5. If he inpu is no perfecly differenial, addiional phase unbalances can occur. R L M1 Fig V RL M2 M4 M5 Q Q M3 M6 Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page ual Modulus ividers Evoluion of a divideby2/3 from a divideby3 circui: Q Q 1 1 G Q G 1 FF 1 FF 2 Q 2 Q G Q 2 Fig ivideby2/3 circui (MC=1 2, MC=0 3): N=3 Q FF 1 Q 1 G 1 G FF 2 Q Q 2 Q 1 G MC Fig Q 2 N=2

13 Lecure 170 Frequency Synhesizers I (6/25/03) Page ual Modulus ividers Coninued Sae diagram of he divide by 2/3 circui: MC=0 "1" Q 1 Q 2 :00 Q 1 Q 2 :01 2/3 decision poin "X" "1" "0" Q 1 Q 2 :01 "X" Q 1 Q 2 :11 Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page Speed of he ual Modulus ivider The divideby3 circuis are generally much slower han heir dividebywo counerpars. Consider he implemenaion of par of he previous divideby2/3 circui. G 1 V V FF2 R L RL R L RL Q 2 Q2 M1 M2 M1 M2 M4 M5 M3 M3 M6 Fig On he clock edge where Q 2 mus change, sufficien ime mus be allowed for he delay of he AN gae, G 1, and he inpu sage of FF2 before he nex clock ransiion. I is seen ha he delay for 3 circui is nearly wice ha of he 2 circui.

14 Lecure 170 Frequency Synhesizers I (6/25/03) Page Programmable ividers A divider can be achieved by using a programmable couner. Preload Inpu (= division raio M) Preload Enable Clock (= ) Programmable Couner, N 2 Maximum coun = N 2 Couner Oupu (= f divide ) For a given speed requiremen, a programmable Fig divider is less power opimized because he criical pah is dependen on he loaded value. A complee divider consising of a fixed divider cascaded wih a programmable divider. fo Fixed Couner N 1 f inermediae Programmable Couner N 2 Max. coun = N 2 (max) f divide Power is high, power can be opimized Power is low, power canno be opimized Fig Resoluion (Complee divider) = Resoluion (programmable divider) x ivision raio (fixed divider) Lecure 170 Frequency Synhesizers I (6/25/03) Page Waveforms of Various Complee ividers N 1 = 3 and N 2 = 4: f inermediae N 1 = 3 and N 2 = 3: 12 f f divide = /12 divide Fig f inermediae f f divide = /9 divide Fig

15 Lecure 170 Frequency Synhesizers I (6/25/03) Page Waveforms of Various Complee ividers Coninued N 1 = 3/4 (N 1 = 4 for one N 2 cycle) and N 2 = 3: f inermediae f divide 10 f divide = /10 Fig N 1 = 3/4 (N 1 = 4 for wo N 2 cycles) and N 2 = 3: f inermediae f f divide = /11 divide Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page MuliModulus ividers 4/ 5 dual modulus couner example: MC Q1 Q d2 d0 d1 Q f 4, 5 Q Q3 Q2 Sae iagram: Pah B X /5 decision poin X Pah A 0 1 Pah B X Fig f ps Fig Noe ha here are wo possible sae pahs A and B each consising of wo sequences, a 4 sequence and a 5 sequence. For pah A, he 4 sequence is from 000, 001,011, 010, 000 and he 5 sequence is from 000, 001, 011, 010, 100, 000. For pah B, he 4 sequence is from 000, 001, 011, 110, 000 and he 5 sequence is from 000, 001, 011, 110, 100, 000.

16 Lecure 170 Frequency Synhesizers I (6/25/03) Page NOISE SHAPING TECHNIQUES elasigma Shaping Techniques elasigma modulaors can be used along wih mulimodulus dividers o achieve noise shaping of phase noise. The objecive of he delasigma modulaor is o remove he noise due o he flucuaion of he mulimodulus dividers. The following slides review his echnique as applied o frequency synhesizers. Analog implemenaion of a firsorder delasigma modulaor: x() Inegraor 1bi quanizer y(nt) 1bi AC Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page igial Implemenaion of he elasigma Modulaor Inpu, k mbis Clock 1bi mbis mbis Oupu Residue, R F(z) z1 z1 1bi quanizer A(z) m Y(z) 2 m 0 Q(z) A(z) Y(z) Fig The discree firsorder delasigma modulaor can be implemened wih an mbi accumulaor. The mbi accumulaor has m inpu bis, a single oupu bi (carrybi or MSB), and mresidue bis. Operaion: On every cycle of he reference clock, he residue oupu R of he accumulaor is assigned he value Rk afer one cycle if an overflow does no occur or he value Rk2 m if he accumulaor produces a carrybi signal. Therefore, he accumulaor overflow is equivalen o he comparaor decision. The daa sored in he accumulaor is essenially he inegral of he error beween he desired frequency daa k and he acual frequency conrol inpu.

17 Lecure 170 Frequency Synhesizers I (6/25/03) Page HighOrder elasigma Modulaors zransform of a firsorder delasigma modulaor: Q(z) Inpu F(z) 1 1z1 Y(z) z1 nh order delasigma modulaor: f(n) Fig FirsOrder Sigma ela Modulaor y 1 (n) Q(z) q 1 (n) FirsOrder Sigma ela Modulaor y 2 (n) Bi Manipulaion q 2 (n) FirsOrder Sigma ela Modulaor y 3 (n) Circuiry y(n) Fig q N (n) FirsOrder Sigma y N1 (n) ela Modulaor Lecure 170 Frequency Synhesizers I (6/25/03) Page Use of a Modulaor for ivider Conrol Consider he secondorder delasigma modulaor implemened wih mbi accumulaors: 1 Adder 1 1 y(n) Bi Manipulaion Circuiry Inpu, k mbis mbis Residue, R mbis mbis Residue, R mbis Fig mbis

18 Lecure 170 Frequency Synhesizers I (6/25/03) Page Use of a Modulaor for ivider Conrol Coninued zranform model for he previous secondorder delasigma modulaor: Q 1 (z) Inpu F(z) 1 1z1 Y 1 (z) Y(z) z1 Q 1 (z) Q 2 (z) 1 z1 1z1 Y 2 (z) Fig From he above diagram, we can wrie, Y 1 (z) = F(z) (1z 1 )Q 1 (z) and Y 2 (z) = Q 1 (z)(1z 1 ) Q 2 (z)(1z 1 ) 2 can be combined o give, Y (z) = F(z) Q 2 (z)(1z 1 ) 2 Generalizing o he nh order gives, Y (z) = F(z) Q n (z)(1z 1 ) n z1 Lecure 170 Frequency Synhesizers I (6/25/03) Page Use of a Modulaor for ivider Conrol Coninued The effecive divide raio of a fracional divider implemened wih an nh order delasigma modulaor can be wrien as, N eff = N(z) Y(z) = N(z) F(z) Q n (z)(1z 1 ) n where N(z) = ineger par of he divide raio F(z) = fracional par of he divide raio Q(z) = quanizaion noise occurring a he nh delasigma modulaor If he PLL is in lock, hen = N eff = [N(z) F(z)] (1z 1 ) n Q n (z) where he firs erm is he desired frequency and he second erm represen he frequency flucuaion resuling from he quanizaion noise in he fracional modulaor.

19 Lecure 170 Frequency Synhesizers I (6/25/03) Page Use of a Modulaor for ivider Conrol Coninued Assume ha he quanizaion noise is a random quaniy in he inerval {0.5, 0.5 } wih equal probabiliy. If he quanizer is 1bi, hen which is he quanizaion sep size is 1. The noise power or variance, σ e 2, can be found as 0.5 σ e 2 = E(e) = 1 e 2 de = The specrum of he quanizaion noise is where N(f) is given as, N(f) = 2 12 where is he sampling frequency which is equal o he comparison frequency of he PF. N(f) f Fig Lecure 170 Frequency Synhesizers I (6/25/03) Page Use of a Modulaor for ivider Conrol Coninued efine f(z) as he frequency noise of flucuaion of he oupu frequency (z). The power specral densiy, S f(z), can be calculaed from he second erm of he previous expression for (z). S f(z) = (1z 1 ) n = (1z 1 ) n = (1z 1 ) f 2n ref 12 Because phase is relaed o frequency hrough inegraion, he phase noise, θ n (), is θ n () = 2π f()d Using a simple recangular inegraion in he zdomain yields, 2π f(z) Θ n (z) = (1z 1 ) The power specral densiy of he phase noise, S Θn (z), can be wrien as, S Θn (z) = Θ n (z) 2 (2π) 2 S f(z) = f 2 ref 1z 1 2 S f(z) = (2π)2 1z 1 2(n1) 12 f rads 2 /Hz ref Assuming S Θn (f) is a wosided power specral densiy funcion gives L(f) = S Θn (f) L(f) = (2π)2 12 f πf 2(n1) ref 2sin rads 2 /Hz where z 1 has been replaced wih e j2πf/ and n is he order of he modulaor.

20 Lecure 170 Frequency Synhesizers I (6/25/03) Page Use of a Modulaor for ivider Conrol Coninued Prediced phase noise of higherorder modulaors (f sample = 12.8 MHz): Lecure 170 Frequency Synhesizers I (6/25/03) Page Use of a Modulaor for ivider Conrol Coninued Resuls: If a modulaor has an accumulaor inpu daa k consising of m bis, hen he oscillaor oupu frequency,, can be given as, = N k 2 m The uncerainy of his frequency will be reduced by he use of he sigmadela modulaor. Summary: The delasigma modulaor aenuaes phase noise from he facional conroller o negligible levels close o he cener frequency. Furher from he cener frequency, he phase noise increase rapidly and mus be filered ou prior o uning he inpu of he VCO. The loop filer in he PLL is used o filer he noise away from he cener frequency. When a higherorder, delasigma modulaor is used for a fracionaln conroller, he PLL needs more poles in he loop filer o suppress he quanizaion noise a high frequencies.

21 Lecure 170 Frequency Synhesizers I (6/25/03) Page SUMMARY Examine he applicaions of PLLs 1.) emodulaion and modulaion 2.) Signal condiioning 3.) Frequency synhesis 4.) Clock and daa recovery 5.) Frequency ranslaion Inegraed Circui Frequency Synhesizers Archiecures and Techniques Fracional N ividers/prescalers Noise shaping echniques

LECTURE 1 CMOS PHASE LOCKED LOOPS

Lecure 01 (8/9/18) Page 1-1 Objecive LECTURE 1 CMOS PHASE LOCKED LOOPS OVERVIEW Undersand he principles and applicaions of phase locked loops using inegraed circui echnology wih emphasis on CMOS echnology.