ADC Modeling for System Simulation

Transcription

1 Linköping Sudies in Science and Technology Thesis No. 07 ADC Modeling for Sysem Simulaion Kalle Folkesson LiU-TEK-LIC-003:6 Deparmen of Elecrical Engineering Linköpings universie, SE Linköping, Sweden Linköping 003 ISBN ISSN

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3 Absrac Modern sysem design mehods are based on early sysem simulaion using behavioral models. Since he ADC ofen is he criical componen i is especially imporan ha i is modeled correcly. Mos curren design environmens use very simple ADC models such as ideal sampling and quanizaion o give a cerain effecive number of bis (ENOB). The ENOB is ypically found by a single-one es where he inpu is an ampliude-limied sine wave. Real applicaions may have inpus very differen from his simple es signal and he ADC can hen have a compleely differen performance. Deailed knowledge of he behavior in a sysem allows he ADC design margin o be minimized hus saving cos and power consumpion. In he work included in his hesis an accurae model of a successiveapproximaion ADC is developed. I is aimed for inegraion ino exising sysem simulaors and can hus no be oo complex or he simulaion ime will be unreasonably long. Measuremens are performed o validae he model and comparisons beween simulaed and measured daa are done in boh ime and frequency domains. This is used o es some error hypoheses in order o find he performance limiing errors of he successive-approximaion archiecure. Furher, he need for accurae ADC models in sysem simulaion is invesigaed. A complex model is of no use if he same informaion can be obained wih a simple one. To do his, he ADC model is inegraed in wo differen sysems: an ADSL modem and a radar receiver. Sysem simulaions are performed and he resuls are compared o he case when a simple ADC model is used. In boh cases he accurae ADC model iii

4 iv showed o be useful. Sysem performance varied quie much for ADCs wih he same specified performance in erms of ENOB depending on which error mechanism was acive.

5 Preface This hesis presens he par of my research a he Elecronic Devices group, Deparmen of Elecrical Engineering a Linköping Universiy from December 998 o December 00 ha concerns ADC modeling. The following papers are included: K. Folkesson, J.-E. Eklund, C. Svensson, and A. Gusafsson, A MATLAB-Based ADC Model for RF Sysem Simulaions, in Proceedings of he Swedish Naional Symposium on GigaHerz Elecronics, pp , Mar. 000 K. Folkesson, J.-E. Eklund, and C. Svensson, Modeling of Dynamic Errors in Algorihmic A/D Converers, in Proceedings of he Inernaional Symposium on Circuis and Sysems, pp , May 00 J. Elbornsson, K. Folkesson, and J.-E. Eklund, Measuremen Verificaion of Esimaion Mehod for Time Errors in a Time- Inerleaved A/D Converer Sysem, in Proceedings of he Inernaional Symposium on Circuis and Sysems, vol. 3, pp. 9-3, May 00 K. Folkesson, J.-E. Eklund, and C. Svensson, Relevance of Using Single-Tone Tess o Characerize ADCs for ADSL Modems, in Proceedings of NORCHIP, pp. 4-9, Nov. 00 v

6 vi K. Folkesson and C. Svensson, An Accurae ADC Model in Radar Sysem Simulaion, o be presened a he Inernaional Workshop on ADC Modelling and Tesing, Sep. 003 Relaed, bu no included papers are: S. Brodén, M. Danesig, K. Folkesson, H. Ohlsson, B. Svensson, and A. Åsröm, "Smar Sensors", in Proceedings of RVK99, Jun. 999 A. Gusafsson, K. Folkesson, and H. Ohlsson, "A Simulaion Environmen for Inegraed Frequency and Time Domain Simulaions of a Radar Receiver", in Proceedings of he Swedish Naional Symposium on GigaHerz Elecronics, Nov. 00 R. Sander, B. Grelsson, S. Axelsson A.-M. Andersson, A. Gusafsson, K. Folkesson, and Henrik Ohlsson, CAD Model of a Radar Receiver, Wih Typical Radar Scenarios, in Combined ADS and MATLAB Environmen, submied o he Swedish Naional Symposium on GigaHerz Elecronics, 003

7 Acknowledgemens I would like o hank he following people My supervisor Professor Chriser Svensson for his guidance, suppor, and paience. My co-supervisor during he firs years, Dr. Jan-Erik Eklund. Henrik Ohlsson, Andreas Gusafsson, and Dr. Jonas Elbornsson for ineresing cooperaion. Roland Sander for a job well done on specificaion of radar applicaions. Lic. Eng. Darius Jakonis for ineresing discussions. Ruger Carlsson and Ara Alvandpour for fixing problems relaed o ools and compuers. Thank you also Maias Arvidsson for showing me a slighly less supid mehod o inser picures in Word. Ingegärd Andersson and Anna Folkeson for help wih adminisraive suff. A big hank you goes o Lic. Eng. Daniel Eckerber for miscellaneous echnical suppor hough he has more han enough vii

8 viii work of his own, no o menion everyhing he does for oher people... Lic. Eng. Henrik Eriksson for proof reading his hesis. Lic. Eng. Daniel Wiklund for sharing my passion for sushi and puns. I would like o hank all pas and presen members of he Elecronic Devices group for creaing a nice working environmen, especially Sefan Andersson and Peer Capua, Lic. Eng. Ulf Nordquis, Dr. Tomas Henriksson, and Professor Dake Liu, and Professor Per Larsson-Edefors. The Swedish Foundaion for Sraegic Research (SSF) for sponsoring his work hrough he Smar Sensors projec. Kalle Folkesson

9 Abbreviaions A/D ADC ADSL DAC DMT DNL ENOB FMCW INL LSB MSB OFDM QAM SA-ADC SFDR SNDR SNR T/H THD VLSI Analog-o-Digial Analog-o-Digial Converer Asymmeric Digial Subscriber Line Digial-o-Analog Converer Discree Muli-Tone Differenial Nonlineariy Effecive Number Of Bis Frequency-Modulaed Coninuous Wave Inegral Nonlineariy Leas Significan Bi Mos Significan Bi Orhogonal Frequency Division Muliplex Quadraure Ampliude Modulaion Successive-Approximaion Analog-o-Digial Converer Spurious-Free Dynamic Range Signal-o-Noise-and-Disorion-Raio Signal-o-Noise-Raio Track-and-Hold Toal Harmonic Disorion Very Large Scale Inegraion ix

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11 Conens Absrac...iii Preface... v Acknowledgemens... vii Abbreviaions... ix I Inroducion... Inroducion Background ADC Applicaions ADSL Radar Conribuions References... 6 ADC Archiecures Inroducion Flash Pipelined Successive-Approximaion....5 Inegraing....6 Sigma-Dela... 3 xi

12 xii.7 Subranging Inerleaving Summary References ADC Characerizaion Inroducion DC Specificaions INL DNL Dynamic Specificaions SNR SNDR ENOB SFDR THD References Error Correcion Error Correcion Correcion of Time-Inerleaved Srucures References... 6 II ADC Modeling ADC Modeling Survey ADC Modeling ADC Behavioral Modeling Saic Modeling Dynamic Modeling References An ADC Model for Sysem Simulaion Inroducion Model Descripion Fuure Work References... 4

13 III Papers xiii 7 Paper Inroducion Errors in ADCs ADC Model Measuremens Conclusions Paper Inroducion The ADC Dynamic Errors The Model Measuremens and Simulaions Conclusions References Paper Inroducion Theory Noaion Time error esimaion mehod Correcion Through inerpolaion Time Error Disorion Measuremens Measuremen seup Daa acquisiion Evaluaion Conclusions References Paper Inroducion Model Descripions ADSL Model ADC Model Simulaions... 80

14 xiv 0.3. Simulaion Seup Simulaion Resuls Conclusions References Paper Inroducion Model Descripions Radar Model ADC Model Simulaions Simulaion Seup Simulaion Resuls Conclusions References IV Appendix A ADC Equaions A. SNR A. Jier B Model Equaions... 0 B. Calculae Seled Reference Volage... 0 B. Calculae Seled Sampled Inpu Volage B.3 Calculae Comparaor Oupu Volage... 06

15 Par I Inroducion

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17 Inroducion. Background Analog-o-digial converers (ADCs) are key componens in signal processing sysems such as communicaion applicaions and radar. As he advances in VLSI echnologies allow more and more circuiry o be inegraed on one chip, he ADCs become jus cells in more complex circuis or sysems on chip. Hence, esing sand-alone ADCs is becoming less relevan []. Also in simulaion, he ADC should be pu in an applicaion. Modern design mehods are based on early sysem simulaion using behavioral models []. I is pracical o simulae analog pars in frequency domain and digial pars in ime domain bu mos curren design environmens focus on one of hese and hus canno efficienly handle boh analog and digial pars. The ADC models included in sysem simulaors are ofen very simple such as ideal sampling and quanizaion o give a cerain effecive number of bis (ENOB). Real ADCs on he oher hand have many errors apar from he quanizaion error [3]. Anoher issue is ha he ENOB number used for characerizaion is found by performing a single-one es [4]. In his es, he oupu is analyzed when he inpu is a full-scale sine wave. For oher inpus, he performance can be very differen so he specified ENOB is no valid for an arbirary applicaion [5]. ADCs normally have a significan impac on sysem performance and o ensure ha he sysem will perform according o he specificaions, he ADC is ofen over- 3

18 4 Inroducion specified o compensae for errors no included in he model. This makes he sysem unnecessarily complex and expensive. One mehod o find suiable ADC requiremens and hereby avoid cosly over-specificaion is o perform sysem simulaions using an accurae ADC model which includes all performance limiing errors. I is also ineresing o perform simulaions o find ou which error mechanism is performance limiing in a cerain applicaion. Errors in ADCs are archiecure dependen so wih his sraegy suiable archiecures can be found as well as knowledge on where o pu he design effor. Deerminisic errors can easily be correced, bu random ones are more difficul o handle. Since some mechanisms, such as mismach, can cause eiher deerminisic or random errors depending on he applicaion, his is also useful o simulae.. ADC Applicaions In mixed-signal design i is desirable o implemen as much as possible in he digial par since his gives more efficien signal processing and inegraion as well as increased flexibiliy. Because of his, funcions ha radiionally have been performed in he analog domain are moved o he digial. If a funcion of an analog componen ha relaxes he ADC requiremens, e.g. a mixer, is moved o he digial domain, he ADC requiremens will, of course, increase. Because of his, he ADC ofen becomes he boleneck. As discussed in he previous secion, ADCs are normally specified in erms of ENOB, which is relaed o a specific inpu. I is herefore of ineres o invesigae applicaions wih oher ypes of inpus o see how he ENOB characerizaion holds. To be relevan, i should give he same sysem performance no maer which error mechanism is acive in he ADC. Inpu signals and imporan ADC properies for applicaions used in his hesis are briefly presened in he following secions. The applicaions are presened wih a lile more deail in he papers hey are used; secion 0 for ADSL and secion for radar... ADSL In an ADSL applicaion, he ADC inpu is a discree muli-one (DMT) signal. I consiss of 56 sine waves wih differen modulaion. These 56 channels are individually QAM modulaed wih o 5 bis depending on he signal-o-noise-and-disorion raio (SNDR) of each

19 .3 Conribuions 5 channel. The higher he SNDR in a channel, he more bis will be assigned o i. This way, all channels can be fully uilized. Since any noise or disorion will degrade he sysem performance, he mos imporan ADC characerisic for his applicaion is SNDR... Radar The ADC inpu in a frequency-modulaed coninuous wave (FMCW) radar applicaion consiss of muliple sine waves represening differen arges. The signal power levels vary quie much depending on he srucure of and disance o he corresponding arge. The combinaion of muliple signals and he possible large difference in heir power levels ses very ough requiremens on he ADC. If a signal has a large enough power, i is recognized as a arge. Spurious signals, such as harmonic disorion, will hus appear as false arges if heir power is above he deecion hreshold. For his ype of radar, he spurious-free dynamic range (SFDR) limis he performance since i is a measure on how well i can deec weak signals in he presence of srong inerfering signals such as closer arges. Noise is no a big problem as long as i is below he deecion hreshold. Hence, he mos imporan ADC characerisic is SFDR..3 Conribuions The main conribuions of his hesis are: Developmen and validaion of an accurae model of a successiveapproximaion ADC (SA-ADC) aimed for sysem simulaion. Moivaing he use of accurae ADC models in sysem simulaion. This secion gives a shor summary of he conens of each paper. Uncerainy in sampling insan, jier, is one of he mos imporan dynamic limiaions [3]. For high inpu frequencies i will limi he performance of an ADC. In he firs paper [6], an ADC model o model jier behavior is developed. I is validaed by comparisons o measured daa and is inegraion in an RF sysem simulaor, Agilen ADS, is demonsraed.

20 6 Inroducion In he second paper [7], he model is expanded o include more errors and is more horoughly validaed wih measuremens in boh ime and frequency domains. The model was used o invesigae he imporance of various dynamic error mechanisms in SA-ADCs. The successive-approximaion archiecure suffers from low hroughpu and o be of use in high-frequency applicaions, a imeinerleaved srucure has o be used. Inerleaving, however, inroduces errors and o keep he performance hese have o be correced. Therefore, o moivae he use of SA-ADCs, some work on error correcion of imeinerleaved srucures is included. To suppor Jonas Elbornsson in he validaion of his error esimaion algorihm developed in [8], some measuremens on ime-inerleaved ADCs were performed. The resuls presened in [9] shows ha he signal qualiy is improved afer correcion based on esimaes using his mehod. The deailed knowledge of dominaing error mechanisms in SA-ADCs gained in [7] was hen used o invesigae heir effecs on sysem behavior [0], []. For an ADSL applicaion, [0], and a radar applicaion, [] i was shown ha ADCs wih he same specified performance in erms of ENOB gave very differen sysem performance depending on which error mechanism was dominaing in he ADC. These resuls moivae he use of accurae ADC models in sysem simulaion..4 References [] G. Chiorboli and C. Morandi, ADC Modeling and Tesing, in Proceedings of he IEEE Insrumenaion and Measuremen Technology Conference, vol. 3, pp , May 00 [] G. G. E. Gielen and R. A. Ruenbar, Compuer-Aided Design of Analog and Mixed-Signal Inegraed Circuis, in Proceedings of he IEEE, vol. 88, no., Dec. 000 [3] R. Walden Analog-o-Digial Converer Survey and Analysis, in IEEE Journal on Seleced Areas in Communicaions, vol. 7, no. 4, pp , Apr. 999 [4] T. E. Linnenbrink, S. J. Tilden, and M. T. Miller, ADC Tesing Wih IEEE Sd 4-000, in Proceedings of he IEEE Insrumenaion and Measuremen Technology Conference, pp , May 00 [5] T. E. Linnenbrink, Effecive Bis: Is Tha All There Is?, in IEEE Transacions on Insrumenaion and Measuremen, vol. IM-33, no. 3, Sep. 984

21 .4 References 7 [6] K. Folkesson, J.-E. Eklund, C. Svensson, and A. Gusafsson, A MATLAB-Based ADC Model for RF Sysem Simulaions, in Proceedings of he Swedish Naional Symposium on GigaHerz Elecronics, pp.73-76, Mar. 000 [7] K. Folkesson, J.-E. Eklund, and C. Svensson, Modeling of Dynamic Errors in Algorihmic A/D Converers, in Proceedings of he Inernaional Symposium on Circuis and Sysems, pp , May 00 [8] J. Elbornsson and J.-E. Eklund, Blind Esimaion of Timing Errors in Inerleaved AD Converers, in Proceedings of ICASSP 00, vol. 6, pp , 00 [9] J. Elbornsson, K. Folkesson, and J.-E. Eklund, Measuremen Verificaion of Esimaion Mehod for Time Errors in a Time- Inerleaved A/D Converer Sysem, in Proceedings of he Inernaional Symposium on Circuis and Sysems, vol. 3, pp. 9-3, May 00 [0] K. Folkesson, J.-E. Eklund, and C. Svensson, Relevance of Using Single-Tone Tess o Characerize ADCs for ADSL Modems, in Proceedings of NORCHIP, pp. 4-9, Nov. 00 [] K. Folkesson and C. Svensson, An Accurae ADC Model in Radar Sysem Simulaion, o be presened a he Inernaional Workshop on ADC Modelling and Tesing, Sep. 003

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23 ADC Archiecures. Inroducion An ADC produces a digial code o represen an analog inpu. The analog-o-digial (A/D) conversion is always based on comparisons beween he analog inpu signal and known reference levels bu here are many differen approaches o perform hese, each wih is own advanages and disadvanages. In his secion he mos common ADC archiecures are presened in heir simples form. More informaion can be found in []-[7]. Some examples of commercially available sae-ofhe-ar ADCs are presened in secion.9.. Flash The flash archiecure is he fases mehod o conver an analog signal o a digial one. All oupu bis are calculaed in one clock cycle using parallel comparaors as shown in figure.. A volage divider is used o generae he reference volages for he comparaors. The comparaor oupus will be up o he reference closes below he analog inpu and hen 0 hus creaing a hermomeer code. This is hen decoded o he digial oupu code. An n-bi converer requires n comparaors. This means an exponenial growh in size and power dissipaion for increasing number of bis. The componen maching requiremens also double for 9

24 0 ADC Archiecures V ref in Decoder... ou V ref- Figure.. Flash ADC block diagram. every addiional bi, which limis he useful resoluion of a flash converer o 8-0 bis. Low-resoluion converers can achieve sample raes of a few GS/s. The flash is ypically used in high-frequency applicaions ha canno be addressed any oher way and where high precision is no very imporan. Examples are poin-o-poin radio links and sampling oscilloscopes..3 Pipelined The pipelined archiecure overcomes he limiing facors of he flash by dividing he conversion ask ino several sages. I consiss of a number of sages each including rack-and-hold (T/H), low-resoluion ADC and DAC, summing circui, and an amplifier o provide iner-sage gain. A block diagram is shown in figure.. If -bi converers are used, he firs sage is a coarse -bi ADC ha calculaes he MSB. The MSB is hen convered back o an analog volage by he -bi DAC. The difference beween he analog inpu and he analog represenaion of he MSB is sen o he nex sage in he pipeline afer a muliplicaion by wo o compensae for he change in significance level. Using he pipelined archiecure, i is possible o achieve higher resoluion han wih he flash bu he oal conversion ime is increased o m clock cycles for an m-sage pipeline. However, since m samples are

25 .4 Successive-Approximaion S/H - ADC DAC in T/H Sage Sage Sage m ou Figure.. Pipelined ADC block diagram. processed simulaneously, he oal hroughpu is he same as for a flash. The difference is only a laency of m cycles. Also, due o he more complex design ha requires a longer seling ime, i is no possible o design i o be as fas as a flash. The pipelined ADC has a good balance beween size, speed, resoluion, and power dissipaion and has herefore become he mos popular archiecure for applicaions where a high sampling rae as well as high resoluion is needed, e.g. digial video and communicaion sysems such as radio base saions and ADSL modems. The resoluion ypically ranges from 8 o 6 bis wih sampling raes of a few MS/s for he higher resoluions and up o a couple of hundred MS/s for he lower..4 Successive-Approximaion While he flash converer uses many comparaors o do he conversion in one clock cycle, he successive-approximaion converer (SA-ADC) does he exac opposie. Here, he conversion is performed using one single converer in many clock cycles o make he successive approximaions of a binary search. The block diagram is shown in figure.3. Basically i consiss of a DAC in a feedback loop. For each sep in he binary search, a comparison is made beween he inpu and a reference level. The logic block updaes he oupu regiser depending on he oucome of he comparison and selecs he appropriae reference level o be generaed by he DAC for he comparison in he nex significance level. An n-bi conversion is performed in n clock cycles and, as for he flash and pipelined converers, he componen maching requiremens doubles for

26 ADC Archiecures in V ref, i Logic Regiser ou... DAC Figure.3. Successive-approximaion ADC block diagram. each addiional bi. The resoluion ypically ranges from 8 o 8 bis a sampling speeds up o 5 MS/s. Since he laency of he SA-ADC is only one sampling cycle (however many cycles of he inernal clock), a conversion can be sared a any ime. This makes he SA-ADC suiable for applicaions wih nonperiodic inpus. I is ideal o conver muliplexed signals. For e.g. a pipelined archiecure, which has longer laency, a delay of a leas he laency mus be added o avoid inerference of he muliplexed signals. The suiabiliy o conver muliplexed signals is crucial also for simulaneous conversion of muliple signals in one ADC. This is necessary if here is phase informaion beween differen channels, as e.g. for I and Q channels. The simulaneous conversion can be performed by using muliple T/H o sample he signals a he same ime insan and hen use a muliplexing scheme for he quanizaion. The low laency also allows he SA-ADC o be urned off when no conversion is needed. Hence, he power dissipaion scales wih he sample rae, while i for e.g. pipelined archiecures normally is consan. This makes he SA-ADC useful in low-power applicaions where he daa acquisiion is no coninuous e.g. PDAs (Personal Digial Assisans)..5 Inegraing A block diagram of an inegraing converer is shown in figure.4. The inpu signal is inegraed and compared o a known reference level. A couner couns he number of clock cycles i akes unil he inpu reaches he reference level and he comparaor oupu swiches. This ime is proporional o he inpu volage. The problem wih his approach is ha is dependen on he olerances of he R and C values of he inegraor. To solve his problem a dual-slope archiecure can be used. Then he inegraor has swiched inpus and charges wih he inpu for a known ime, charge, and discharges wih a known opposie-polariy reference

27 .6 Sigma-Dela 3 in Inegraor V in V ref Comparaor Couner... ou Figure.4. Inegraing ADC block diagram. volage, V ref, unil i reaches zero. The ime for discharge, discharge, is measures and he inpu can be calculaed as charge V in Vref. discharge Wih his echnique, any error inroduced by componen value imperfecion will be canceled ou during he discharge. The dual-slope converer has no problems wih exponenial increase of size and componen maching requiremens. The circuiry will no change for increasing resoluion. The conversion ime, however, increases exponenially. To double he resoluion, he resoluion of he ime measuremens has o double, which requires inegraion over wice as many clock cycles. An ineresing feaure of he inegraing archiecure is he abiliy o rejec unwaned signals. Using an inegrae cycle of T, all frequencies of n will inegrae o zero and hus be compleely T rejeced. The inegraion ime can hus be chosen o rejec unwaned frequencies. Inegraing ADCs ypically achieves resoluions of 6 bis, bu are very slow. The sample rae is only abou 00 S/s. Typical applicaions are insrumenaion, e.g. digial mulimeers. Due o is good noise rejecion i is useful in noisy indusrial environmens. Examples are digiizing oupus of srain gauges and hermocouples..6 Sigma-Dela The block diagram of a sigma-dela converer is shown in figure.5. The oupu from a -bi DAC is subraced from he inpu signal. The resuling signal is inegraed and hen fed o a comparaor, which convers i o a -bi digial oupu. This is hen used as inpu o he DAC,

28 4 ADC Archiecures in Diff. Amp. Inegraor Comparaor Dig. Fil.... ou DAC Figure.5. Sigma-dela ADC block diagram. which makes sure ha he average oupu from he inegraor is close o he reference level of he comparaor. This loop is run a an oversampled rae, much faser han he sample rae, and i produces a sream of ones and zeros from he comparaor oupu. The densiy of ones in he daa sream is proporional he inpu signal value. A digial filer performs low-pass filering and decimaion of he daa sream and generaes he digial oupu code. For an n-bi sigma-dela converer, a simple implemenaion of he digial filer is an n-bi couner. In real converers, however, he filers are much more advanced. One commonly used opology is he sinc 3. The sigma-dela makes use of wo principles o obain high resoluion: oversampling and noise shaping. Oversampling reduces he quanizaion noise by means of increasing he noise bandwidh. Anoher advanage wih he oversampling is ha i relaxes he requiremens for an exernal ani-aliasing filer. By summing he error volage, he inegraor has a noise shaping feaure. I acs as a low-pass filer for he inpu signal and as a high-pass filer for noise hus moving his up in frequency and ou of he used band. The oversampled noise-shaper effecively rades speed for accuracy. This means ha he sigma-dela does no have he ough requiremens on componen maching as he oher archiecures. Highresoluion converers can be designed wihou he need for precision analog elemens, which allow he sigma-delas o be implemened in sandard digial processes. This also gives i low power dissipaion. Typical resoluion is 4 bis. The high oversampling raio needed o obain his limis he sampling rae o abou 00 khz. Like pipelined converers, he sigma-delas have laency. Sigma-dela converers are used in low-frequency applicaions wih high resoluion requiremens such as voice-band communicaion and audio.

29 .7 Subranging 5 clk ADC clk ADC in.... clk m MUX ou ADC m clk sample quanize. clk clk m. sample.. sample Figure.6. Time-inerleaving of ADCs..7 Subranging Generaing many reference levels separaely requires many resisors, one per reference level, and will use much area. To save area, subranging can be used. This means ha he conversion is divided ino muliple seps. In he firs sep a coarse conversion is performed producing he MSBs. The difference beween he inpu and he analog represenaion of he MSBs is hen passed o he nex sage where anoher conversion is performed. If wo subranging sages wih n and n reference levels respecively are used, only n n resisors are needed o produce he equivalence of n n reference levels. Subranging is a par of he pipelined archiecure, bu i can also easily be implemened in SA-ADCs. If he subranges are chosen o overlap, here will be a redundancy ha can be used for error correcion..8 Inerleaving The sampling rae of a sysem can be increased by using several imeinerleaved ADCs [8]. A higher sampling rae is obained a he cos of more hardware by running he ADCs in parallel, bu a differen clock phases, see figure.6. Thereby he requiremens on each ADC is relaxed

30 6 ADC Archiecures bis inegraing sigma-dela pipelined successiveapproximaion flash Figure.7. Performance of ADC archiecures. f s (log) since he ime available for conversion is increased by a facor of m -, where m is he number of ime-inerleaved ADCs. The sampling, however, sill has o be performed a full speed. Ideally, m imeinerleaved converers will have he same performance as one converer bu a m imes higher sampling frequency. In a real case, here are some problems ha arise when ime-inerleaved ADCs are used. Mismach in gain, offse, and phase beween he ime-inerleaved channels will cause errors ha have o be correced o make full use of he gained performance. To be able o ime inerleave ADCs, a division of he clock signal is also necessary..9 Summary Figure.7 summarizes he relaive performance in resoluion and speed for he discussed archiecures and some examples of sae-of-he-ar ADCs are shown in able..

31 .0 References 7 Table.. Sae-of-he-ar ADCs. Number of Bis Sampling Rae [MS/s] Archiecure Manufacurer flash Maxim [9] 0 0 flash Analog Devices[0] 0 pipelined Analog Devices[] 4 80 pipelined Analog Devices[] SA-ADC Analog Devices[3] Sigma-dela Analog Devices[4].0 References [] R. van de Plassche, Inegraed Analog-o-Digial and Digial-o- Analog Converers, Kluwer Academic Publishers, 994 [] Maxim, The ABCs of ADCs: Undersanding Flash ADCs, hp:// May 003 [3] Maxim, Undersanding Pipelined ADCs, hp:// May 003 [4] Maxim, Undersanding SAR ADCs hp:// May 003 [5] Maxim, Undersanding Inegraing ADCs, hp:// May 003 [6] Maxim, Demysifying Sigma-Dela ADCs, hp:// May 003 [7] Analog Devices, Analog-o-Digial Converer Archiecures and Choices for Sysem Design, hp:// May 003 [8] Black W. C. and Hodges D. A. Time Inerleaved Converer Arrays. IEEE Journal of Solid-Sae Circuis, vol. SC-5, no. 6, pp. 0-09, Dec 980 [9] Maxim, MAX08 8-bi,.5 GS/s ADC daa shee, hp://pdfserv.maxim-ic.com/arpdf/max08.pdf, 00 [0] Analog Devices, AD940 0-bi, 0 MS/s ADC daa shee, hp:// 40_0.pdf, 000

32 8 ADC Archiecures [] Analog Devices, AD9430 -bi, 70 MS/s ADC daa shee, hp:// 30_a.pdf, 003 [] Analog Devices, AD945 4-bi, 80 MS/s, ADC daa shee, hp:// 45_0.pdf, 00 [3] Analog Devices, AD bi, 800 ks/ssar ADC, daa shee, hp:// 74_prc.pdf, 00 [4] Analog Devices, AD khz, daa shee, hp:// 836_prc.pdf, 00

33 3 ADC Characerizaion 3. Inroducion There are many parameers for ADC characerizaion, describing differen aspecs of he conversion. They are all imporan for differen reasons. In he following secions, he mos commonly used specificaions are defined. More informaion can be found in [] and []. 3. DC Specificaions When performing an A/D conversion, here are several mechanisms ha limi how accuraely he signal is represened. When convering an analog signal o a digial, here is a round-off error. This quanizaion error exiss even in ideal ADCs and ses a heoreical upper limi on achievable resoluion. I is a deerminisic error, bu since he inpu o an ADC ypically is complicaed signals and noise, i is randomized. For his reason, quanizaion error is normally reaed as whie noise. Besides he quanizaion noise, hermal noise will reduce he resoluion. I is a fundamenal random noise ha is presen in all sysems. Anoher facor ha affecs he oupu code is mismach from chip manufacuring. The maching can be improved wih special design mehods or by moving o a process wih smaller feaure size. 9

34 0 ADC Characerizaion Ideal ransfer curve. Acual ransfer curve Ideal ransfer curve. Acual ransfer curve. 4 4 Digial Oupu INL 0 INL 0.5 LSB Digial Oupu DNL 0.5 LSB DNL 0.3 LSB Analog Inpu Figure 3.. INL Analog Inpu Figure 3.. DNL. 3.. INL Inegral nonlineariy (INL) is a measure of how far from he ideal ransfer curve a measured converer resul is, see figure DNL The differenial nonlineariy (DNL) is a measure of how far a code is from a neighboring code. The disance is measured as a change in inpu volage ampliude and hen convered o LSBs. This is illusraed in figure 3.. A DNL of </- LSB ensures ha here are no missing codes. INL is he inegral of DNL, so a good INL guaranees a good DNL. 3.3 Dynamic Specificaions Having good values on INL and DNL does no necessarily mean ha a converer will perform well. Those measures are only valid a or near DC. As he frequencies increase, he ADC performance will decrease due o various dynamic effecs. Jier, uncerainy in sampling insan due o ADC or sampling clock imperfecions, will limi he performance for high inpu frequencies. Deails on he effec of jier for high inpu frequencies can be found in appendix A.. There will also be dynamic effecs due o ime consans in T/H, DAC, and comparaor. The RC seling of hese componens ses a limi for maximum clock frequency. There will be a performance decrease when he ADC is run oo fas for he sampling capaciors o charge correcly or oo fas for he comparaor o make a correc decision.

35 3.3 Dynamic Specificaions 3.3. SNR The signal-o-noise-raio describes where he noise floor is by relaing he signal power o he noise power. SNR P s 0 log [db], Pn where P s is he signal power and P n he oal noise power. In an ideal converer, he only noise is he quanizaion noise and, if he inpu is a full-scale signal, he SNR can be calculaed as SNR 6.0n.76 [db], where n is he number of bis. See figure 3.3 for an illusraion and appendix A. for deails. In real applicaions, here are of course more noise conribuions and he SNR is lower, bu his ses he heoreical maximum SNR SNDR I is no only noise ha degrades he performance of ADCs. There is also disorion. The signal-o-noise-and-disorion-raio (SNDR) is defined as SNDR P s 0 log [db], Pnd where P s is he signal power and P nd is he oal power of noise and disorion ENOB An ADC is designed o have a cerain nominal number of bis, a resoluion direcly relaed o he number of quanizaion levels available. In a real ADC his resoluion is never achieved since here are always more noise sources han jus he quanizaion noise. As shown in secion 3.3., he maximum SNR can be calculaed from nominal number of bis. For a cerain SNDR an equivalen resoluion, he effecive number of bis (ENOB), for he ADC can be defined as

36 ADC Characerizaion Power [db] SNR SFDR Figure 3.3. Signal specrum Frequency [MHz] SNDR.76 ENOB [bis] SFDR The spurious-free dynamic range (SFDR) gives a measure of how well an ADC can conver weak signals. I is defined as Ps SFDR 0log [db], Pd,max where P s is he signal power and P d,max is he power of he sronges spurious peak. This is illusraed in figure THD The oal harmonic disorion is defined as THD Ps 0 log [db], Pd, harm where P s is he signal power and P d,harm is he power of all harmonic disorion.

37 3.4 References References [] R. van de Plassche, Inegraed Analog-o-Digial and Digial-o- Analog Converers, Kluwer Academic Publishers, 994 [] Maxim, The ABCs of ADCs: Undersanding How ADC Errors Affec Sysem Perfromance, hp:// May 003

38

39 4 Error Correcion 4. Error Correcion I is common ha he performance of ADCs is improved by error correcion in he digial domain. This can be done by adding correcion erms from a look-up able, see furher secion 5. This is easily done as long as good esimaes of he errors are available. The problem is o find hese good esimaes. I can be done wih calibraion using a known inpu signal bu his is ime consuming and expensive. A lo can be saved if a echnique ha does no require any knowledge of he inpu is used o calibrae he ADC a runime. Error correcion is used for single ADCs bu is even more imporan for ime-inerleaved srucures, where addiional errors are inroduced. In he nex secion, he errors ha arise in ime-inerleaved srucures are described and suggesions are made on how hey can be correced. 4. Correcion of Time-Inerleaved Srucures As discussed in secion.8, ime-inerleaving can be used o increase he sampling rae for a cerain resoluion. Inerleaving, however, inroduces errors, which mus be correced o achieve his. Due o mismach in gain, offse, and iming (phase) beween he ADCs, he signal will be disored. 5

40 6 Error Correcion Offse mismach will disor he signal every ime a sample is aken using an ADC wih differen offse han he one used o ake he previous sample. This means ha offse errors will show up in he specrum as a peak a he sample frequency for he individual ADCs, f s,i, []. For a case wih wo inerleaved ADCs, his is illusraed in figure 4.. Offse mismach can be measured by sending signals wih he same number of periods o he ADCs and hen sudy he average values. This informaion can hen be used o correc he offse errors. Gain and iming offse mismach will have he same effec on he signal. I is no possible o deermine if he signal is disored by gain or iming errors jus by observing i. One mehod o find ou is o vary he inpu frequency. Gain errors will no vary wih inpu frequency, bu iming errors will increase linearly as he sampling frequency increases. Gain and iming offse errors will affec he signal wih a frequency ha is f s,i modulaed wih he inpu frequency, f in. Afer folding, i will appear in he specrum as peaks a f s,i f in [], see figure 4. and 4.3. One mehod o find he gain mismach beween inerleaved ADCs on he same chip is o add consan volage generaors and hereby be able o sudy he gain of each ADC. This informaion can hen be used o correc gain errors. Time errors, however, are more difficul o correc. A calibraion echnique o minimize he ime errors is presened in []. Depending on he inpu frequency i improves he SFDR by 0-60 db. This echnique, however, requires a known calibraion signal. An algorihm o esimae iming offse errors wihou any knowledge of he inpu signal is presened in [3], [4]. I is based on he basic idea is ha signals change more in average if he sampling insan is delayed and less if i comes oo early. This improvemen wih his echnique is good for low frequencies and ends o zero near he Nyquis frequency. 4.3 References [] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, Explici Analysis of Channel Mismach Effecs in Time- Inerleaved ADC Sysems, in IEEE Transacions on Circuis and Sysems : Fundamenal Theory and Applicaions, vol. 48, no. 3, pp. 6-7, Mar. 00

41 4.3 References 7 Ampliude [V] Signal Samples ADC Samples ADC Error Power [db] Time [ns] Frequency [MHz] a) b) Figure 4.. Offse error in a) ime and b) frequency domain. Ampliude [V] Signal Samples ADC Samples ADC Error Power [db] Time [ns] Frequency [MHz] a) b) Figure 4.. Gain error in a) ime and b) frequency domain. Ampliude [V] Signal Samples ADC Samples ADC Error Power [db] Time [ns] Frequency [MHz] a) b) Figure 4.3. Timing error in a) ime and b) frequency domain.

42 8 Error Correcion [] H. Jin, A Digial-Background Calibraion Technique for Minimizing Timing-Error Effecs in Time-Inerleaved ADC s, in IEEE Transacions on Circuis and Sysems : Analog and Digial Signal Processing, vol. 47, no. 7, pp , Jul. 000 [3] J. Elbornsson and J.-E. Eklund, Blind Error Esimaion of Timing Errors in Inerleaved A/D Converers, in Proceedings of ICASSP 00. IEE, 00, vol.6, pp [4] J. Elbornsson, Equalizaion of Disorion in A/D Converers, Lic. Thesis 883, Deparmen of Elecrical Engineering, Linköping Universiy, April 00.

43 Par II ADC Modeling 9

44

45 5 ADC Modeling Survey 5. ADC Modeling ADC models are used in many applicaion fields and for many differen reasons. Therefore, he differen users are ineresed in differen modeling deails []. The end user of an ADC is no ineresed in he conversion process or he error sources. The ineresing hing is ha he ADC performs as well as possible. Here, ADC models are used for calibraion, i.e. increasing he accuracy of he digial represenaion of he analog inpu signal. This is done by using a model ogeher wih an error correcion echnique. Since he srucure of he ADC is no of ineres, a black-box model can be used. The ADC eser is ineresed in reducing he esing ime. To do his, he ADC is modeled wih as small a se of parameers as possible. Then only one es poin per parameer is needed o fully characerize he ADC []. The ADC designer uses models for diagnosis, i.e. geing an undersanding of error sources and why he conversion does no work as expeced. This informaion is hen used o correc design flaws. He also uses he forecasing capabiliies of he model o compare he consequences of differen design choices. This requires much more deailed models han for calibraion or es ime reducion. The sysem designer has needs similar o he ADC designer. However, since he is simulaing an enire sysem, he simulaion ime is more criical. Therefore he does no wan any unnecessary deails. The imporan hing is ha he facors ha are performance limiing in he 3

46 3 ADC Modeling Survey applicaion he is simulaing are included. Also, he ADC model mus be compaible wih his sysem simulaion sofware. Because of he many differen uses of ADC models and he fac ha ADC errors are very archiecure dependen [3], here is a huge amoun of models presened in he lieraure. The majoriy of hem only model a specific ADC archiecure, bu here are also many papers wih general suggesions [], [4], [5]. There is always a rade-off beween good accuracy and shor simulaion ime. Circui-level models, such as SPICE models, may be useful o simulae small pars or, in some cases, even complee ADCs, bu for sysems he simulaion ime becomes much oo large. The complexiy of he sysems can only be handled by using advanced CAD ools and by shifing o a higher absracion level [6]. Behavioral modeling is necessary. 5. ADC Behavioral Modeling A generalized model srucure is suggesed in [4]. I is based on he division of he converer ino wo main blocks: one analog and one discree-sae. There are also wo blocks, AD and DA, which handle he conversion beween analog signals and discree saes. Using his srucure, various ADCs wih differen block diagrams can be included and hus i is possible o use he same emplae for differen ADC archiecures. Of course, o ake archiecure specific errors ino accoun, models have o be developed individually for all he differen archiecures. To exrac parameers for models of individual sub circuis, circui level simulaions are normally used. A model of a SA-ADC is shown as an example, where he analog block consiss of models of he inpu amplifier and comparaors and he DA block of a model of he DAC. 5.. Saic Modeling For calibraion, a black-box model is normally used, where he ADC is modeled by is ransfer characerisic. The posiions of all ransiion levels are measured, he disances from heir nominal posiions calculaed and hen a correcion erm can be added o each oupu code by he use of a look-up able. This mehod can be used o correc errors ha exceed LSB. Since a black-box model does no conain any informaion abou he acual circuiry, i canno be used for diagnosis.

47 5. ADC Behavioral Modeling 33 In [3], a unified error model for inegraing, successive-approximaion, and flash archiecures is proposed. The effecs of he main error sources for each archiecure are analyzed in erms of INL and DNL. Such a model can be used for calibraion as well as diagnosis. A general approach of modeling for diagnosis and calibraion is he use of error signaures []. The behavior of an ADC is usually deermined by a relaively small number of variables, such as variaions in criical resisances and capaciances. If he number of variables is x, x error signaures are used o model he ADC and he response error can be expressed as a weighed sum of hese. For a cerain ADC, i is hen enough o invesigae x es poins o solve he sysem of x equaions and hereby find he weighs. Once he weighs are known, he response error can be prediced in any es poin in which he model is valid. Deails on how o develop error signaure models can be found in [7]. If noise is included in an error signaure model, i is also possible o calculae SNDR direcly, wihou using simulaion [5]. 5.. Dynamic Modeling For low frequencies, saic ADC models may be effecive bu as he frequencies increase ADCs show many dynamic effecs ha also have o be modeled. For calibraion his means ha muli-dimensional correcion ables have o be used. The wo mos common wo-dimensional approaches are phase-plane compensaion, where he error is modeled as a funcion of ampliude and slope of he inpu, and sae-space compensaion, where he error is modeled as a funcion of presen sample ampliude and previous sample ampliude [8] [9] [0]. There are several mehods o generae he error able used for correcion. In [], sine wave hisograms are used o generae he error able for a model ha describes he error as a funcion of ADC sae and inpu slope. In [], a dual-one inpu and a bidimensional hisogram is used o achieve a beer errorable coverage and improved compensaion. The same is accomplished in [3] wih he use of pseudorandom calibraion signals. A comparison is also made wih an alernaive compensaion echnique based on Volerra series. Volerra series is a mahemaical approach o describe a sysem where nonlinear phenomena and memory effecs are simulaneously presen. For a given example, i is shown ha he error-able approach gives beer compensaion and has less compuaional complexiy. However, i is also saed ha for a sysem wih longer memory, he

48 34 ADC Modeling Survey Volerra approach may perform beer. An advanage wih he Volerra approach is ha i can give some insigh ino sysem properies such as significance of various nonlineariy orders, somehing ha is no possible wih he error-able approach. Anoher example of a Volerra-based model can be found in [4]. For diagnosis, again, informaion abou he individual blocks is necessary. To be useful in sysem design, a model also has o include he saisical properies, caused by process variaion [5], ha affec boh saic and dynamic behavior [6]. This requires advanced mahemaical mehods and is closely relaed o he ADC archiecure. Some recenly published models are e.g. a flash archiecure in [7], a pipelined in [8], and a coninuous-ime sigma-dela in [9]. The models are implemened in differen high-level languages, such as SIMULINK [8] and C [7]. A VHDL implemenaion of a sigma-dela model is presened in [0]. The complexiy of sae-of-he-ar ADCs makes i difficul o develop effecive dynamic models. Therefore mos dynamic specificaions, e.g. ENOB, do no refer o a commonly acknowledged dynamic model wih which he signal response can be prediced. They serve as a descripion of signal degradaion raher han ADC behavior and, since hey are relaed o a specific es signal, hey canno be rused o be he wors case for an arbirary applicaion []. They can be used o compare he performance of similar devices in similar condiions, bu are of limied use for sysem designers who wan o predic sysem performance []. 5.3 References [] A. Baccigalupi and M. D apuzzo, Analog-o-Digial Converer Modeling: a Survey, in Measuremen, vol. 9, no. 3-4, pp , Nov.-Dec. 996 [] T. M. Souders and G. N. Senbakken, A Comprehensive Approach for Modeling and Tesing Analog and Mixed-Signal Devices, in Proceedings of he Inernaional Tes Conference, pp , Sep. 990 [3] P. Arpaia and P. Dapone, Influence of he Archiecure on ADC Error Modeling, IEEE Transacions on Insrumenaion and Measuremen, vol. 48, pp , Oc. 999 [4] G. Ruan, A Behavioral Model of A/D Converers Using a Mixed- Mode Simulaor, in IEEE Journal of Solid-Sae Circuis, Vol. 6, Mar. 99

49 5.3 References 35 [5] E. Liu, G. Gielen, H. Chang, A. L. Sangiovanni-Vincenelli, and P. Gray, Behavioral Modeling and Simulaion of Daa Converers, in Proceedings of he IEEE Inernaional Symposium on Circuis and Sysems, Vol. 5, pp , May 99 [6] G. G. E. Gielen, Modeling and Analysis Techniques for Sysem- Level Archiecural Design of Telecom Fron-Ends, in IEEE Transacions on Microwave Theory and Techniques, vol. 50, no., Jan 00 [7] G. N. Senbakken and T. M. Souders, Linear Error Modeling of Analog and Mixed-Signal Devices, in Proceedings of he Inernaional Tes Conference, pp , Oc. 99 [8] T. A. Rebold and F. H. Irons, A Phase Plane Approach o he Compensaion for Analog-o-Digial Converers, in Proceedings of he Inernaional Symposium Circuis and Sysems, pp , May 987 [9] D. Asa and F. H. Irons, Dynamic Error Compensaion of Analogo-Digial Converers, in Lincoln Laboraory Journal, vol., no., pp. 6-8, 989 [0] F. H. Irons, D. M. Hummels, and S. P. Kennedy, Improved Compensaion for Analog-o-digial Converers, in IEEE Transacions on Circuis and Sysems, vol. 38, no. 8, pp , Aug. 99 [] J. Larrabee, F. H. Irons, and D. M. Hummels, Using Sine Wave Hisograms o Esimae Analog-o-Digial Converer Dynamic Error Funcions, in IEEE Transacions on Insrumenaion and Measuremen, vol. 47, no. 6, pp , Dec. 998 [] S. Acuno, P. Arpaia, D. M. Hummels, and F. H. Irons, A New Bidimensional Hisogram for he Dynamic Characerizaion of ADCs, in IEEE Transacions on Insrumenaion and Measuremen, vol. 5, no., pp , Feb. 003 [3] J. Tsimbinos and K. V. Lever, Improved Error-Table Compensaion of A/D Converers, in IEE Proceedings Circuis, Devices, and Sysems, vol. 44, no. 6, pp , Dec 997 [4] P. Mikulik and J. Saliga, Volerra Filering for Inegraing ADC Error Correcion, Based on an A Priori Error Model, in IEEE Transacions on Insrumenaion and Measuremen, vol. 5, no. 4, pp , Aug. 00

50 36 ADC Modeling Survey [5] M. J. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbres, Maching Properies of MOS Transisors, in IEEE Journal of Solid-Sae Circuis, vol. 4, no. 5, pp , Oc 989 [6] G. Van der Plas, J. Vandenbussche, W. Verhaegen, G. Gielen, and W. Sansen, Saisical Behavioral Modeling for A/D-Converers, in Proceedings of he IEEE Inernaional Conference on Elecronics, Circuis and Sysems, vol. 3, pp , 999 [7] J. Compie, P. de Jong, P. Wambacq, G. Vanderseen, S. Donnay, M. Engels, and I. Bolsens, High-Level Modeling of a High-Speed Flash A/D Converer for Mixed-Signal Simulaions of Digial Telecommunicaion Fron-Ends, in Souhwes Symposium on Mixed- Signal Design, pp , 000 [8] D. Dalle, Modelling and Characerizaion of Pipelined ADCs, in Proceedings of he IEEE Insrumenaion and Measuremen Technology Conference, vol., pp. 07-, May 00 [9] K. Francken, M. Vogels, E. Marens, and G. Gielen, A Behavioral Simulaion Tool for Coninuous-Time Σ Modulaors, in Proceedings of he IEEE/ACM Inernaional Conference on Compuer Aided Design, pp , 00 [0] M. Schuber, VHDL Based Simulaion of a Sigma-Dela Converer, in Proceedings of he IEEE/ACM Inernaional Workshop on Behavioral Modeling and Simulaion, pp. 7-76, 000 [] T. E. Linnenbrink, Effecive Bis: Is Tha All There Is?, in IEEE Transacions on Insrumenaion and Measuremen, vol. IM-33, no. 3, Sep 984 [] G. Chiorboli and C. Morandi, ADC Modeling and Tesing, in Proceedings of he IEEE Insrumenaion and Measuremen Technology Conference, vol. 3, pp , May 00

51 6 An ADC Model for Sysem Simulaion 6. Inroducion As discussed in secion., here is a grea need for accurae sysem simulaion o find reasonable ADC requiremens for a cerain applicaion and as shown in secion 5, here are a huge number of differen ADC models. There is, however, a lack of invesigaions on requiremens for ADC models for sysem simulaion and heir effecs on sysem performance accuracy presened in open lieraure. A complex ADC model is of no use if he same informaion can be obained wih a simple one. An example of ADC modeling for sysem simulaion can be found in [], where he effec of sigma-dela converers in orhogonal frequency division muliplex (OFDM) sysems is invesigaed. This work has wo main pars. The firs is o develop a deailed ADC model ha includes dynamic behavior and all performance limiing errors for a cerain archiecure. The model should also be validaed by comparing simulaed daa wih measuremens. The second is o invesigae if his accurae model is needed, if i gives any more informaion han simple models in sysem simulaion. This is done by performing sysem simulaions on realisic applicaions and sudying how differen model parameers affec sysem performance in comparison o simulaions wih a simple model. 37

52 38 An ADC Model for Sysem Simulaion The chosen archiecure is successive-approximaion. I is one of he mos popular archiecures and, as described in secion.4, i has several advanages such as suiabiliy o conver muliple signals per ADC and non-periodic muliplexed signals. The major drawback of he successiveapproximaion archiecure is he low hroughpu. To obain high sample raes, inerleaving has o be used. An imporan advanage wih choosing he successive-approximaion archiecure was also ha here was previous experience in he research group and an ADC was available for measuremens [], [3]. The currenly dominaing archiecure for high-speed applicaions is he pipelined due o is high hroughpu and high possible resoluion. The pipelined archiecure has some similariies wih he SA-ADC. I also performs successive approximaions only in his case he binary search is implemened in a pipeline where each sage gives a closer approximaion of he inpu. Hence, an inerleaved SA-ADC srucure can be an alernaive o a pipelined. Assuming ha he errors inroduced by inerleaving can be sufficienly correced, i should have performance comparable o a pipelined. Since i is o be used in sysem simulaion, he model canno be oo deailed or he simulaion ime will be oo long. This is especially rue since design normally involves he sweeping of parameers o find an opimum and hus many simulaions have o be performed. As discussed in secion.4, i is well known ha he SA-ADC resoluion is limied by componen maching. The componens ha require good maching are he reference volage generaor and he comparaor. Hence, i is naural o focus on finding accurae models for hose. Oher pars, such as he oupu regiser and he conrol logic for he binary search, can be assumed ideal. One approach o increase he chance ha all performance-limiing effecs will be included is o keep he models as physically correc as possible. Then he model correcly mimics he behavior of he acual circui and here is less risk ha effecs ge los in mahemaics. A mahemaical behavioral model based on explici equaions ha describes he physical behavior of a circui will be boh accurae and fas. The drawback is ha i will no be generally applicable.

53 6. Model Descripion Model Descripion A model of a subranging SA-ADC has been implemened in MATLAB. As would a real ADC, i akes a ime-domain analog inpu signal and gives a ime-domain digial oupu signal. This makes is easy o inegrae in any sysem simulaor where embedded MATLAB code can be used. The main objecive was o model all performance limiing dynamic errors as realisically as possible while keeping he model simple enough o give reasonable simulaion imes. This was done by using an approach wih mahemaical behavioral modeling as discussed in he previous secion. The model equaions were obained by analyically solving he equaions of an equivalen circui found by idenifying he main resisances and capaciances in he sampling fronend of a real ADC [3]. The deails on his can be found in appendix B. A block diagram of he model is shown in figure 6.. Three subranges are used: C (Coarse), M (Middle), and F (Fine). Firs he inpu is applied o ge a sampled volage V S. Then, for each ieraion in he binary search, a reference volage, V R, o compare o he sampled volage is calculaed by superposiion of he conribuions from he differen subranges. Figure 6. shows he equivalen circui for he conribuion from he coarse subrange, V R,C. The resisances come from he on-resisances of he NMOS swiches, which are calculaed as r S µ C n ox W L ( V V ) GS, where µ n and C ox are process parameers, W and L widh and lengh respecively of he ransisor, V GS is he gae-source volage, and V is he hreshold volage. The capaciances are he sampling capaciors. This gives a model for he seling behavior of he ADC. Errors included in he model are: Quanizaion error and clipping, modeled by a binary search among defined volage reference levels. Thermal noise, modeled by random addiion o he inpu signal.

54 40 An ADC Model for Sysem Simulaion S F C F binary search conrol logic V RF S M V RM S M C M V S -V R S S V ou S C C C V RC V in Figure 6.. ADC model block diagram. V RC r SC C C V R,C C M C F C P r SM r SF Figure 6.. ADC model equivalen circui. Resisor ladder mismach. This is modeled by a random Gaussian addiion o reference volages. Nonlinear behavior of sampling swiches. The resisance values depend on he reference values currenly used. RC seling o comparaor inpu, modeled by analyical soluion o differenial equaions. Comparaor recover ime. Due o ime consans in he comparaor, some ime is needed o recover from an iniially wrong decision. This reduces he comparaor decision ime. I is modeled as a consan reducion of he available ime o sele.

55 6.3 Fuure Work 4 Jier. This is modeled by a random Gaussian addiion o he inpu signal phase. Necessary model parameers are: Technology parameers µ n (NMOS mobiliy) and C ox (gae oxide capaciance) o be able o calculae NMOS ransisor onresisances. Comparaor ransisor sizes o calculae g m and he parasiic capaciance of he comparaor inpu, C p and o esimae he comparaor load capaciance, C L. Number of subranges and values of he reference generaor resisors and sampling capaciors. Since he swich on-resisances vary, he equaion sysem has o be solved for each possible reference value, n soluions for an n-bi converer. To save ime a runime, all possible roos are calculaed beforehand and saved in a marix. The calculaion imes for differen number of bis simulaed on a GHz Penium III wih 5 MB RAM is shown in figure 6.3. The ime increases exponenially, bu his calculaion has o be done only once for a model wih given parameers. Calculaing roos for a -bi ADC akes abou 3 min. The simulaion ime vs. number of bis for a vecor lengh of 6384 is shown in figure 6.4. The model core is very simple. I is jus a binary search loop where all volages are calculaed wih explici equaions. This can be implemened on a few lines of MATLAB code. The coefficiens, however, are quie complex, which increases code complexiy and simulaion ime. 6.3 Fuure Work To srenghen his work, modeling of oher archiecures is necessary. I should be done using he same sraegy of finding explici mahemaical equaions based on a few physical properies of he sub blocks. Since he same blocks, T/H, reference generaor (DAC), and comparaor, are used

56 4 An ADC Model for Sysem Simulaion Calculaion Time [s] Simulaion Time [s] ADC Bis ADC Bis Figure 6.3. Roo calculaion ime. Figure 6.4. Simulaion ime. in mos ADC archiecures, a similar approach should be possible for oher archiecures as well. I remains o be seen, however, which properies of he sub blocks will be performance limiing. To model a pipelined converer would be a suiable choice since i is he dominaing archiecure for high-frequency applicaions where he dynamic effecs become an issue. Anoher coninuaion would be o use he converer model in oher common applicaions wih ough requiremens on he ADC, e.g. radio receivers. 6.4 References [] A. Moschia and D. Peri, Wideband Communicaion Sysem Sensiiviy o Quanizaion Noise, in Proceedings of he IEEE Insrumenaion and Measuremen Technology Conference, vol., pp , 00 [] J. Yuan and C. Svensson, A 0-bi 5 MS/s Successive Approximaion ADC Cell Used in a 70 MS/s ADC Array in. µm CMOS, in IEEE Journal of Solid-Sae Circuis, vol. 9, no. 8, pp , Aug. 994 [3] J.-E. Eklund, A 00 MHz Cell for a Parallel-Successive- Approximaion ADC in 0.8 µm CMOS, Using a Reference Pre-Selec Scheme, in Proceedings of he European Solid-Sae Circuis Conference, pp , Sep. 997

57 Par III Papers 43

58

59 7 Paper A MATLAB-Based ADC Model for RF Sysem Simulaions Kalle Folkesson ), Jan-Erik Eklund ), Chriser Svensson 3), and Andreas Gusafsson 4),3) Elecronic Devices, Deparmen of Physics Linköping Universiy, SE Linköping, Sweden ) Microelecronic Research Cener, Ericsson Componens AB Isafjordsgaan 6, SE-64 8 Kisa, Sweden 4) Defence Research Esablishmen (FOA), Deparmen of Microwave Technology SE-58, Linköping, Sweden in Proceedings of he Swedish Naional Symposium on GigaHerz Elecronics, pp , Mar

60 46 Paper A MATLAB-Based ADC Model for RF Sysem Simulaions Kalle Folkesson ), Jan-Erik Eklund ), Chriser Svensson 3), and Andreas Gusafsson 4),3) Elecronic Devices, Deparmen of Physics Linköping Universiy, SE Linköping, Sweden ) Microelecronic Research Cener, Ericsson Componens AB Isafjordsgaan 6, SE-64 8 Kisa, Sweden 4) Defense Research Esablishmen (FOA), Deparmen of Microwave Technology SE-58, Linköping, Sweden Absrac Analog-o-digial converers (ADCs) are ofen he limiing componens in signal processing sysems. When a sysem is designed, he demands on he ADC are ofen se unnecessary high o ensure ha he sysem will work. To find reasonable demands on he ADC, an accurae model for sysem simulaions would be useful. Such a model would also make i possible o find ou which ADC errors limi he performance in a cerain applicaion and o do design rade-offs for various sysems. A MATLABbased ime-domain ADC model aimed o work ogeher wih frequency domain RF simulaors is presened. 7. Inroducion ADCs are essenial pars in signal processing sysems such as wireless communicaion and radar. Since hese areas are developing rapidly, here is a need for high-performance ADCs. When a sysem is designed, one very imporan ask is o choose he ADC, which ofen has a significan impac on he sysem performance. I is, however, raher difficul since here is no so much knowledge of wha he requiremens on he ADC

61 7. Errors in ADCs 47 should be. This leads o ADCs wih unnecessarily high performance being used, and his makes he sysem unnecessarily complex and expensive. One way o find suiable requiremens would be o make sysem simulaions using an accurae ADC model which includes all he performance limiing errors. Tha would give good knowledge abou he limis in accuracy, sampling rae, and bandwidh. Such a model would also be a good ool o es error hypoheses. This paper will focus on some of he errors ha occur in ADCs and a MATLAB-based model which akes hese ino accoun will be presened. 7. Errors in ADCs Quanizaion errors occur in all ADCs, even ideal ones. I arises because he analog inpu signal, which can ake any value, is rounded o a finie number of oupu levels. The only way o decrease he quanizaion error is o increase he resoluion. Quanizaion is deerminisic, bu since he inpu normally consiss of complicaed signals and noise, he error is approximaely random and has a noise-like behavior. The maximum SNR due o limiaion by quanizaion noise for an N bi ADC can for a sine wave inpu be calculaed as: SNR Q,max VS, 0log V rms Q, rms 6.0N.76 max Vref 0log V LSB 0log 8 N Anoher imporan error is jier, i.e. uncerainy in sample ime. This can be considered a random error and consequenly i will lead o an increase in noise level. The error ampliude A V S S When he inpu signal is a sine wave A Aω cos ω Aω

62 48 Paper Frequency Hz Frequency Hz Figure 7.. Hence, if he inpu frequency is doubled, A is doubled. Tha is equivalen o a 6 db decrease in SNR. This is illusraed in figure. 7.. The accuracy of a sysem is proporional o he maching accuracy. Mismach, i.e. gradiens on a chip, will of course decrease performance. Accuracy is improved wih deeper submicron echnologies and i is also possible o reduce mismach o a cerain degree by using design mehods ha spli up devices and place he pars in such a way ha i minimizes he effec of gradiens. Depending on he applicaion, mismach can cause eiher noise or disorion. Therefore i is ineresing o simulae for a cerain applicaion and see which effec i has in ha paricular case. 7.3 ADC Model A MATLAB-based ADC model has been developed. To make i easy o use, i akes an analog inpu signal and yields a digial oupu. This, in addiion o he fac ha i is wrien in MATLAB, makes i compaible wih evaluaion sofware normally used o es ADCs. ADC errors are very archiecure dependen. The model simulaes one of he mos widespread archiecures, he successive approximaion ADC (SA-ADC), bu i is easy o inegrae models of oher archiecures. The model solves he differenial equaion ha arises when he SA-ADC is modeled by an RC nework. The RC ime consans make i possible o model he performance decrease when he ADC runs oo fas for he sampling capaciors o charge correcly. Besides he quanizaion error and he RC ime consans, he model also akes jier and mismach ino accoun.

63 7.3 ADC Model Fs 3.5 MHz, 7 ps jier 6 Fs 3.5 MHz, Fin.3 MHz, 7 ps jier SNR [db] 50 SNR [db] Fin [MHz] Mismach [%] Figure 7.. Figure 7.3. Jier is modeled as a normally disribued random number, which modifies he values of he sampled inpu signal. Since he signal is ime discree afer sampling, he inpu frequency should no affec he SNR in he res of he sysem. I is, however, clear from figure ha he SNR decreases significanly when he inpu frequency increases. This means ha i is he sampling ha limis he bandwidh for a cerain SNR. The sraigh lines have a slope of -6 db for every doubling of he inpu frequency. As explained in he previous secion, his is he heoreical slope for a curve when jier is he limiing facor. The simulaion follows i closely for high frequencies. This means ha he performance in sysems wih high frequency inpu signals will be limied by jier. For lower frequency sysems, oher facors such as mismach and hermal noise will be limiing. Simulaions like he one in figure 7. are useful o find ou wheher he performance would increase if more bis were used or if he jier would limi i anyway. Like jier, saic mismach in he resisors is modeled as a normally disribued random number. Simulaion resuls are shown in figure 7.3. As expeced, SNR decreases when he mismach increases. The model was run ogeher wih ADS (Advanced Design Sysem), an RF simulaor from HP. A very simple es case, shown in figure 7.4, was simulaed. A sine wave inpu signal was run wihou any oher componens, wih a quanizaion block included in ADS, and wih he model. A sample frequency of 50 MHz was used o sample a 0 MHz signal. For visibiliy, a 36 ps jier was used wih he ADC model. To

64 50 Paper Sin Quanizaion ADC model Figure 7.4. Sine wave Quanizaion ADC model Figure 7.5. compare he oupus, he specra was sudied. In figure 7.5, i shows ha he ADC model resuled in a higher noise level and harmonics. 7.4 Measuremens To verify he accuracy of he model, simulaions were compared wih measured daa. This is shown in figure 7.6. The dos are measured daa and he curve is simulaed. The ADC was characerized by uning he ADC parameers unil he curve mached he measured daa. The SNR measured before jier becomes he limiing facor is unfairly low due o harmonics from he signal generaor. When measuremens were made using a low pass filer, he SNR for low frequencies were abou 58.5 db. Therefore he model was uned o mach ha insead. The resul was an ADC wih 0.5% mismach and 7 ps jier. An ineresing phenomenon is ha he jier is higher for low frequencies. This may be because he sine wave clock does no produce very good edges hen.

65 7.5 Conclusions 5 60 Fs 3.5 MHz, 0.5% mismach, 7 ps jier ADC limied Source limied SNR [db] Fs 5 MHz Jier limied Fs 3.5 MHz 4 Fs.5 MHz Fin [MHz] Figure Conclusions A MATLAB-based model o describe some of he mos imporan errors ha occur in ADCs was presened in his paper. I can easily run ogeher wih exising RF simulaion ools o perform accurae sysem simulaions.

66

67 8 Paper Modeling of Dynamic Errors in Algorihmic A/D Converers Kalle Folkesson ), Jan-Erik Eklund ), Chriser Svensson 3),3) Elecronic Devices, Deparmen of Physics Linköping Universiy, SE Linköping, Sweden ) Microelecronic Research Cener, Ericsson Microelecronics AB Teknikringen 8, SE Linköping, Sweden in Proceedings of he IEEE Inernaional Symposium on Circuis and Sysems, pp , May 00 53

68 54 Paper Modeling of Dynamic Errors in Algorihmic A/D Converers Kalle Folkesson ), Jan-Erik Eklund ), Chriser Svensson 3),3) Elecronic Devices, Deparmen of Physics Linköping Universiy, SE Linköping, Sweden ) Microelecronic Research Cener, Ericsson Microelecronics AB Teknikringen 8, SE Linköping, Sweden Absrac In communicaion applicaions, he requiremens on A/D converers are high and increasing. To be able o design high- performance converers, i is imporan o undersand he speed limiaions. In his work, performance decrease caused by dynamic errors relaed o seling ime of he swiched circuis a high sampling frequencies is invesigaed. 8. Inroducion The performance requiremens on analog-o-digial converers (ADCs) are coninuously increased. For applicaions in communicaion, high resoluion a high sampling frequencies is needed []. I is he aim of his work o improve he undersanding of he speed limiaions of algorihmic ADCs. A high frequencies, he effecive resoluion ends o reduce in erms of effecive number of bis or signal-o-noise raio []. This has wo main reasons: he effec of sampling jier and he effec of dynamic errors in he sampling and conversion processes. Such dynamic errors are for example decision ime and hyseresis effecs in comparaors and also seling ime of swiched circuis. The effec of a oo long comparaor decision ime is measabiliy errors, which cause spikes in he ime domain [3]. In his work, dynamic effecs relaed o seling ime of he swiched circuis are invesigaed by using a model of he successive-approximaion archiecure as an example. The findings are compared o measuremens on an experimenal ADC. The ADC is

69 8. The ADC 55 Binary Search Conrol Logic S RF C F V RF S RM C M V RM V RC S RC C C Comparaor V D S A S S V A Figure 8.. Principle of he ADC. described in secion 8. followed by some words on dynamic errors in secion 8.3. Secion 8.4 describes he model and in secion 8.5 he measuremens and simulaions are presened. Finally, some conclusions are drawn in secion The ADC For he measuremens, a 0-bi subranging successive-approximaion ADC ha uses binary search [4] was used. The principle is shown in figure 8.. I has 3 reference volage ranges: C (coarse), M (middle), and F (fine). The supply volage is 5 V and he signal range is 0- V cenered on V. The reference volages V RC, V RM, and V RF are generaed wih resisor ladders ha have a resisance of less han 30 Ω in series wih he sampling capaciors. The sampling capaciors, C C, C M, and C F are 8,, and imes of a ff uni capacior respecively. The comparaor consiss of several sages of differenial amplifiers, clocked regeneraive comparaors, and laches. A simplified block diagram is shown in figure 8.. In principle, i has wo phases: Compare and Lach. The iming of hese is shown in figure 8.3. When clock goes low, he rese swich opens and he evaluaion cycle sars afer r ( r 0.5 ns), he delay in he rese swich. Figure 8.4 shows SPICE simulaions of he amplifier chain for a few inpu signals. To illusrae he dynamic effecs, ramping inpu signals ha

70 56 Paper S R C Diff. Amp. Comparaor Lach ou Rese Figure 8.. Comparaor block diagram. Clock Lach Compare Lach Compare Comparaor Evaluae Rese Lach Rese Evaluae Figure 8.3. Comparaor iming diagram. Volage [V] rese ramp inpus oupu signals Time [ns] Figure 8.4. SPICE simulaions of amplifier chain.

71 8.3 Dynamic Errors 57 crosses he 0-level were chosen. The lach insan is when he rese signal goes high. When he inpu signal ramp crosses he 0-level a.5 V during he evaluaion cycle, i akes some ime for he amplifiers o recover from he wrong iniial value, i.e. for he oupu signals o change from posiive o negaive. I shows ha his recover ime depends weakly on he inpu signal, bu as a firs approximaion i can be considered consan. 8.3 Dynamic Errors In his work, dynamic errors in ADCs are invesigaed. Primarily, an aemp is made o realisically model conversion errors due o RC ime consans from resisances in reference swiches and ladders ogeher wih sampling capaciors. However, anoher ype of error is also considered; a consan ime by which he comparaor decision ime is decreased. This will be moivaed in secion 8.4. These errors limi he clock frequency a which he ADC can run. The ime consans reduce he ime available for nodes o sele o correc values and he consan ime error reduces he comparaor decision ime. In boh cases, a oo large error leads o a wrong decision in he comparaor. 8.4 The Model A MATLAB-based model of a successive-approximaion ADC has been developed [5]. The main objecive was o model all limiing errors as realisically as possible. This was done by idenifying he main resisances and capaciances in he real ADC and considering hese an RC nework o which he signals were applied. A block diagram of he model is shown in figure 8.5. When he inpu signal has been applied o he RC nework o ge a sampled volage, V S, superposiion is used o find he oal conribuion from he reference volages. Figure 8.6 shows an equivalen circui when he conribuion of he coarse reference secion, V R,C, is calculaed. The swiches are NMOS ransisors and heir resisances, r i, are modeled as r i L W S S µ C n ox ( V GS L V ) W S S µ C n ox (5 V R, i,.)

72 58 Paper V in V RC S S r SRC C C... S RC C C C M r SRM V R,C C F r SRF C P... S RM C M V S, V R C P V ou C L Figure 8.6. Equivalen RC nework.... S RF C F Figure 8.5. Model block diagram. where 5 is a full-scale conrol signal on he gae, V R,i is he reference volage, and. is an approximaion of V when he body effec is considered. This gives resisances larger han 00 Ω. The reference ladder resisances are negligible and herefore lef ou of he model. The parasiic capaciance C P and load capaciance C L are modeled as 0.65 pf. Figure 8.7 shows block diagrams of wo differen models of he differenial amplifiers and he comparaor. For model a, he digial oupu is simply one or zero depending on if V ou is posiive or negaive. V ou is calculaed as V ou g C m L s k 0 ( V V )d, S R where V S is he sampled inpu signal, V R he sum of all reference volage conribuions, V R,i, s is half a sampling period, and k is a consan ime o model he recover ime described in secion 8.. This reduces he ime he comparaor has o change an iniially wrong decision. As he clock frequency, f c, increases, k will become a subsanial par of he available decision ime, k - s, and performance will decrease very quickly.

73 8.5 Measuremens and Simulaions 59 V S -V R g m V ou C L V S -V R V ou a) b) Figure 8.7. Amplifier model block diagrams. Model b in figure 8.7 is an alernaive model, which uses a linear model of he differenial amplifiers insead of he consan delay, k. I includes he delay in he rese swich, r, which is se o 0.45 ns. This yields an oupu V s m ou S L g C r r ( V V ) d d Furher, a model of noise on he lach inpu can be added by leing he digial oupu be random if V ou < V n. Also, hyseresis can be modeled by leing a par of V ou remain as an iniial value when he nex bi is calculaed. V ou, ini K hvh, where K h is he hyseresis facor and V h is he previous V ou limied o [-, ] V. When sudying he effec of one of hese errors, he oher is lef ou. 8.5 Measuremens and Simulaions Simulaions and measuremens were performed wih a sine wave inpu signal wih approximaely half swing. In he measuremens, i was generaed wih a high-precision signal generaor and a low-pass filer o ge a signal wih as lile harmonic disorion as possible. The resuls are shown in figures 8.8 hrough 8.4 below. The dos are measured daa and he solid lines are simulaions. A slope of 30 db/ocave is ploed o make i easier o compare plos. To analyze oupu daa, a 4096-poin FFT is performed and based on ha he SNR is calculaed. The SNR is hen used as a performance measure in comparisons beween measuremens and simulaions. The same analysis sofware is used o evaluae boh measuremens and simulaions. R

74 60 Paper 65 f in.905 MHz SNR [db] measured daa model simulaion _ 30 db/ocave f c [MHz] 0 3 Figure 8.8. SNR vs. f c wih k 0. Figure 8.8 shows SNR as a funcion of clock frequency when model a is used wih k 0. The inpu signal frequency is.905 MHz. The performance decrease in he simulaion is no nearly as large as in he measuremen, so ime consans alone are apparenly no enough o realisically model dynamic errors. Figure 8.9 shows he same simulaion as figure 8.8 bu wih k ns. This maches he measuremens very well. To furher compare model simulaions and measuremens, he case when f c is approximaely equal o f in was sudied. This gives a good view of he ime domain daa, see figure 8.0, bu i would be much oo ime consuming o simulae i in SPICE. Uncerainy in he model due o inaccurae idenificaion of ADC componen values leads o ha he frequencies do no mach; 80 MHz was used in he measuremen and 0 MHz in he simulaions. I is, however, clear ha he general behavior is he same. In figures 8. and 8., he same simulaions are shown wih model b and s V n.5e. This models he SNR behavior very well, bu fails o produce he correc form of he ime domain daa. In figures 8.3 and 8.4, model b is used wih K h 0.4. This models he ime domain daa correcly, bu he SNR behavior is wrong.

75 8.5 Measuremens and Simulaions 6 65 f in.905 MHz SNR [db] measured daa model simulaion _ 30 db/ocave f [MHz] c Figure 8.9. SNR vs. f c wih k ns. Figure 8.0. Time domain daa. 65 f in.905 MHz SNR [db] measured daa model simulaion _ 30 db/ocave f c [MHz] Figure 8.. SNR vs. f c wih lach inpu noise. Figure 8.. Time domain daa wih lach inpu noise. 65 f in.905 MHz SNR [db] measured daa model simulaion _ 30 db/ocave f [MHz] c 0 3 Figure 8.3. SNR vs. f c wih hyseresis Figure 8.4. Time domain daa wih hyseresis.

76 6 Paper 8.6 Conclusions In his work, differen ways o model dynamic errors in ADCs have been esed and compared o measuremens. Boh SNR behavior and ime domain daa have been invesigaed. I was shown ha i is possible ha a model ha models SNR behavior correcly does no necessarily produce he correc ime domain daa and vice versa. This is an example of how a model can be used o verify error hypoheses. I has also been shown ha dynamic errors in successiveapproximaion ADCs can be modeled as a combinaion of ime consans and a consan reducion of comparaor decision ime. 8.7 References [] A. Salkinzis, H. Nie, and T. Mahiopoulos, ADC and DSP Challenges in he Developmen of Sofware Radio Base Saions, in IEEE Personal Communicaions, vol. 6, no. 4, pp , Aug 999 [] R. Walden, Analog-o-Digial Converer Survey and Analysis, in IEEE Journal on Seleced Areas in Communicaions, vol. 7, no. 4, pp , Apr. 999 [3] J.-E. Eklund and C. Svensson, "Measabiliy Deermines he Noise in Fas and Accurae A/D Converers", in Inernaional Workshop on ADC Modelling and Tesing, Proceedings of he IMEKO World Congress, Volume IVB, pp. 7-76, Jun. 997 [4] J.-E. Eklund, A 00 MHz Cell For a Parallel-Successive- Approximaion ADC in 0.8 µm CMOS, Using a Reference Pre-Selec Scheme, in Proceedings of he European Solid-Sae Circuis Conference, pp , Sep. 997 [5] K. Folkesson, J.-E. Eklund, C. Svensson, and A. Gusafsson, A MATLAB-based ADC Model for RF Sysem Simulaions, Proceedings of he Swedish Naional Symposium on GigaHerz Elecronics, pp , Mar. 000

77 9 Paper 3 Measuremen Verificaion of Esimaion Mehod for Time Errors in a Time-Inerleaved A/D Converer Sysem Jonas Elbornsson ), Kalle Folkesson ), and Jan-Erik Eklund 3) -) Deparmen of Elecrical Engineering Linköping Universiy 3) Ericsson Microelecronics AB in Proceedings of he IEEE Inernaional Symposium on Circuis and Sysems, vol. 3, pp. 9-3, May 00 63

78 64 Paper 3 Measuremen Verificaion of Esimaion Mehod for Time Errors in a Time-Inerleaved A/D Converer Sysem Jonas Elbornsson ), Kalle Folkesson ), and Jan-Erik Eklund 3) -) Deparmen of Elecrical Engineering Linköping Universiy 3) Ericsson Microelecronics AB Absrac A previously presened mehod for esimaion of ime errors in imeinerleaved A/D converer sysems is here verified on measuremens from a dual A/D converers sysem. The advanage of his esimaion mehod, compared o oher mehods, is ha i does no require any knowledge abou he inpu signal. The esimaion is mos accurae for slowly varying inpu signals bu he signal qualiy is improved even when he esimaion is done for a sinusoidal signal close o he Nyquis frequency. 9. Inroducion Many digial signal processing applicaions, such as radio base saions or VDSL modems, require ADCs wih very high sample rae and very high accuracy. To achieve high enough sample raes, an array of M ADCs, inerleaved in ime, can be used. Each ADC should work a /Mh of he desired sample rae [], [], see figure 9.. Three kinds of mismach errors are inroduced by he inerleaved srucure: Time errors Offse difference Gain difference

79 9. Theory 65 sampling clock u ADC y delay, Ts ADC ADC3 y y3 M U X y Correcion y0 ADCM ym Figure 9.. M parallel ADCs wih he same maser clock. We consider only he ime errors in his paper. The ime errors are assumed o be saic, so ha he error is he same in he same ADC from one cycle o he nex. Mehods for esimaion of iming errors have been presened in for insance [3] and [4] bu hose mehods require a known calibraion signal. Calibraion of ADCs is ime-consuming and expensive. Therefore a lo of coss can be saved if he errors in he ADC can be auomaically esimaed and compensaed for a run-ime. We will in his paper review an esimaion mehod for ime errors in inerleaved ADCs, [5], [6]. The esimaion mehod does no require any prior knowledge abou he inpu signal, excep ha i should be band limied o he Nyquis frequency. The esimaed ime errors are hen used for correcing he oupu signal. In order o show he qualiy of he esimaes, we correc he daa by inerpolaion in he frequency domain. The resuls in [5], [6] are based on simulaions. The esimaion mehod is here verified on measuremens from a dual A/D converers sysem. 9. Theory In his secion he esimaion and compensaion algorihms are briefly described. A more complee descripion of he esimaion algorihm is given in [5], [6].

80 66 Paper 3 Too early sample Too lae sample 0.8 Ideal sample Figure 9.. The basic idea for he iming error esimaion mehod. If he sample is aken oo early he average difference beween adjacen sample values is smaller, if he sample is aken oo lae he average difference beween adjacen samples is larger. 9.. Noaion The analog inpu signal is denoed u(). T s denoes he nominal sampling inerval. M is he number of ADCs. The ime error for he ih ADC is denoed i. The oupu from he ih ADC is denoed y i [k] where k is he kh sample from ha ADC. N denoes he number of samples from each ADC. y[k] denoes he non-uniformly sampled signal and ^y 0 [k] denoes he esimaed uniformly sampled signal. 9.. Time error esimaion mehod The basic idea of he esimaion mehod is ha he signal changes more on average if he sampling inerval is longer han he nominal sampling inerval and vice versa, see figure 9.. We assume, for his esimaion algorihm, ha he inpu signal is band limied Esimaion algorihm A crude esimae of he ime errors is firs calculaed as (0) i T s 0 ix vu j ^R N j;j [0] M P M i ^R N i;i [0] A () i ;:::;M

81 9. Theory 67 where ^R N [0] i;i is calculaed from measured daa as ^R N i;i [0] N NX k fy i [k] y i [k]g () The ime error esimaes can hen be improved by fixed-poin ieraion: for i ;:::;M (l) i T s a (l) M ix 0vu j M a (l ) MX i ^R N j;j [0] P M i ^R N i;i [0] ψ (l) i T s! M MX i A (l) (l) i i A T s T s (3) 9..3 Correcion Through inerpolaion When he ime errors are esimaed, we need o esimae he uniformly sampled signal from he measured non-uniformly sampled signal. The reconsrucion is done in he frequency domain [7]. Calculae he DFTs of he M subsequences y i [k]; i ;:::;M: Y i [n] DFTfy i [k]g (4) The DFT of ^y 0 can hen be calculaed from i [k] Y i [n] as ^Y 0 i [n] e j ßn i MN Yi [n]; n N;:::;N ^Y 0 [n] can hen be calculaed from hese M subsequences [8] ^Y 0 [n] MX i ß(i )n j e MN ^Y 0 n NM;:::;NM i [(n mod N) N] (5) (6)

82 68 Paper 3 80 Time disorion Harmonics from signal source SignaloTimeDisorion Raio Frequency [MHz] Figure 9.3. Definiion of he Signal-o-Time-Disorion Raio. The esimaed uniformly sampled signal is hen calculaed as ^y 0 [k] IDFTf ^Y 0 [n]g (7) 9..4 Time Error Disorion The frequency synhesizer ha is used as signal source ypically has high harmonic disorion. However, he posiion of he disorion caused by he ime error is, for a dual ADCs sysem, given by f N f in, where f N is he Nyquis frequency and f in, is he inpu signal frequency. This means ha we can sudy only he improvemen of he one caused by he ime error wihou having o boher abou he qualiy of he signal source. The disance beween he energy of he signal peak and he energy of he disorion peak caused by he ime error is measured, see figure 9.3. We will denoe his measure signal-o-ime-disorion raio (STDR). We will here calculae he signal qualiy as a funcion of he size of he ime error for a sinusoidal inpu, u() sin(!). We assume, for simpliciy in he calculaions, ha M and ha! ßa where a is an ineger. This NM means ha y[k] is formed from he wo subsequences k ßa y [k] sin NM ßa y [k] sin NM (k )

83 9.3 Measuremens 69 The DFT of y[k] is Y [n] 8 >< >: N j N j N j N j ( ej ßa N ) ( e j ßa N ) ( e j ßa N ) ( ej ßa N ) if n a if n N a if n N a if n N a 0 oherwise (8) The signal-o-ime-disorion raio is hen STDR 0 log fi fifi A Taylor expansion of (9) gives STDR ß 0 log 0 log fi e j ßa N ßa j e N fi fi fi fi ßa N (9) (0) This means ha he signal-o-ime-disorion raio is decreased approximaely 6 db per ocave, see figure Measuremens In his secion, he measuremen verificaion of he algorihm described in secion 9., is presened Measuremen seup Measuremens were done using wo AD6644 evaluaion boards from Analog Devices [9], wih a sampling frequency of 66.6 MHz each, see figure 9.4(a). A signal generaor was used as clock signal and a differenial pulse splier was used o creae wo clock signals wih opposie phase, hereby doubling he sampling frequency. A signal generaor was used as inpu signal, see figure 9.4(b).

84 70 Paper 3 a) PC Logic Analyzer Power Supply Signal Signal Generaor Clock Signal Generaor Splier Phase Shifer Synch AD6644 AD6644 b) Figure 9.4. (a) Two AD6644 evaluaion boards. (b) Measuremen seup: Clock signal and inpu signal are generaed from he wo signal generaors. Time inerleaving is achieved by invering he clock signal o one ADC. The oupu signal is colleced in he logic analyzer and he signal processing is done in MATLAB Daa acquisiion The measured daa were colleced from he logic analyzer and MATLAB was used for signal processing. To look only a ime errors, offse and