Light-Load Efficiency Optimization Method

Transcription

1 Ligh-Load Efficiency Opimizaion Mehod Yungaek Jang, Milan M. Jovanović, and avid L. illman Power Elecronics Laboraory ela Producs Corporaion P.O. Box 273, 50 avis rive Research Triangle Park, NC 279 Absrac A mehod of mainaining high power-conversion efficiency across he enire load range and is circui implemenaions are described. The proposed mehod subsanially increases he conversion efficiency a ligh loads by minimizing swiching and driving losses of semiconducor swiches, as well as core losses of magneic componens. These losses are minimized by periodically urning off and on he power converer and by conrolling he converer so ha when he converer is on i operaes a he power level ha exhibis he maximum efficiency. The performance of he proposed mehod was evaluaed on a 0-W, 400-V/2-V dc/dc converer and a - kw ac/dc boos PFC fron end. I. INTROUCTION Ever since he sar of he miniaurizaion era spurred on by he microelecronics revoluion of he lae fifies and early sixies, power conversion equipmen has been facing coninuously increasing power densiy and efficiency challenges. Unil recenly, efficiency increases of power conversion circuis were primarily driven by increased power densiy requiremens since power densiy increases are only possible if appropriae incremenal improvemens in full-load efficiency are achieved so ha he hermal performance is no adversely affeced. As a resul, maximizaion of he full-load efficiency has been a design focus all along. However, in he lae nineies, he explosive growh of consumer elecronics and daa-processing equipmen has promped he inroducion of various, mosly volunary, requiremens aimed a minimizing he idle-mode, i.e., ligh-load, power consumpion. Meeing hese increasingly-sringen requiremens, mos noably hose defined in he U.S. Energy Sar, Japan Top Runner, and ECoC (European Code of Conduc) specificaions [], sill poses a major design challenge. Today, he power supply indusry is a he beginning of anoher major focus shif ha pus efficiency improvemens across he enire load range in he forefron of cusomers performance requiremens. This focus on efficiency has been promped by economic reasons and environmenal concerns caused by he coninuous, aggressive growh of he Inerne infrasrucure and a relaively low energy efficiency of is power delivery sysem. In fac, he environmenal concerns have already promped inroducion of programs and iniiaives aimed a reducing he energy wase in power supplies for daa-processing applicaions by challenging power-supply manufacurers o improve efficiencies of heir producs. For example, he 80Plus incenive program [2] and Climae Saver Compuing Iniiaive (CSCI) [3], he wo programs ha are already in place, require ha power supplies for compuer applicaions mainain efficiency above 80% in he enire load range from full load down o 20% of full load. These efficiency arges have recenly been incorporaed ino he laes U.S. Environmenal Proecion Agency s (EPA) Energy Sar specificaions [4]. However, many of he larges compuer, elecom, and neworkequipmen manufacurers already require ligh-load efficiencies ha exceed he laes Energy Sar specificaions and also are exending hese requiremens down o 0% and, even 5% loads. Generally, he efficiency of power conversion circuis a heavy loads is deermined by he conducion losses of semiconducor and magneic componens, whereas heir ligh-load efficiency is primarily deermined by swiching losses of semiconducors, core losses of magneics, and drive losses of semiconducor swiches [5],[6]. Because swiching and drive losses of semiconducor swiches and core losses of magneic componens are almos independen of he load, a ypical efficiency curve as a funcion of he load power shows a seep fall off as he load decreases below 0-20% of he full load, as illusraed in Fig.. Furhermore, as he raed oupu power of he converer increases, larger semiconducor devices (or more devices in parallel) and larger magneic cores are needed, which leads o increased swiching and core η η MAX P LL LIGHT LOA MI-RANGE P OPT HEAVY LOA Fig.. Typical efficiency profile of power converer wih respec o delivered power. P FL P /09/$ IEEE 38

2 losses and an even seeper fall-off of efficiency a ligh loads. To make he power supply exhibi a flaer efficiency curve ha mees cusomer s expecaions, power managemen echniques such as variable swiching frequency conrol, bulk-volage reducion, phase-shedding, and burs -mode operaion have been inroduced [7]-[0]. Alhough he described echniques have been shown o improve he parialload efficiency, hey suffer from some major drawbacks ha limi heir area of applicaion. For example, a major problem of reducing he swiching frequency a ligh loads is an increased curren ripple caused by he increased vol-second produc in he core of he oupu filer inducor. This increase in he ripple curren has an adverse effec on he efficiency because i increases he conducion loss. A major concern wih bulk-volage reducion and sage-shedding echniques is he dynamic performance. Specifically, heir abiliy o resore full-power capabiliy wihou oupu disurbance or oher performance deerioraion when he load suddenly changes from ligh load o full load. Finally, burs -mode operaion is limied o very low power levels primarily due o acousic noise. In his paper, a mehod of mainaining high powerconversion efficiency across he enire load range and is circui implemenaions are described. Specifically, he proposed mehod subsanially increases he conversion efficiency a ligh load by minimizing swiching and driving losses of semiconducor swiches, as well as core losses of magneic componens. These losses are minimized by periodically urning off and on he power converer wih a duy cycle se so ha when he converer is on i operaes a he power level ha exhibis he maximum efficiency. The required oupu power during he periods ha he converer is urned off is supplied from an energy-sorage device. The operaion and ligh-load efficiency performance of he proposed mehod was verified on a 0-W, 400-V/2-V dc/dc converer and a -kw ac/dc boos PFC fron end. II. METHO ESCRIPTION The proposed mehod of ligh-load efficiency opimizaion is based on a simple observaion ha he minimizaion of power loss requires ha he power converer is eiher always operaed a he load power wih he maximum efficiency or be compleely urned off. Namely, by resricing he operaion of a converer o only hese wo operaing poins he bes possible efficiency can be achieved because when he converer is urned off no loss is incurred, whereas when he converer is urned on i operaes wih he maximum efficiency. A concepual block diagram of he proposed ligh-load efficiency opimizaion mehod is shown in Fig. 2. The emporary energy sorage and power condiioning block in Fig. 2 serves o mainain a coninuous supply of load power during he periods he power converer is urned off. A power levels ha he power converer is coninuously on, his emporary energy sorage and power condiioning block is INPUT CONVERTER ( + OUTPUT FILTER) CONTROL OUTPUT P O P CHR P IS TEMPORARY ENERGY STORAGE & CONITIONING P LOA LOA Fig. 2. Concepual block diagram of proposed ligh-load efficiency opimizaion mehod. P O P CHR P IS T ON T OFF P LOA P O(AV) ( - ) P LOA P CHR(AV) P LOA P IS(AV) Fig. 3. Timing diagram of oupu power P O, charging power P CHR, and discharging power P IS. idle since he enire required load power is supplied by he power converer. As illusraed in he iming diagrams in Fig. 3, during ime periods T ON when he power converer is on, he power converer simulaneously supplies load power P LOA and charge power P CHR o he energy-sorage device. uring ime periods T OFF when he power converer is urned off, he load power is enirely suppored by he discharging of he energysorage device, i.e., P IS =P LOA. According o Fig. 3, average power P O(AV) delivered by he power converer o he load is PO ( AV ) = PLOA () and average power P IS(AV) delivered by he energy-sorage device o he load is PIS( AV ) = ( ) PLOA, (2) where =T ON /(T ON +T OFF ). Since average charging power P CHR(AV) mus be equal o average discharging power P IS(AV), he insananeous charging power P CHR during T ON is /09/$ IEEE 39

3 ( ) PCHR = P LOA, (3) as illusraed in Fig. 3. Therefore, oal insananeous power P delivered by he power converer during T ON is PLOA P = PO + PCHR = PLOA + PLOA =. (4) From Eq. (4), o improve he ligh-load efficiency of a power converer wih he efficiency dependence on delivered power as in Fig., opimal duy cycle OPT should be seleced from Eq. (4) as PLOA OPT =, (5) POPT i.e., he power converer during T ON should deliver power P OPT ha corresponds o he maximum efficiency. Theoreically, he power level ha his mehod of efficiency opimizaion can be applied is limied o he power level below P OPT. Typically, he boundary load power beween coninuous and pulse modes of operaion of he power converer P BOUN (<P OPT ) is se a ligh load levels where efficiency fall-off becomes pronounced, as illusraed in Fig. 4. In he derivaion of OPT in Eq. (5), i was assumed ha no loss is incurred during he charging and discharging of he energy-sorage device. If charging and discharging losses are included by assuming ha he energy-sorage device charging and discharging efficiencies are η CHR and η IS, respecively, opimal duy cycle is OPT OPT =, (6) POPT η ES + ( η ES ) P LOA where η ES = η CHR η IS is he efficiency of he energy sorage and power condiioning block. Wih charging and discharging losses included, he η η MAX η ES = η ES < conversion efficiency a power levels below P BOUN is given by η ES η = η MAX. (7) ( η ) OPT In he ideal case when no energy is los during he charging and discharging of he energy-sorage device, i.e., when η ES = is assumed, ligh-load efficiency is equal o η MAX all he way o a minimum load, as illusraed in Fig. 4. However, in pracice, because η ES < he ligh-load efficiency is lower han η MAX and exhibis a fall-off as power is reduced, as shown in Fig. 4. Generally, o achieve ligh-load efficiency improvemen, i is necessary o make a favorable rade-off beween he power saved by periodically urning-off he power converer and he power los in he charging and discharging process of he energy-sorage device. I should be noed ha while opimal duy cycle ES OPT is precisely defined by Eq. (6), once power level POPT and load power P LOA <P BOUN is known, he frequency a which he power converer is urned on and off can be se anywhere in a relaively wide frequency range. Generally, he upper frequency limi is relaed o he large signal dynamic response ime of he converer, whereas he lower frequency limi is deermined by he size and required energy-sorage capaciy of he energy-sorage device because a lower frequencies more sored energy is required o suppor he load power during prolonged off imes. For power levels of several hundred Was, ypical minimum frequency for elecrolyic-capacior-ype energy sorage is in he several- Herz o several-hundred-herz range, whereas sub-herz frequencies can be achieved by employing baeries, super capaciors, flywheels, and similar sorage devices. Finally, i should be noed ha i is desirable o keep he swiching frequency ouside he audio range o avoid acousic noise associaed wih he swiching of a relaively large power. Many variaions of he proposed efficiency opimizaion mehod are possible. Generally, hese variaions are relaed o realizaion of he charging and discharging pahs of he energy-sorage device. For example, he charging energy can be supplied from he inpu of he power converer insead of INPUT OUTPUT P O OUTPUT FILTER P LOA LOA P IS P CHR P LL P BOUN P OPT P FL P LOA CONTROL TEMPORARY ENERGY STORAGE & CONITIONING LIGHT LOA MI-RANGE HEAVY LOA Fig. 4. General illusraion of ligh-load efficiency improvemens obained by proposed efficiency opimizaion mehod. Fig. 5. Concepual block diagram of anoher implemenaion of proposed ligh-load efficiency opimizaion mehod /09/$ IEEE 40

4 from he oupu. Also, he proposed mehod can be implemened wih a common charging and discharging pah. Furhermore, he charging and discharging pahs do no need o be coupled direcly o inpu and/or oupu, bu can be coupled o any suiable poin in he power conversion pah. As an example, Fig. 5 shows he concepual implemenaion of his mehod where he charging and discharging pahs are coupled before he oupu filer of he power converer. If properly designed, hese implemenaions can reduce, or even compleely eliminae, ransiens caused by periodic urning on and off of he power converer. Namely, since in hese implemenaions he oupu-filer inducor curren is coninuously flowing, i.e., i is eiher supplied from he converer or from he discharging energy-sorage device, i does no exhibi significan ransiens if he circui is designed so ha he curren supplied by he converer when i is on and he curren supplied by he energy-sorage and condiioning circui during he off-ime are reasonably mached. III. CIRCUIT IMPLEMENTATIONS Figures 6(a)-(e) show several dc/dc converer implemenaions of he proposed efficiency opimizaion mehod. The power sage box in he figures can be any single or inerleaved power conversion opology such as, for example, half-bridge, full-bridge, single- or wo-swich forward, or LLC opology. Figures 6(a)-(c) show he implemenaions of he concep according o Fig. 5 where he discharging pah of he energy-sorage devices, i.e., capacior, is hrough he oupu filer of he power converer. Figures 6(d) and (e) show examples of he proposed mehod implemenaion according o Fig. 2 where he charging and discharging pahs of energy-sorage cap are coupled direcly o he oupu. In he implemenaion in Fig. 6(a), energy-sorage capacior is inducively charged by a dc oupu of he power sage when he power sage is urned on. uring he ime periods he power sage is urned off, he load power is provided by discharging hrough a buck converer ha shares he oupu filer wih he power sage. Generally, for isolaed power converer sages, inducance L in he charging pah can be he leakage inducance of he ransformer. The implemenaion of L as he leakage inducance of he ransformer is especially effecive in opologies where he leakage inducance of he ransformer is inenionally increased such as in he full-bridge converer wih phase-shif conrol or LLC resonan converer. The implemenaion in Fig. 6(b) employs a boos converer o charge energy-sorage capacior and a buck converer in he discharging pah. Because of he boos converer, energy sorage in capacior can be done a a higher volage, which makes i possible o reduce he size of he energy-sorage capacior. A variaion of his implemenaion ha employs a common charging and discharging pah is shown in Fig. 6(c). In his implemenaion a bi-direcional buck-boos converer is used o provide conrolled charging and discharging of he energy-sorage capacior. Figure 6(d) shows an implemenaion where he charging and discharging pahs of capacior are coupled o he oupu of he power converer. In fac, his implemenaion is a variaion of he implemenaion in Fig. 6(c) since he boos converer is used for charging and he buck for discharging. Finally, Fig. 6(e) shows he simples implemenaion of he proposed mehod. In his implemenaion energy-sorage V V 2 L L (a) S V CT 2 V V 2 L S L (b) S (c) (d) (e) C S ST Fig. 6. Examples of circui implemenaions of proposed ligh-load efficiency opimizaion mehod. C F /09/$ IEEE 4

5 LINE VOLTAGE - 4 IRFP23NL 3 I PRI LINE CURRENT 400 V OFF ON OFF OFF ON OFF T T ON T OFF T T OFF OFF ON 2 2 Fig. 7. Conrol implemenaion of proposed mehod in PFC applicaions. 2 TR Np=44 urns (AWG#8) Ns=2 urns, 0mils foil core=e34/26/9 -H7C4 N P - 2 TR MBR080G N S N S 2 CST 6000 uf V SR + - SR - SR 2 FB045AN08 S - FP047AN08 S CF 4000 uf 6 V 4 8 urns AWG#8 6 srands HF, u= A2 2V capacior is direcly conneced in parallel wih oupufiler capacior. In fac, in applicaions where he oupu filer capacior needs o sore significan energy such, for example, in PFC applicaions, addiional energy-sorage capacior may no be needed. When he proposed efficiency opimizaion mehod is applied o he ac/dc PFC fron end, i is necessary o recognize ha he line-curren harmonic limi specificaions need o be me down o 75 W of inpu power []. As a resul, a sraighforward implemenaion of his mehod where he fron-end power converer is periodically urned on and off wih an arbirary frequency is only possible below he inpu power of 75 W. Because of he required compliance wih he line-curren harmonic limi specificaions a inpu power levels above 75 W, he urning off and on of he converer can only be done wihin half-line cycles, as illusraed in Fig. 7. In he conrol approach shown in Fig. 7, he PFC converer is kep off near he zero-crossings of he line curren and is enabled for power processing around he peaks of he line curren. Since his conducion-angle conrol generaes line-curren disorions ha increase as urn-off ime T OFF increases, he maximum duraion of off ime T OFF is limied by he required harmoniclimi compliance of he line curren. This maximum off-ime can be easily figured ou for a given power level eiher by using simulaion or calculaion sofware. IV. EXPERIMENTAL RESULTS The performance of he proposed echnique was separaely evaluaed on a 0-W dc/dc converer and a -kw ac/dc PFC boos fron-end recifier. The circui diagram of he 0-W dc/dc converer prooype is shown in Fig. 8. The circui in Fig. 8 implemens he proposed mehod of ligh-load efficiency opimizaion according o Fig. 6(a) where V =V 2 Fig. 8. Circui diagram of 0-W, ZVS full-bridge dc-dc converer laboraory prooype. Added emporary energy sorage and power condiioning circui are shown inside dashed-line recangular. and L is he leakage inducance of ransformer TR, i.e., i combines a ZVS full-bridge converer wih phase-shif conrol wih a synchronous-buck converer discharging circui. The 0-W dc/dc prooype was designed o operae from a 400-V dc inpu and deliver up o 42 A a a 2-V oupu. The full-bridge converer operaing a 0-kHz swiching frequency was implemened wih an IRFP23NL MOSFET from IR for each bridge swich - 4, whereas a FB045AN08 MOSFET from Fairchild was employed for each synchronous recifier SR and SR 2. Transformer TR was buil using a pair of ferrie E-cores (E34/26/9-H7C4) wih 44 urns of magne wire (AWG# 8) for he primary winding and 2 urns of copper foil (0 mil, 20 mm) for each of he secondary windings. Oupu filer inducor was buil using a oroidal high flux core (58894A2, u=60) from Magneics wih 8 urns of magne wire (6 srands, AWG #8). Four low volage aluminum capaciors (000 µf, 6 VC) were used for oupu capacior. The buck converer ha is periodically urned on a ligh loads o deliver power from energy-sorage capacior was implemened wih an FP047AN08 MOSFET from Fairchild for boh he buck swich S and synchronous-recifier swich. Schoky diodes MBR080G from On Semi were used for charging diodes and 2. Finally, six low volage aluminum capaciors (000 µf, VC) were used as sorage capacior. I should be noed ha he buck converer shares he oupu filer, i.e., oupu inducor and SR /09/$ IEEE 42

6 oupu capacior, wih he full-bridge converer. The swiching frequency of he buck converer was se o approximaely 00 khz. This frequency is close enough o he 0-kHz frequency of he full bridge o keep he oupu filer-inducor curren virually unchanged during ransiions beween he full-bridge and buck operaion, which ensures smooh ransiions beween hese wo modes of operaion. Since he full-bridge converer and he buck converer do no operae a he same ime, a frequency synchronizaion of wo converers was no necessary. The maximum oupu power of V I IN L 56 urns AWG#7 wo HF cores 58929A2 u=47 S IPP60R099CS wo in parallel CS0060 C 560 uf 4 V 400V GSIB2560 I PRI [ A/div] Fig.. Circui diagram of experimenal -kw PFC boos recifier. V 2 [0 V/div] 0 ms/div [20 V/div] I PRI [ A/div] V 2 [0 V/div] P O = 20 W 5uS/div I IN [2 A/div] [ V/div] Fig. 9. Measured primary-curren I PRI and swich 2 drain-o-source volage V 2 waveforms of ZVS full-bridge converer prooype. Time scale for upper wo races is [0 ms/div]. Time scale for boom wo races is [5 us/div]. P O = 75 W =00 V = 400 V I IN Efficiency [%] PROPOSE CONVERTER P 5% 40 ORIGINAL FULL-BRIGE CONVERTER P 0% 20 BUCK CONVERTER (STAN ALONE) Oupu Power [W] η MAX = 92% P BOUN P OPT Fig. 0. Measured efficiencies of original full-bridge converer, sand-alone buck converer, and proposed converer as funcions of oupu power. Fig. 2. Measured waveforms of experimenal PFC boos recifier. is line volage, I IN is line curren, and oupu volage. he buck converer was designed o be approximaely 40 W which is enough o deliver up o 25% of he oal oupu power. Figure 9 shows he measured waveforms of he prooype circui a approximaely 20 W, whereas Fig. 0 shows measured efficiency of he proposed converer along wih he measured efficiencies of he full-bridge converer and he buck converer. As can be seen from Fig. 0, he proposed converer exhibis higher efficiencies below approximaely 00 W. The improvemen of he efficiency is more pronounced as he load becomes ligher. For example, a W, which is 0% of he full load, he efficiency improvemen is around 8%, whereas a 25 W, i.e., a 5% of he full load, he improvemen is approximaely 24%. Figure shows he circui diagram of he PFC boos recifier prooype build o evaluae he performance of he proposed mehod in ac/dc applicaions. The -kw, 0-kHz PFC boos recifier prooype was designed o operae from a universal ac-line inpu ( V RMS -264 V RMS ) and deliver up o /09/$ IEEE 43

7 00 ms OPERATION W/ CONUCTION ANGLE CONTROL T ON as he oupu power reduces. Wih his kind of conrol, he ligh-load efficiency is represened by he dashed line in Fig. 3. Efficiency [%] ms ms T =7 ms ON OPERATION W/O CONUCTION ANGLE CONTROL Oupu Power [W] = 00 V A from a 400-V oupu. The prooype employs wo IPP60R099CS MOSFETs (V SS = 600 V, R S = Ω) in parallel for boos swich S and a CS0060 SiC diode (V RRM = 600 V, I FAVM = 0 A) for boos diode. In his implemenaion, he 560-µF bulk capacior C B ha is sized based on he hold-up ime requiremen also serves as energysorage capacior. Figure 2 shows he oscillograms of he inpu curren, inpu volage, and oupu volage waveforms of he PFC recifier prooype wih he conducion-angle conrol. To simplify he experimen, i.e., o avoid implemening a conducion-angle conrol iself, he conducion angle of he inpu volage waveform was acually conrolled by a programmable ac source (6000LX, California Insrumen). Because in he PFC boos recifier he inpu curren waveform follows he inpu volage waveform, he desired operaion was achieved wihou any modificaions of he PFC conrol circui. The measured efficiencies of he PFC recifier wih and wihou conducion-angle conrol are shown in Fig. 3. As can be seen from Fig. 3, conducion-angle conrol was applied a power levels below 00 W, i.e., below 0% of he full power. Wih he conducion-angle conrol, he prooype PFC recifier exhibis higher ligh-load efficiencies. In fac, a he same power level, he efficiency gains are larger as conducion ime T ON decreases from 7 ms o ms. However, as he conducion ime reduces he maximum power ha can be delivered o he oupu also reduces. The maximum lighload efficiency gains can be obained by implemening acive conducion-ime conrol, i.e., by reducing conducion ime = 400 V Fig. 3. Measured efficiency of PFC recifier as funcions of oupu power for differen conducion imes T ON. ashed line represens efficiency ha can be obained by changing (decreasing) T ON as oupu power decreases. V. SUMMARY A mehod of improving he ligh-load efficiency of power converers is proposed. In he proposed mehod, he ligh-load efficiency improvemen is achieved by periodically urning off he power converer o reduce swiching-relaed losses. uring he ime periods he converer is urned off, he required load power is supplied from an energy-sorage device. uring he ime periods when he converer is delivering power o he load and charging he energy-sorage device, i is conrolled so ha i operaes a he power level ha corresponds o he maximum conversion efficiency. The proposed efficiency opimizaion mehod is applicable o any power conversion dc/dc or ac/dc sysem or opology. Generally, he energy sorage medium can be any componen/device ha can sore energy such as, for example, capaciors, baeries, flywheels, ec. The performance of he proposed mehod is verified on wo experimenal prooypes; a 0-W, ZVS full-bridge dc/dc converer and a -kw boos PFC converer. Boh prooypes showed remarkable ligh-load efficiency improvemens wih he proposed approach all he way down o 5% load. REFERENCES [] Power Inegraions, Inc., Company Web Sie, Green Room page a hp:// [2] 80Plus Program, hp:// [3] Climae Savers Compuing Iniiaive (CSCI) Web Sie, Home page hp:// Efficiency Specificaion page hp:// [4] Environmenal Proecion Agency (EPA) Energy Sar Program, Version 5.0 Compuer Specificaions, hp:// [5] F. C. Lee, P. Barbosa, P. Xu, J. Zhang, B. Yang, and F. Canales, Topologies and design consideraions for disribued power sysem applicaions, Proceedings of he IEEE, vol. 89, no. 6, June 200, pp [6] F. C. Lee, M. Xu, S. Wang, and B. Lu, esign challenges for disribued power sysems, IEEE In l Power Elecronics & Moion Conrol Conf. (IPEMC) Proc., Key Noe Speech PA, Shanghai, China, [7] H. S. Choi and.y. Huh, Techniques o minimize power consumpion of SMPS in sandby mode, IEEE Power Elecronics Specialis s Conf. (PESC) Record, pp , [8] P. Vinciarelli, Adapive Boos Swiching Preregulaor and Mehod, US Paen [9] S. W. Hobrech and R. G. Flaness, Muliple phase swiching regulaors wih sage shedding, US Paen [0] J. Choi,. Huh, and Y. Kim, The improved burs mode in he sandby operaion of power supply, IEEE Applied Power Elecronics Conf. (APEC) Proc., pp , [] Elecromagneic compaibiliy (EMC) Par3: Limis Secion 2: Limis for harmonic curren emissions (equipmen inpu curren < 6 A per phase), IEC , /09/$ IEEE 44