The Single-Stage TAIPEI Rectifier

Transcription

1 The Single-Sage TAIPEI Recifier Yungaek Jang, Milan M. Jovanović, and Juan M. Ruiz Power Elecronics Laboraory Dela Producs Corporaion 5101 Davis Drive, Research Triangle Park, C, USA Absrac A new hree-phase, single-sage, isolaed zerovolage-swiching (ZVS) recifier ha achieves less han 5% inpu-curren oal harmonic disorion (THD) and provides ighly regulaed oupu volage is inroduced. The proposed circui is obained by inegraing he hree-phase, wo-swich, ZVS, disconinuous-curren-mode (DCM), boos power-facorcorrecion (PFC) recifier wih he ZVS full-bridge (FB) phaseshif dc/dc converer. The performance evaluaion of he circui was performed on a hree-phase 1.8-kW prooype designed for he line-o-line volage range of V RMS and delivering a ighly regulaed, selecable, dc oupu volage from 0 V o 300 V. I. ITRODUCTIO Generally, modern off-line power supplies consis of a fron-end power-facor-correcion (PFC) recifier followed by an isolaed dc-dc converer. In single-phase implemenaions, he PFC fron-end is ypically implemened eiher as a convenional boos converer, an inerleaved boos converer, or a bridgeless boos converer [1]. In hreephase applicaions, he six-swich boos converer and Vienna recifier are he mos commonly used fron-end opologies []. In high-performance applicaions, he Vienna recifier is he preferred opology because i offers he highes efficiency wih oday s commercially available Si semiconducor devices. The choice of isolaed dc/dc oupu-sage opology is primarily dependen on he power level. A lower power levels, flyback and forward opologies are usually employed, whereas he bridge-ype opologies are ypically used a power levels over W. In oday s ac/dc power supplies ha need o mee exremely challenging efficiency requiremens across he enire load range, he zero-volageswiching (ZVS) full-bridge (FB) converer wih phase-shif conrol, he wo-swich inerleaved forward converer, and LLC series-resonan converer are exclusively used as dc/dc oupu sage. In hree-phase applicaions wih nominal lineo-line volage 380/480 V, where he oupu volage of he fron end is in he V range, he dc/dc oupu sage is eiher implemened by connecing inpus of wo converers in series and heir oupus in parallel, or by employing a hree-level dc/dc opology [3]-[5]. Boh of hese approaches make possible o use 600-V-raed Si MOSFET devices which are more efficien compared o 100-V-raed IGBTs. Alhough he wo-sage off-line conversion has demonsraed excellen performance, power supply designers have always been emped o combine he wo sages ino a single sage o reduce he cos and/or o increase he power densiy. For example, various hree-phase, single-sage implemenaions have been inroduced in [5]-[10]. Generally, hey eiher inegrae a hree-phase boos recifier wih an isolaed dc/dc sage [5]-[8], or combine hree singlephase, single-sage isolaed converers ino a hree-phase isolaed converer [9] and [10]. A high PF and low inpu curren THD in he implemenaions in [5]-[8] were obained by operaing he inegraed boos sage in he disconinuousconducion mode (DCM) where he phase currens naurally follow he respecive phase volages, i.e., wihou any acive curren conrol. Generally, hese implemenaions can achieve curren THD from approximaely 5% o 15% in he load range from full load down o 50% load. While his is accepable performance in many applicaions, i is no good enough for applicaions in oday s compuer/elecom power sysems which in his load range require THD below 5%. In his paper, a single-sage hree-phase recifier ha mainains curren THD below 5% from full load down o 0% load is proposed. The proposed recifier is derived by inegraing he recenly proposed hree-phase, wo-swich, ZVS PFC DCM boos recifier, shorened o he TAIPEI recifier [11], wih a convenional phase-shif, ZVS FB converer [1]. In addiion o exhibiing an excellen THD and PF performance, he recifier offers ZVS of all swiches in a wide oupu-curren range which reduces swiching losses and improves efficiency. The performance of he proposed single-sage TAIPEI recifier was evaluaed on a hree-phase 1.8-kW prooype designed o operae in he lineo-line volage range from 180 V RMS o 64 V RMS and deliver a ighly regulaed, selecable, oupu volage from 0 V o 300 V. 0 V A V B V C C 1 C C 3 Fig. 1. L L 3 S 1 S S 3 MAI COTROL AD DRIVER PHASE-SHIFT COTROL TAIPEI RECTIFIER D 1 D D 3 C R D 4 D 5 D 6 R COTROLLER FREQUECY COTROL V O C O Proposed single-sage TAIPEI recifier. S 1 S L O FULL-BRIDGE COVERTER C B D O1 D O S 3 TR /13/$ IEEE 104

2 II. THREE-PHASE SIGLE-STAGE TAIPEI RECTIFIER The circui diagram of he proposed hree-phase, singlesage Taipei recifier is shown in Fig. 1. In his circui, swiches S 1 and S simulaneously serve as he swiches of he boos fron end and leading-leg swiches of he ZVS FB. A he inpu side, hree boos inducors, L, and L 3 are conneced o he hree-phase power-source erminals along wih hree differenial-mode filer capaciors C 1, C, and C 3 conneced in Y ( sar ) configuraion. Since for a balanced hree-phase power source, he poenial of he common node of he filer capaciors, labeled in Fig. 1, has he same poenial as power source neural 0 ha is no physically available or conneced in hree-wire power sysems, node represens a virual neural. Virual neural is conneced o he mid-poin beween wo swiches S 1 and S. As a resul of connecing virual neural direcly o he mid-poin beween swiches S 1 and S, decoupling of he hree inpu currens is achieved. In such a decoupled circui, he curren in each of he hree inducors is dependen only on he corresponding phase volage, which reduces he THD and increases he PF [11]. In addiion, he mid-poin of he swiches do no experience abrup changes wih high dv/d, which makes i possible for he recifier o operae wih a relaively low common-mode EMI noise. Swiches S 3 and serve as he lagging-leg swiches of he phase-shif FB converer whose primary also includes isolaion ransformer TR and blocking capacior C B. In Fig. 1, he secondary-side of he FB converer is implemened wih he cener-apped secondary winding, oupu diodes D O1 and D O, and oupu filer L O - C O. However, in some applicaions i may be more appropriae o implemen secondary side wih a full-bridge recifier or employ synchronous recifiers (SRs) insead of he diode oupu recifiers. Since swiches S 1 and S operae as he PFC boos swiches as well as he leading leg swiches of he ZVS FB circui, he energy required o achieve ZVS of swiches S 1 and S is sored boh in boos inducors -L 3 and he leakage inducance of ransformer TR. Because he inducance of he boos inducors is relaively large, hey sore enough energy for complee ZVS of swiches S 1 and S even a very low power levels. As a resul, in he proposed circui in Fig. 1, he leakage inducance of he ransformer can be minimized. This improves he performance of he ZVS FB converer because i minimizes he secondary-side duy-cycle loss and parasiic ringing beween he juncion capaciance of he secondary-side recifier and he leakage inducance [1]. The energy required o achieve ZVS of lagging-leg swiches S 3 and is sored in oupu inducor L O. Since he inducance of he oupu-filer inducor is also large, all four swiches in he proposed converer can achieve ZVS in a wide inpuvolage and load range wihou an addiional energy-sorage inducor in series wih he ransformer primary, which is ypically employed in convenional ZVS FB converers o exend he ZVS range. As illusraed in Fig. 1, o simulaneously achieve low inpu-curren harmonic disorions and igh oupu-volage V A V C V B L D 1 D 5 L 3 D 6 S 1 S Fig.. Simplified circui diagram of proposed single-sage Taipei recifier. regulaion, he proposed single-sage recifier employs wo feedback conrol loops. A low bandwidh (below several ens of Hz) frequency-conrolled loop is used o regulae bus volage and indirecly shape he disconinuous inducor currens o follow he respecive phase volage wih low harmonic disorions. A high bandwidh (in he khz range) phase-shif conrol loop is employed o ighly regulae oupu volage V O wih negligible recified-line- and swiching-frequency ripple. I should be noed ha he proposed single-sage TAIPEI recifier is opologically idenical o ha described by Huang e al. in [8]. However, he inpu-curren THD and efficiency performance of he wo implemenaions are dramaically differen because of differen conrol approaches. The implemenaion in [8] regulaes only he oupu volage wih a consan-frequency conrol ha canno achieve THD below 5% and does no provide ZVS of all four swiches. III. AALYSIS OF OPERATIO The simplified circui diagram of he proposed recifier along wih reference direcions of currens and volages is shown in Fig.. I should be noed ha he model in Fig. is only valid in he 60 0 segmen of he line cycle where V A > 0, V B <0, and V C <0. However, he same model is applicable o any oher 60 0 segmen during which he phase volages do no change polariy by properly selecing conducing recifiers in he inpu six-diode recifier [11]. The model in Fig also assumes ha he volage across blocking capacior C B is much smaller han he volage across he primary of ransform TR, i.e., ha he capaciance of he blocking capacior is large enough so ha he capacior volage drop caused by he primary curren is small. In Fig. he blocking capacior C B is represened by a shor circui. To furher faciliae he explanaion of operaion, Fig. 3 shows opological sages of he circui in Fig. during a swiching cycle, whereas Fig. 4 shows he power-sage key waveforms. As can be seen from he gae-drive iming diagrams for swiches S 1 - in Fig. 4, he swiches operae in a complemenary fashion wih approximaely 50% duy cycle and wih a shor dead ime beween he urn-off of one swich and he urn-on of he oher swich of each leg. Because of his gaing sraegy, all swiches can achieve ZVS. In he proposed single-sage recifier, he inpu power is conrolled by S 1 and S employing a variable swiching TR D O1 S V 3 P 1 V C CR CR D O i S3 i S4 1043

3 C OSS1 V A V A V A V C V B V C V B C OSS V C V B (a) [ T - T ] 0 1 (b) [ T - T ] 1 (c) [ T - T ] 3 V A V A V A V C V B V C V B V C V B (d) [ T - T ] 3 4 (e) [ T - T ] 4 5 (f) [ T - T ] 5 6 V A V A C OSS1 V A V C V B V C V B COSS V C V B (g) [ T - T ] 6 7 (h) [ T - T ] 7 8 (i) [ T - T ] 8 9 V A V A V A V C V B V C V B V C V B (j) [ T - T ] 9 10 (k) [ T - T ] (l) [ T - T ] 11 1 V A V A V C V B V C V B (m) [ T - T ] 1 13 (n) [ T - T ] Fig. 3. Topological sages of proposed single-sage TAIPEI recifier wih condiion when V A > 0, V B < 0, and V C < 0. frequency conrol. The minimum frequency is se a full load and minimum inpu volage, whereas he maximum frequency is se a ligh load and maximum inpu volage. The oupu volage is ighly regulaed by phase-shif conrol beween he S 1 -S leg and he S 3 - leg. In his conrol, he swiching ransiion of swiches in he S 3 - leg of he bridge is delayed, i.e., phase shifed, wih respec o he swiching ransiion of corresponding swiches in he S 1 -S leg. By conrolling he angle of he delay wih a high bandwidh feedback loop, he oupu volage is ighly regulaed. The recifier operaes in conrolled burs mode a ligh load or no load o avoid unnecessarily high swiching frequency. As shown in Figs. 3(a) and 4, before swich S 1 is urned off a =T 1, inducor curren flows hrough swich S 1. The slope of inducor curren is equal o V A / and he peak of he inducor curren a =T 1 is approximaely [11] VA TS I(PK) =, (1) L1 where V A is line-o-neural volage and T S he swiching period. 1044

4 During he period beween T 0 and T 1, oupu diodes D O1 and D O conduc oupu curren and he secondary winding of ransformer TR is shored, as shown in Fig. 3(a). During his inerval, primary curren decreases wih he rae V S(O) /L LK where L LK is he leakage inducance of ransformer TR (no shown in Fig. 3) and V S(O) is he onsae volage drop of he swich. A =T 1, when swich S 1 is urned off, inducor curren sars charging he oupu capaciance of swich S 1, as shown in Fig. 3(b). Because he sum of he volages across swich S 1 and swich S is clamped o he flying capacior volage, he oupu capaciance of swich S discharges a he same rae as he charging rae of he oupu capaciance of swich S 1. This period ends when he oupu capaciance of swich S is fully discharged and he ani-parallel body diode of swich S sars conducing a =T, as shown in Fig. 3(c) and Fig. 4. Because he body diode of swich S is forward biased, inducor currens and begin o increase linearly. When he body diode of swich S sars conducing, primary volage of ransformer TR reaches which T S S 1 S S 1 O S O S 1 O S O S 3 V S1 V S O S 3 O O S 3 O V A - V A -V C L 3 Fig. 4. Key waveforms of proposed single-sage TAIPEI recifier when V A > 0, V B < 0, and V C < 0. -V B -V B L i L L ZVS V B L -n DT S V C -V A L 3 -V C L 3 ZVS V A -V B L n - V -V CR C V -V B A L 3 L L n = 1 makes oupu diode D O1 reverse biased, as shown in Fig. 3(c). During his period, primary curren is equal o -n, where n= / 1 is he urns raio of he ransformer. A =T 3, swich S is urned on wih ZVS and inducor currens,, and are commuaed from he aniparallel diode of swich S o he swich, as shown in Fig. 3(d). This period ends when inducor curren decreases o zero a =T 4. To mainain DCM operaion, he ime period beween =T 3 and =T 4 mus be less han one-half of swiching period T S which means ha he rising slope of inducor curren should be smaller han is falling slope. As illusraed in Fig. 4, he rising and falling slopes of are V A / and (V A - )/, respecively. As a resul, minimum volage (MI) across flying capacior C R o achieve DCM operaion is VCR(MI) = VA(PK) = VL L( RMS), () 3 where V A-PK is he peak line-o-neural volage. I should also be noed ha because during he T -T 4 inerval inducor currens and and primary curren flow in he opposie direcion from inducor curren, he average curren hrough swich S is reduced so ha he swich in he proposed recifier exhibis reduced power losses. A ime =T 5, swich S 3 is urned off, primary curren, ha is refleced oupu curren n, charges he oupu capaciance of swich S 3 o flying capacior volage which makes he ani-parallel body diode of swich o sar conducing, as shown in Fig. 3(f). A =T 6, swich is urned on wih ZVS and primary curren is commuaed from he aniparallel diode of swich o he swich as shown in Fig. 3(g). During he period beween T 5 and T 7, oupu diodes D O1 and D O conduc oupu curren and he secondary winding of ransformer TR is shored so ha primary curren increases wih he rae V S(O) /L LK, as shown in Figs. 3(f) and 3(g). During he period beween =T and =T 7, inducor currens and coninue o flow hrough swich S as shown in Fig. 4. The slopes of inducor currens and during his period are equal o V B /L and V C /L 3, respecively, and heir peaks a he momen when swich S urns off are approximaely VB TS IL (PK) = and (3) L VC TS I L 3(PK) =. (4) L3 As i can be seen in Eqs. (1), (3), and (4), he peak of each inducor curren is proporional o is corresponding phase volage, which resuls in a low THD of he phase currens [11]. Afer swich S is urned off a =T 7, inducor currens and sar o simulaneously charge he oupu capaciance of swich S and discharge he oupu capaciance of swich S 1, as shown in Fig. 3(h). This period ends a =T 8 when he oupu capaciance of swich S 1 is fully discharged and is ani-parallel diode sars conducing, as shown in Fig. 3(i) and Fig. 4. Afer =T 8, swich S 1 can be urned on wih ZVS. In Fig. 4, swich S 1 is urned on a =T 9. As shown in Fig. 1045

5 3(j), once swich S 1 is on, increasing inducor curren and primary curren flow in he opposie direcion from inducor currens and hrough swich S 1 so ha swich S 1 carries only he difference of sum of curren and primary curren and sum of currens and. This period ends when inducor curren decreases o zero a =T 10. During period T 10 -T 11, decreasing inducor curren coninues o flow hrough swich S 1, as shown in Fig. 3(k). Afer inducor curren reaches zero a =T 11, swich is urned off a =T 1 and primary curren charges he oupu capaciance of swich o. The ani-parallel body diode of swich S 3 sars conducing a =T 1, as shown in Fig. 3(m). A =T 13, swich S 3 is urned on wih ZVS and primary curren is commuaed from he aniparallel diode of swich S 3 o he swich, as shown in Fig. 3(n), and a new swiching cycle begins. In he proposed recifier, oupu volage V O is relaed o he average volage across flying capacior (AVG) as V A V B V C L1, L, L3 PQ40/40-3C96 Liz 0.1mmx360 6T, 50 uh EMI FILTER C1, C, C3.uF /450 V Fig. 5. C 1 C C 3 L L 3 D1-D6 STTH30R06 D 1 D D 3 D 4 D 5 D 6 TR (18T:18T:18T) PQ50/50-3C90 Pri.=Liz 0.1mmx300 Sec.=Liz 0.1mmx180 Lm=85uH, Llk=0.5uH C R R CR x70uf/450 V V O Experimenal prooype circui of proposed recifier. S 1 S C O L O CB.uF S 3 /450 V V CB TR C B Co 70uF /450 V S1 - S4 IPW65R041CFD D O1 D O Do1, Do C4D1010 Lo PQ40/40-3C96 Liz 0.1mmx300 34T, 5 uh V = n D, (5) O (AVG) THD=1.% where duy cycle D is he phase shif shown in he gaeiming waveforms in Fig. 4. The value of volage (AVG) is deermined by he regulaion se poin of he low-bandwidh variable-frequency conrol loop and is minimum value has o mee Eq. (). Finally, i should be noed ha in he proposed recifier he inpu curren is no sensed. The inpu curren shaping is obained naurally by seing he recifier s oupu-volageconrol bandwidh much lower han he line frequency, i.e., by mainaining swiching period T S virually consan during a line cycle. Wih a consan swiching period T S and 50% duy cycle, he peaks of he inducor currens are proporional o he corresponding phase volages. For such a riangular curren waveform, he line-frequency averagecurren disorion is predominanly conained in he 3 rd harmonic. Since he 3 rd harmonic (riplen harmonic) currens canno flow in a hree-wire sysem, hey circulae hrough capaciors C 1, C, and C 3, whereas he remaining harmonics conribues less han 1% of inpu-curren THD, as described in [11]. (a) THD=1.1% IV. EXPERIMETAL RESULTS The performance of he proposed recifier was evaluaed on a 1.8-kW prooype circui ha was designed o operae from a V L-L(RMS) hree-phase inpu and deliver a ighly regulaed selecable oupu volage from 0 V o 300 V. The applicaion argeed by his inpu/oupu specificaion was he hree-phase, isolaed fron end for high-volage (HV) DC disribuion power sysems. The prooype circui was designed wih he variablefrequency-conrol-loop bandwidh of 10 Hz and he phaseshif-conrol-loop bandwidh of khz. The low-bandwidh frequency-conrol loop was used o regulae he flyingcapacior volage o 400 V. The swiching frequency range of he variable-frequency conrol was beween 50 khz and 300 khz. (b) (c) Fig. 6. Measured inpu curren waveforms when recifier operaes from hree-phase inpu volage 30 V L-L(RMS) and delivers: (a) 1.8 kw; (b) 1.5 kw; (c) 900 W. Time scale is 5 ms/div. THD=3.4% 1046

6 Figure 5 shows he power-sage schemaics along wih componen informaion of he experimenal prooype circui. Since he volage sress of all primary swiches S 1 - is approximaely equal o flying capacior volage of 400 V, swiches ha are raed a leas 500 V mus be used o mainain he desirable design margin of 0%. In he prooype circui, an IPW65R041CFD MOSFET (V DS = 650 V, R DS = Ω, C OSS =400 pf, Q rr =1.9 μc) from Infineon was used for each swich. Since inpu diodes D 1 - D 6 block he same peak volage sress and conduc he same peak curren (approximaely 0 A) as he swiches, an STTH30R06 diode (V RRM = 600 V, I FAVM = 30 A) from ST was used for each diode. A C4D1010 SiC diode (V RRM = 100 V, I FAVM = 10 A) from Cree was used for each oupu diode because heir volage sress is wice he peak volage across he primary winding of ransformer TR since he urns raio of ransformer TR is n=1. To obain he desired inducance of boos inducors, L, and L 3 of approximaely 50 μh and also o achieve high efficiency a ligh-load, each inducor was buil using a pair of ferrie cores (PQ-40/40, 3C96) wih 6 urns of Liz wire (Φ 0.1mm, 360 srands) and approximaely 8 mm gap. Liz wire was used o reduce he fringing-effec-induced winding loss near he gap of he inducor core. Transformer TR was buil using a pair of ferrie cores (PQ-50/50, 3C96) wih 18 urns of Liz wire (Φ 0.1mm, 300 srands) for he primary winding and 18 urns of Liz wire (Φ 0.1mm, 180 srands) for he wo secondary windings ha form he cener-ap secondary srucure. The measured magneizing and leakage inducances are 85 μh and 0.5 μh, respecively. Oupu inducor L O was buil using a pair of ferrie cores (PQ-40/40, 3C96) wih 34 urns of Liz wire (Φ 0.1mm, 300 srands) wih approximaely 1 mm gap. Is measured inducance is 5 μh. Two parallel conneced aluminum capaciors (70 μf, 450 VDC) were used for flying capacior C R and a film capacior (. μf, 450 VDC) was used for each inpu filer capacior C 1, C, and C 3 as well as for blocking capacior C B. An aluminum capacior (70 μf, 450 VDC) was used for oupu capacior C O. Figures 6(a)-(c) show he measured inpu curren waveforms of he experimenal circui a he inpu volage of 30 V L-L(RMS) and hree differen power levels. The measured inpu-curren THDs are approximaely 1.%, 1.1%, and 3.4% a 1.8 kw, 1.5 kw, and 900 W, respecively. To illusrae he ZVS of he primary swiches, Fig. 7 shows drain-o-source volages V S and V S4 of swiches S and (he ground referenced swiches) ogeher wih heir gae driving volages V S-GATE and V S4-GATE a full power and for he inpu volage of 30 V L-L(RMS). As i can be seen in Fig. 7, he drain-o-source volages of he swiches become zero before he swiches are urned on. Complemenary swiches S 1 and S 3 (no shown) operae in he same manner. Figure 8 shows he measured curren waveforms of boos inducors, L, and L 3 of he experimenal circui a full power, 1.5 kw, and 900 W when i operaes from hreephase inpu volage 30 V L-L(RMS). The experimenal V S-GATE [5 V/div] V S [50 V/div] V S4-GATE [5 V/div] V S4 [50 V/div] Fig. 7. Measured waveforms of swich volages V S and V S4 ogeher wih heir gae driving volages V S-GATE and V S4-GATE when recifier delivers full power from hree-phase inpu volage 30 V L-L(RMS). Time scale is μs/div. =400 V V O =0 V f S =9 khz (a) (b) ZVS ZVS =400 V, V O =0 V, f S =3 khz (c) Fig. 8. Measured waveforms of inducor currens,, and when recifier operaes from hree-phase inpu volage 30 V L-L(RMS) and delivers: (a) 1.8 kw; (b) 1.5 kw; (c) 900 W. Time scale is μs/div. il =400 V, V O =0 V, f S =110 khz =400 V, V O =0 V, f S =18 khz 1047

7 5 =400 V, V O =300 V, f S =110 khz (a) THD [%] V = 0 V O V = 300 V O V I=08 VL-L Oupu Power [W] Fig. 11. Measured THDs of experimenal PFC recifier prooype as funcions of oupu power. =400 V, V O =0 V, f S =110 khz (b) Fig. 9. Measured waveforms of drain currens of swich S 1 and of swich S ogeher wih primary curren I P of ransformer TR when recifier delivers full power from hree-phase inpu volage 30 V L-L(RMS) and regulaes oupu volage: (a) 300 V and (b) 0 V. Time scale is μs/div. Efficiency [%] V = 0 V O V = 300 V O V I=08 VL-L Oupu Power [W] Fig. 10. Measured efficiencies of experimenal PFC recifier prooype as funcions of oupu power. waveforms are in very good agreemen wih corresponding ideal waveforms shown in Fig. 4. Figure 9 shows he waveforms of he drain currens of swiches S 1 and S along wih he waveform of primary curren of ransformer TR a full power and 30 V L-L(RMS) for he oupu volage regulaed a 300 V and 0V. The reason for a noiceable discrepancy beween he measured curren waveforms of swiches S 1 and S and corresponding ideal waveforms in Fig. 4 is he assumpion ha he volage of he blocking capacior is zero, i.e., modeling he blocking capacior wih a shor circui in Fig.. In he prooype circui, he peak ac volage across blocking capacior C B caused by he primary curren flowing hrough i is around 30 V and is effec canno be negleced. In fac, his volage causes a relaively large decrease of he swich currens during he ime inervals he secondary winding of he ransformer is shored, i.e., during inervals T 5 -T 7 and T 1 -T 14 in Fig. 3, because he blocking capacior volage reses (decreases) he ransformer primary curren wih a relaively high rae V CB /L LK. Finally, he measured efficiency and THD of he proposed recifier as funcions of oupu power a he linevolage of 30 V L-L(RMS) are shown in Fig. 10 and Fig. 11, respecively. The measured efficiency is beween 94% and 95.5% from full load down o 40% of he full load while he measured THD is below 5% in he enire measured range of power. V. SUMMARY In his paper, he hree-phase single-sage recifier ha is derived by combining he recenly inroduced Taipei recifier and a convenional phase-shif full-bridge converer has been described. The proposed recifier offers low inpu-curren THD (< 5%) and a ighly regulaed, isolaed, oupu volage and feaures ZVS of all he swiches over he enire inpu and load range. The evaluaion of he proposed converer was performed on a hree-phase 1.8-kW prooype operaing from he line-o-line volage range of V RMS and delivering a ighly regulaed selecable oupu volage from 0 V o 300 V. The measured efficiency of he proposed recifier is beween 94% and 95.5% from full load down o 40% load. REFERECES [1] M.M. Jovanović and Y. Jang, Sae-of-he-ar, single-phase, acive power-facor-correcion echniques for high-power applicaions an overview, IEEE Transacions on Indusrial Elecronics, vol. 5, o. 3, pp , Jun

8 [] J. W. Kolar and T. Friedli, The essence of hree-phase pfc recifier sysems, Proc. IEEE In. Telecommun. Energy Conf. (ITELEC) Rec., 011, Plenary Session, Paper 1.1. [3] J. R. Pinheiro and I. Barbi, The hree-level zvs-pwm dc-o-dc converers, IEEE Transacions on Power Elecronics, vol. 8, o. 4, pp , Oc [4] X. Ruan, L. Zhou, and Y. Yan, Sof-swiching pwm hree-level converers, IEEE Trans. Power Elecronics, vol. 16, no. 5, pp. 61 6, 001. [5] P.M. Barbosa, F. Canales, J.M. Burdio, and F.C. Lee, The hree-level converer and is applicaion o power facor correcion, IEEE Transacions on Power Elecronics, vol. 0, o. 6, pp , ov [6] J.G. Conreras and I. Barbi, A hree-phase high power facor pwm zvs power supply wih a single power sage, IEEE Power Elecronics Specialiss Conf. (PESC) Proc., pp , [7] F.S. Hamdad and A.K.S. Bha, A novel sof-swiching high-frequency ransformer isolaed hree-phase ac-o-dc converer wih low harmonic disorion, IEEE Transacions on Power Elecronics, vol. 19, o. 1, pp , Jan [8]. Huang, D. Zhang, T. Song, M. Fan, and Y. Liu, A 10 kw singlesage converer for welding wih inheren power facor correcion, IEEE Applied Power Elecronics Conf. (APEC) Proc., pp , 005. [9] M.J. Kocher and R. L. Seigerwald, An ac-o-dc converer wih high qualiy inpu waveform, IEEE Transacions on Indusry Applicaions, vol. 19, o. 4, pp , Jul./Aug [10] R. Ayyanar,. Mohan, and J. Sun, Single-sage hree-phase powerfacor-correcion circui using hree isolaed single-phase sepic converers operaing in ccm, IEEE Power Elecronics Specialiss Conf. (PESC) Proc., pp , 000. [11] Y. Jang and M.M. Jovanović, The Taipei recifier a new hree-phase wo-swich zvs pfc dcm boos recifier, IEEE Transacions on Power Elecronics, vol. 8, o., pp , Feb [1] J. Sabaė, V. Vlaković, R. B. Ridley, F. C. Lee, and B. H. Cho, Design consideraions for high-volage high-power full-bridge zerovolage-swiched pwm converer, IEEE Applied Power Elecronics Conf. (APEC) Proc., pp ,