CoolSET -F3R80 ICE3AR4780CJZ. Off-Line SMPS Current Mode Controller with integrated 800V CoolMOS and Startup cell (brownout & CCM) in DIP-7

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1 Version 2.0, 19 Apr 2013 CoolSET -F3R80 Off-Line SMPS Curren Mode Conroller wih inegraed 800V CoolMOS and Sarup cell (brownou & CCM) in DIP-7 Power Managemen & Supply Never sop hinking.

2 Revision Hisory: Daashee Version 2.0 Previous Version: V 0.1 For quesions on echnology, delivery and prices please conac he Infineon Technologies Offices in Germany or he Infineon Technologies Companies and Represenaives worldwide: see our webpage a hp:// CoolMOS, CoolSET are rademarks of Infineon Technologies AG. Ediion Published by Infineon Technologies AG München, Germany Infineon Technologies AG 4/19/13. All Righs Reserved. Aenion please! The informaion given in his daa shee shall in no even be regarded as a guaranee of condiions or characerisics ( Beschaffenheisgaranie ). Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices please conac your neares Infineon Technologies Office ( Warnings Due o echnical requiremens componens may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies Office. Infineon Technologies Componens may only be used in life-suppor devices or sysems wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem, or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body, or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

3 Off-Line SMPS Curren Mode Conroller wih inegraed 800V CoolMOS and Sarup cell (brownou & CCM) in DIP-7 CoolSET -F3R80 Produc Highlighs 800V avalanche rugged CoolMOS wih sarup cell CCM and DCM operaion wih slope compensaion Acive Burs Mode o reach he lowes Sandby Power <100mW Acive burs mode wih selecable enry and exi burs mode level P-DIP-7-1 PG-DIP7 Frequency jier and sof driving for low EMI Brownou feaure Lach enable and fas AC rese Auo Resar proecion for over load, over emperaure and over volage Pb-free lead plaing; RoHS complian Feaures Descripion 800V avalanche rugged CoolMOS wih Sarup Cell The ICE3ARxx80CJZ is an enhanced version of Acive Burs Mode for lowes Sandby Power ICE3ARxx80JZ (CoolSET -F3R80). The PWM conroller Slope compensaion for CCM operaion is based on F3R80 wih new and enhanced feaures. The Selecable enry and exi burs mode level major new feaures include slope compensaion for CCM 100kHz inernally fixed swiching frequency wih operaion and fas AC rese afer lach enabled. The jiering feaure major enhanced feaures include fixed volage brownou Auo Resar Proecion for Over load, Open Loop, deec and volage deec for he burs selecion. In VCC Under volage & Over volage and Over paricular i is a device running a 100KHz, implemened emperaure wih brownou feaures, insalling 800V CoolMOS wih Exernal lach enable pin and fas AC rese sarup cell and packaged ino DIP-7. I arges for he low Over emperaure proecion wih 50 C hyseresis power SMPS wih increased MOSFET volage margin Buil-in 10ms Sof Sar requiremen such as Off-Line baery adapers, DVD R/ Buil-in 40ms blanking ime for shor duraion peak W, DVD Combi, Blue ray, se op box, auxiliary power power supply for PC and server, ec. In summary, his enhanced Propagaion delay compensaion for boh maximum ICE3ARxx80CJZ provides 800V MOSFET, lowes load and burs mode sandby power, CCM opeaion, selecable burs level, Brownou feaure brownou feaure, maximum power compensaed for boh BiCMOS echnology for low power consumpion and maximum and sandby load, low EMI wih frequency wide VCC volage range jiering and sof gae drive, buil-in and flexible Sof gae drive wih 50Ω urn on resisor proecions, ec. Therefore, ICE3ARxx80CJZ is a complee soluion for he low power SMPS applicaion. Typical Applicaion + Snubber Converer CBulk VAC DC Oupu - VCC CVCC Drain Power Managemen Sarup Cell RBO1 RBO2 BRL PWM Conroller Curren Mode Precise Low Tolerance Peak Curren Limiaion Conrol Uni Brownou mode Acive Burs Mode Auo Resar/ Lach Mode CoolMOS CoolSET -F3R80 (Brownou & CCM) CS FBB GND RSense Rsel Type Package Marking V DS F OSC 1) R DSon 230VAC ±15% 2) VAC 2) PG-DIP-7 3AR4780CJZ 800V 100kHz 4.7Ω 31W 20W 1) T=25 C 2) Calculaed maximum inpu power raing a T a =50 C, T i =125 C and wihou copper area as hea sink. Version Apr 2013

4 Table of Conens Page 1 Pin Configuraion and Funcionaliy Pin Configuraion wih PG-DIP Pin Funcionaliy Represenaive Blockdiagram Funcional Descripion Inroducion Power Managemen Improved Curren Mode PWM-OP PWM-Comparaor Slope Compensaion Sarup Phase PWM Secion Oscillaor PWM-Lach FF Gae Driver Curren Limiing Leading Edge Blanking Combined OPP curve considering Propagaion Delay and Slope Compensaion Conrol Uni Acive Burs Mode (paened) Selecable burs enry level Enering Acive Burs Mode Working in Acive Burs Mode Leaving Acive Burs Mode Proecion Modes Vcc OVP, OTP, exernal proecion enable and Vcc under volage Over load, open loop proecion Brownou Mode Fas AC rese Elecrical Characerisics Absolue Maximum Raings Operaing Range Characerisics Supply Secion Inernal Volage Reference PWM Secion Sof Sar ime Conrol Uni Curren Limiing Version Apr 2013

5 4.3.7 CoolMOS Secion CoolMOS Perfromance Characerisic Inpu Power Curve Ouline Dimension Marking Schemaic for recommended PCB layou Version Apr 2013

6 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion wih PG-DIP-7 Pin Symbol Funcion 1 BRL Brownou, fas AC Rese & Lach enable 2 FBB Feedback & Burs enry/exi conrol 3 CS Curren Sense/ 800V CoolMOS Source 4 n.c. no conneced 5 Drain 800V CoolMOS Drain 6 - (no pin) 7 VCC Conroller Supply Volage 8 GND Conroller Ground CoolSET -F3R80 Pin Configuraion and Funcionaliy 1.2 Pin Funcionaliy BRL (Brownou, fas AC Rese & Lach enable) The BRL pin combines he funcions of brownou, fas AC rese and he exernal lach enable. The brownou feaure is o sop he swiching pulse when he inpu volage is dropped o lower han 1V. The Fas AC rese feaure is o recover from lach feaure when he volage of BRL pin has a rising rae of <1.33V/ms from 0.4V o 1V. The exernal lach enable funcion is an exernal access o sop he gae swiching and force he IC o ener lach mode. I is riggered by pulling he pin volage o less han 0.4V. FBB (Feedback & Burs enry selec) The FBB pin combines he feedback funcion and he burs enry/exi conrol. The regulaion informaion is provided by he FBB pin o he inernal Proecion Uni and he inernal PWM-Comparaor o conrol he duy cycle. The FBB-signal is he only conrol signal in case of ligh load a he Acive Burs Mode. The burs enry selec provides an access o selec he enry/exi burs mode level. BRL FBB CS Package PG-DIP GND VCC CS (Curren Sense) The Curren Sense pin senses he volage developed on he shun resisor insered in he source of he inegraed CoolMOS. If CS reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore he curren informaion is provided for he PWM- Comparaor o realize he Curren Mode operaion. Drain (Drain of inegraed CoolMOS ) The Drain pin is he connecion o he Drain of he inegraed CoolMOS. n.c. 4 5 Drain VCC (Power Supply) The VCC pin is he power supply of he IC. The volage operaing range is beween 10.5V and 24.7V. Figure 1 Pin Configuraion PG-DIP-7 (op view) GND (Ground) The GND pin is he ground of he conroller. Version Apr 2013

7 Represenaive Blockdiagram 2 Represenaive Blockdiagram VAC RBO0 #1 CBR0 RBO1 Lach Enable Signal #1 BRL RBO2 #2 #1 TLE Cap2 FBB Rsel CBulk Snubber CVCC 1.25V 1V 25.5V Vcc C1a C1b C2 Blanking ime 270 s 120us Blanking S R FF2 Q Brownou mode Power Managemen Inernal Bias Volage Reference Power-Down Rese 5.0V Undervolage Lockou 17V 10.5V VCC Oscillaor 0.75 PWM Secion Drain CoolMOS Sarup Cell Blanking ime Lach Duy Cycle C3 max 0.4V 210us Mode RFB 5.0V 25k 2pF Burs deec and adjus Vcs_burs 0.4V 1V Vcc 8V VFB_burs C2a C2b C11 4.5V 4.0V VFB_burs 3.5V 3.2V Blanking ime 450 s G3 C4 C9 C5 C6a C6b Lach Rese Thermal Shudown Tj >130 C 20ms Blanking Time Conrol Uni Spike Blanking 30us ICE3ARxxx80CJZ / CoolSET -F3R80CCM & G2 40ms Blanking Time Sof Sar Block Auo Resar Mode Acive Burs Mode & G11 G7 Sof Sar C7 Curren Mode 0.6V PWM OP Sof sar comparaor & G3 C8 PWM comparaor x3.25 & G6 Clock Freq. jier C10 C12 Curren Limiing or G8 Maximum power limi G4 Vcsh Vcsh_burs Propagaion-Delay Compensaion-Burs FF1 S R Mc Q LEB 180/220ns LEB 180/220ns Gae Driver & G5 Slope compensaion S5 5.0V 1pF 1pF 10k D1 Rslope 10k D2 #1 :RBO0, RBO1 &RBO2 are used for brownou feaure (need o ie high BRL if no brownou feaure needed) #2 : TLE is used o enable he exernal Lach-Mode feaure GND CS RSense Converer DC Oupu VOUT Figure 2 Represenaive Blockdiagram Version Apr 2013

8 Funcional Descripion 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.2 Power Managemen Drain Sarup Cell VCC 3.1 Inroducion ICE3ARxx80CJZ brownou and CCM 800V version is an enhanced version of he CoolSET -F3R80. The major new and enhanced feaures include slope compensaion for CCM operaion, fas AC rese afer lach enabled, fixed volage brownou deec and volage deec for he burs selecion. I is paricular good for high volage margin low power SMPS applicaion such as auxiliary power supply for PC and server. The major characerisics are ha he IC is developed wih 800V CoolMOS wih sar up cell, having adjusable brownou feaure, running a 100KHz swiching frequency, CCM operaion and packed in DIP-7 package. The feaures include BiCMOS echnology o reduce power consumpion and increase he Vcc volage range, cycle by cycle curren mode conrol, buil-in 10ms sof sar o reduce he sress of swiching elemens during sar up, buil-in 40ms for shor period of peak power before enering proecion, acive burs mode for lowes sandby power, propagaion delay compensaion for close power limi beween high line and low line which also akes ino consideraion of slope compensaion, frequency jiering for low EMI performance, he buil-in auo-resar mode proecions for open loop, over load, Vcc OVP, Vcc under volage, and lach enable feaure ec. The oher feaures include narrowing he feedback volage swing o 0.3V (from 0.5V) during burs mode so ha he oupu volage ripple can be reduced by 40%, reducion of he fas volage fall ime of he MOSFET by increasing he sof urn-on ime and addiion of 50Ω urn-on resisor, faser sar up ime by opimizing he Vcc capacior o 10uF and over emperaure proecion wih 50 C hyseresis. The new feaures include slope compensaion for sable operaion in CCM mode when duy is larger han 0.5, fixed volage riggering for he bronwou feaure for easier design, volage levels selec for enry/exi burs level, fas AC rese fo rese he lach feaure, ec. In summary, he CoolSET ICE3ARxx80CJZ provides good volage margin of MOSFET, lowes sandby power, flexible burs level, CCM operaion, reduced oupu ripple during burs mode, accurae power limi for boh maximum power and burs power, low EMI wih frequency jiering and sof gae drive, buil-in and flexible proecions, ec. Therefore, CoolSET ICE3ARxx80CJZ is a complee soluion for he low power SMPS applicaion. Power Managemen Inernal Bias Lached Off Mode Rese; VVCC < 8V or AC fas rese is riggered Power-Down Rese Sof Sar block Undervolage Lockou 17V 10.5V Volage Reference Auo Resar Mode Acive Burs Mode Lached Off Mode CoolMOS 5.0V Figure 3 Power Managemen The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is conneced o he VCC pin. This VCC charge curren is conrolled o 1.0mA by he Sarup Cell. When he V VCC exceeds he on-hreshold V CCon =17V he bias circui are swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swich-on, a hyseresis sar up volage is implemened. The swich-off of he conroller can only ake place when V VCC falls below 10.5V afer normal operaion was enered. The maximum curren consumpion before he conroller is acivaed is abou 210μA. When V VCC falls below he off-hreshold V CCoff =10.5V, he bias circui is swiched off and he sof sar couner is rese. Thus i ensures ha a every sarup cycle he sof sar sars a zero. The inernal bias circui is swiched off if Lached Off Mode or Auo Resar Mode is enered. The curren consumpion is hen reduced o 420μA. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar Mode does no require re-cycling he AC line. In case Lached Off Mode is enered, VCC needs o be lowered below 8V or having AC fas rese riggered o rese he Version Apr 2013

9 Funcional Descripion Lached Off Mode. This is done usually by re-cycling he AC line. When Acive Burs Mode is enered, he inernal Bias is swiched off mos of he ime bu he Volage Reference is kep alive in order o reduce he curren consumpion below 620μA. 3.3 Improved Curren Mode FBB Sof-Sar Comparaor 0.6V C8 PWM OP x3.25 Improved Curren Mode Figure 4 Curren Mode Curren Mode means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FBB signal wih he amplified curren sense signal. Amplified Curren Signal FBB PWM-Lach R S CS Q Q Driver In case he amplified curren sense signal exceeds he FBB signal he on-ime on of he driver is finished by reseing he PWM-Lach (Figure 5). The primary curren is sensed by he exernal series resisor R Sense insered in he source of he inegraed CoolMOS. By means of Curren Mode regulaion, he secondary oupu volage is insensiive o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal R Sense allows an individual adjusmen of he maximum source curren of he inegraed CoolMOS. To improve he Curren Mode during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (see Figure 6). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver, T2 is opened so ha he volage ramp can sar. FBB Sof-Sar Comparaor Oscillaor V OSC T 2 R 1 PWM Comparaor C8 ime delay circui (156ns) 0.6V 10kΩ V 1 PWM-Lach Gae Driver X3.25 PWM OP 0.6V Driver Volage Ramp Figure 6 Improved Curren Mode Figure 5 on Pulse Widh Modulaion In case of ligh load he amplified curren ramp is oo small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FBB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he ime delay circui which is riggered by he invered V OSC signal, he Gae Driver is swiched-off unil i reaches approximaely 156ns delay ime (Figure Version Apr 2013

10 Funcional Descripion 7). I allows he duy cycle o be reduced coninuously ill 0% by decreasing V FBB below ha hreshold. V OSC max. Duy Cycle FBB 5V R FB Sof-Sar Comparaor PWM-Lach C8 Volage Ramp PWM Comparaor 0.6V FBB Gae Driver 156ns ime delay Opocoupler 0.6V PWM OP X3.25 CS Improved Curren Mode Figure 8 PWM Conrolling Figure PWM-OP Ligh Load Condiions The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o pin CS. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.25 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V 1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM- Comparaor C8 and he Sof-Sar-Comparaor (Figure 8) PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he inegraed CoolMOS wih he feedback signal V FBB (Figure 8). V FBB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pull-up resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he inegraed CoolMOS exceeds he signal V FBB he PWM-Comparaor swiches off he Gae Driver Slope Compensaion Due o he sub harmonic oscillaion of CCM operaion when duy cycle is larger han 50%, he slope compensaion is added. The slope Mc; 50mV/μs is added o he curren sense pin when gae is on. During burs mode operaion, he Mc slope is shu down and no slope added ino he curren sense signal. This can save he power consumpion a burs mode. FB Figure V C8 PWM comparaor x3.25 PWM OP Acive burs mode PWM lach Slope compensaion 5.0V Mc=50mV/us S5 LEB 180/220ns Slope compesnaion Gae Drive signal Rslope 10kΩ 1pF D2 CS Version Apr 2013

11 Funcional Descripion 3.4 Sarup Phase Sof Sar couner The funcion is realized by an inernal Sof Sar resisor, an curren sink and a couner. And he ampliude of he curren sink is conrolled by he couner (Figure 12). 5V R SofS Sof Sar finish SofS C7 Sof Sar Sof Sar Sof-Sar Comparaor & G7 Gae Driver Sof Sar Couner 32I 8I 4I SofS 2I I 0.6V PWM OP x3.25 Figure 10 Sof Sar In he Sarup Phase, he IC provides a Sof Sar period o conrol he primary curren by means of a duy cycle limiaion. The Sof Sar funcion is a buil-in funcion and i is conrolled by an inernal couner.. CS Figure 12 Sof Sar Circui Afer he IC is swiched on, he V SofS volage is conrolled such ha he volage is increased sepwisely (32 seps) wih he increase of he couns. The Sof Sar couner would send a signal o he curren sink conrol in every 300μs such ha he curren sink decrease gradually and he duy raio of he gae drive increases gradually. The Sof Sar will be finished in 10ms ( Sof-Sar ) afer he IC is swiched on. A he end of he Sof Sar period, he curren sink is swiched off. Wihin he sof sar period, he duy cycle is increasing from zero o maximum gradually (see Figure 13). V SofS Sof-Sar V SOFTS32 V SofS V SofS2 V SofS1 Gae Driver Figure 11 Sof Sar Phase When he V VCC exceeds he on-hreshold volage, he IC sars he Sof Sar mode (Figure 11). Figure 13 Gae drive signal under Sof-Sar Phase Version Apr 2013

12 Funcional Descripion In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during normal Auo Resar. 3.5 PWM Secion V SOFTS32 V SofS Sof-Sar Oscillaor Duy Cycle max 0.75 PWM Secion Clock V FB Frequency Jier 4.5V V OUT V OUT Sar-Up Sof Sar Block Sof Sar Comparaor PWM Comparaor 1 G8 FF1 S R Q Gae Driver & G9 Curren Limiing Figure 14 Sar Up Phase The Sar-Up ime Sar-Up before he converer oupu volage V OUT is seled, mus be shorer han he Sof- Sar Phase Sof-Sar (Figure 14). By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he inegraed CoolMOS, he clamp circui and he oupu recifier and i helps o preven sauraion of he ransformer during Sar-Up. Figure 15 PWM Secion Block CoolMOS Gae Oscillaor The oscillaor generaes a fixed frequency of 100KHz wih frequency jiering of ±4% (which is ±4KHz) a a jiering period of 4ms. A capacior, a curren source and curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Once he Sof Sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he Sof Sar block. Then he swiching frequency is varied in range of 100KHz ± 4KHz a period of 4ms PWM-Lach FF1 The oupu of he oscillaor block provides coninuous pulse o he PWM-Lach which urns on/off he inegraed CoolMOS. Afer he PWM-Lach is se, i is rese by he PWM comparaor, he Sof Sar comparaor or he Curren -Limi comparaor. When i is in rese mode, he oupu of he driver is shu down immediaely. Version Apr 2013

13 Funcional Descripion Gae Driver VCC 3.6 Curren Limiing PWM-Lach 1 PWM Lach FF1 Propagaion-Delay Compensaion Curren Limiing 50Ω Gae CoolMOS PWM-OP & G6 C10 C12 Vcsh LEB 220ns LEB 180ns S4 VCSh_burs Gae Driver Figure 16 Gae Driver The driver-sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich on slope when exceeding he inegraed CoolMOS hreshold. This is achieved by a slope conrol of he rising edge a he driver s oupu (Figure 17) and adding a 50Ω gae urn on resisor (Figure 16). Thus he leading swich on spike is minimized. (inernal) V Gae 4.6V yp. = 160ns Figure 17 Gae Rising Slope Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. During power up, when VCC is below he undervolage lockou hreshold V VCCoff, he oupu of he Gae Driver is se o low in order o disable power ransfer o he secondary side. Acive Burs Mode VFB_burs FBB C5 Propagaion-Delay Compensaion-Burs or G8 CS 10k D1 1pF Figure 18 Curren Limiing Block There is a cycle by cycle peak curren limiing operaion realized by he Curren-Limi comparaor C10. The source curren of he inegraed CoolMOS is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense which is fed ino he pin CS. If he volage V Sense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down of he inegraed CoolMOS wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o minimal. This compensaion applies o boh he peak load and burs mode. In order o preven he curren limi from disorions caused by leading edge spikes, a Leading Edge Blanking (LEB) is inegraed in he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he Gae G6 if Acive Burs Mode is enered. When i is acivaed, he curren limiing is reduced o V csh_burs. This volage level deermines he maximum power level in Acive Burs Mode. Version Apr 2013

14 Funcional Descripion Leading Edge Blanking V csh V Sense Figure 19 Leading Edge Blanking Whenever he inegraed CoolMOS is swiched on, a leading edge spike is generaed due o he primaryside capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o swich off uninenionally. In order o avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220ns for normal load and LEB = 180ns for burs mode Combined OPP curve considering Propagaion Delay and Slope Compensaion The ICE3ARxx80CJZ has combined he propagaion delay, CCM inheri reduced power effec and he slope compensaion effec for he overcurren conrol. I employs he dynamic hreshold volage V csh wih 2 seps slope compensaion o achieve he closed over curren for whole inpu volage range. In case of overcurren deecion, here is always propagaion delay o swich off he inegraed CoolMOS. An overshoo of he peak curren I peak is induced o he delay, which depends on he raio of di/ d of he peak curren (Figure 20). I Sense LEB = 220ns/180ns Signal2 Signal1 Propagaion Delay slope is depending on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swiching off of he inegraed CoolMOS is compensaed over emperaure wihin a wide inpu range. Curren Limiing is hen very accurae. For he inheri influence of he CCM operaion, he final Vcs can no be consan in whole line range as in DCM. This ICE3ARxx80CJZ has implemened wih 2 compensaion curves for he compensaion so ha he maximum power can be close. One of he curve is used when he ime range is larger han 4μs and he oher is for lower han 4μs. The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (Figure 21). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. V OSC V Sense V csh Figure 21 Dynamic Volage Threshold V csh A ypical measured Vsense vs dvsense/d is ploed in Figure 22 for reference max. Duy Cycle Signal1 off ime Propagaion Delay Signal2 I peak2 I peak1 I Overshoo I Limi I Overshoo1 V Sense (V) Figure 20 Curren Limiing The overshoo of Signal2 is larger han of Signal1 due o he seeper rising waveform. This change in he dv sense Figure 22 Overcurren Shudown Version Apr 2013

15 Funcional Descripion Similarly, he same concep of propagaion delay compensaion is also implemened in burs mode wih reduced level, V csh_burs (Figure 18). Wih his implemenaion, he enry and exi burs mode power can be close beween low line and high line inpu volage. 3.7 Conrol Uni The Conrol Uni conains he funcions for Acive Burs Mode, Auo Resar Mode and Lach Mode. The Acive Burs Mode, Lach Mode and he Auo Resar Mode boh have inernal blanking ime. Wih he blanking ime, he IC avoids enering ino hose wo modes accidenally. Those buffer ime is very useful for he applicaion which works in shor duraion of peak power occasionally Acive Burs Mode (paened) To increase he efficiency of he sysem a ligh load, he mos effecive way is o operae a burs mode. Saring from CoolSET F3, he IC has been employing he acive burs mode and i can achieve he lowes sandby power. ICE3ARxx80CJZ adops he same concep wih some more innovaive improvemens o he feaure. I includes he adjusable enry burs level, close power conrol beween high line and low line and he smaller oupu ripple during burs mode. Mos of he burs mode design in he marke will provide a fixed enry burs mode level which is a raio o he maximum power of he design. ICE3ARxx80CJZ provides a more flexible level which can be seleced exernally. Propagaion delay is he major conribuor for he power conrol variaion for DCM flyback converer. I is proved o be effecive in he maximum power conrol. ICE3ARxx80CJZ also apply he same concep in he burs mode. Therefore, he enry and exi burs mode power is also finely conrolled during burs mode. The feedback conrol swing during burs mode will affec he oupu ripple volage direcly. ICE3ARxx80CJZ reduces he swing o 0.3V (from 0.5V). Therefore, i would have around 40% improvemen for he oupu ripple. CS FBB R sel Vcsh_burs 4.0V 3.5V 3.2V C12 Burs deec and adjus VFB_burs C5 C13 C6a C6b G6 & FF1 20 ms Blanking Time Curren Limiing Inernal Bias Acive Burs Mode & G11 Conrol Uni Figure 23 Acive Burs Mode The Acive Burs Mode is locaed in he Conrol Uni. Figure 23 shows he relaed componens Selecable burs enry level The burs mode enry level can be seleced by changing he differen Resisor R sel a FBB pin. There are 3 levels o be seleced wih differen resisor which are argeed for 15%, 10% and 5% of he maximum inpu power. A he same ime, he exi burs level are argeed o 27%, 20% and 11% of he maximum power accordingly. The below able is he conrol logic for he enry and exi level wih he FBB volage. Level V FBB R sel 1 V FBB < V ref1 (1.8V) < 405kΩ 2 V ref1 (1.8V) <V FBB <V ref2 (4.0V) 685kΩ ~ 900kΩ 3 V FBB > V ref2 (4.0V) > 1530kΩ Enry level Exi level Level % of P in_max V FB_burs % of P in_max V csh_burs 1 5% 1.29V 11% 0.21V 2 10% 1.61V 20% 0.29V 3 15% 1.84V 27% 0.34V Version Apr 2013

16 Funcional Descripion During IC firs sarup, he Ref good signal is logic low when Vcc<8V. The low Ref good signal will rese he Burs Mode level Deecion lach. When he Burs Mode Level Deecion lach is low and IC is in OFF sae, he FBB resisor is isolaed from he FBB pin and a curren source I sel (3.5μΑ) is urned on insead. From Vcc=8V o Vcc on hreshold(17v), he FBB pin will sar o charge o a volage level associaed wih R sel resisor. When Vcc reaches Vcc on hreshold, he FBB volage is sensed. The burs mode hresholds are hen chosen according o he FBB volage level. The Burs Mode Level Deecion lach is hen se o high. Once he deecion lach is se high, any change of he FBB level will no change he hreshold level. When Vcc reaches Vcc on hreshold, a imer of 2μs is sared. Afer he 2μs ends, he I sel is urned off while he FBB resisor is conneced o FBB pin (Figure 24) Working in Acive Burs Mode Afer enering he Acive Burs Mode, he FBB volage rises as VOUT sars o decrease, which is due o he inacive PWM secion. The comparaor C6a moniors he FBB signal. If he volage level is larger han 3.5V, he inernal circui will be acivaed; he Inernal Bias circui resumes and sars o provide swiching pulse. In Acive Burs Mode he gae G6 is released and he curren limi is reduced o Vcsh_burs (Figure 2 and 23). In one hand, i can reduce he conducion loss and he oher hand, i can reduce he audible noise. If he load a VOUT is sill kep unchanged, he FBB signal will drop o 3.2V. A his level he C6b deacivaes he inernal circui again by swiching off he Inernal Bias. The gae G11 is acive again as he burs flag is se afer enering Acive Burs Mode. In Acive Burs Mode, he FBB volage is changing like a saw ooh beween 3.2V and 3.5V (Figure 25). UVLO Ref good Vcsh_burs V FB_burs S R Selecion Logic 2µs delay Burs mode deecion lach Compare logic Isel V dd S2 Rfb S1 Vref1 Vref2 FBB Rsel Leaving Acive Burs Mode The FBB volage will increase immediaely if here is a high load jump. This is observed by he comparaor C13 (Figure 23). Since he curren limi is reduced o 0.21V~0.34V during acive burs mode, i needs a cerain load jump o rise he FBB signal o exceed 4.0V. A ha ime he comparaor C5 reses he Acive Burs Mode conrol which in urn blocks he comparaor C12 by he gae G6. The maximum curren can hen be resumed o sabilize V OUT. Conrol uni Figure 24 Burs mode deec and adjus Enering Acive Burs Mode The FBB signal is kep monioring by he comparaor C5 (Figure 23). During normal operaion, he inernal blanking ime couner is rese o 0. When FBB signal falls below V FB_burs, i sars o coun. When he couner reaches 20ms and FBB signal is sill below V FB_burs, he sysem eners he Acive Burs Mode. This ime window prevens a sudden enering ino he Acive Burs Mode due o large load jumps. Afer enering Acive Burs Mode, a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC o abou 620μA. I needs he applicaion o enforce he VCC volage above he Undervolage Lockou level of 10.5V such ha he Sarup Cell will no be swiched on accidenally. Or oherwise he power loss will increase drasically. The minimum VCC level during Acive Burs Mode depends on he load condiion and he applicaion. The lowes VCC level is reached a no load condiion. Version Apr 2013

17 Funcional Descripion VFBB 4.0V 3.5V 3.2V VFB_burs Blanking Timer Enering Acive Burs Mode 20ms Blanking Time Leaving Acive Burs Mode Proecion Modes The IC provides Auo Resar mode as he major proecion feaure. Auo Resar mode can preven he SMPS from desrucive saes. There are 3 kinds of auo resar mode; normal auo resar mode, odd skip auo resar mode and non swich auo resar mode. Odd skip auo resar mode (Figure 26) is ha here is no deec of faul and no swiching pulse for he odd number resar cycle. A he even number of resar cycle he faul deec and sof sar swiching pulses are mainained. If he faul persiss, i would coninue he auo-resar mode. However, if he faul is removed, i can release o normal operaion only a he even number auo resar cycle. V CS VVCC Faul deeced No deec Sarup and deec No deec Vcsh Vcsh_burs Curren limi level during Acive Burs Mode 17V 10.5V VCS VVCC 10.5V IVCC 3.4mA 620uA Figure 26 Odd skip auo resar waveform Non swich auo resar mode is similar o odd skip auo resar mode excep he sar up swiching pulses are also suppressed a he even number of he resar cycle. The deecion of faul sill remains a he even number of he resar cycle. When he faul is removed, he IC will resume o normal operaion a he even number of he resar cycle (Figure 27). V OUT VVCC Faul deeced No deec Sarup and deec No deec 17V 10.5V VCS Figure 25 Signals in Acive Burs Mode No swiching Figure 27 non swich auo resar waveform The main purpose of he odd skip auo resar is o exend he resar ime such ha he power loss during auo resar proecion can be reduced. This feaure is paricularly good for smaller Vcc capacior where he resar ime is shorer. Version Apr 2013

18 Funcional Descripion The following able liss he possible sysem failures and he corresponding proecion modes. VCC Over volage Over load Open Loop VCC Undervolage Shor Opocoupler Over emperaure Exernal proecion enable Odd skip Auo Resar Mode Odd skip Auo Resar Mode Odd skip Auo Resar Mode Normal Auo Resar Mode Normal Auo Resar Mode Non swich Auo Resar Mode Lach Mode Vcc OVP, OTP, exernal proecion enable and Vcc under volage Lach Enable Signal BRL T LE VCC 0.4V 25.5V C9 C2 210µs blanking ime Thermal Shudown Tj >130 C Sop gae drive 120µs blanking ime Lach mode Spike Blanking 30µs Conrol Uni Auo Resar Mode Rese VVCC < 10.5V Auo Resar mode Volage Reference mode afer 210μs blanking ime. The gae drive is sopped and here is no swiching pulse before i is recovered. The Vcc undervolage and shor opo-coupler will go ino he normal auo resar mode inherenly. In case of VCC undervolage, he Vcc volage drops indefiniely. When i drops below he Vcc under volage lock ou OFF volage (10.5V), he IC will urn off he IC and he sarup cell will urn on again. Then he Vcc volage will be charged up o UVLO ON volage (17V) and he IC urns on again provided he sarup cell charge up curren is no drained by he faul. If he faul is no removed, he Vcc will coninue o drop unil i his UVLO OFF volage and he resar cycle repeas. Shor Opocoupler can lead o Vcc undervolage because once he opo-coupler (ransisor side) is shored, he feedback volage will drop o zero and here will be no swiching pulse. Then he Vcc volage will drop same as he Vcc undervolage Over load, open loop proecion FBB 4.5V 5.0V RFB C4 40ms Blanking Time Auo Resar Mode Figure 28 Vcc OVP, OTP, exernal proecion enable Conrol Uni Vcc OVP condiion is when V VCC volage is > 25.5V, he IC eners ino odd skip Auo Resar Mode (Figure 28). The over emperaure proecion OTP is sensed inside he conroller IC. The Thermal Shudown block keeps on monioring he juncion emperaure of he conroller. Afer deecing a juncion emperaure higher han 130 C, he IC will ener ino he non swich Auo Resar mode. The ICE3ARxx80CJZ has also implemened wih a 50 C hyseresis. Tha means he IC can only be recovered when he conroller juncion emperaure is dropped 50 C lower han he over emperaure rigger poin (Figure 28). The exernal lach enable feaure can provide a flexibiliy o a cusomer s self-defined proecion feaure. This funcion can be riggered by pulling down he V BRL volage o < 0.4V. Or i can simply rigger he base pin of an exernal ransisor, T LE a he BRL pin. When his funcion is enabled, i will ener ino lach Figure 29 Over load and open loop proecion In case of Overload or Open Loop, he V FBB volage exceeds 4.5V which will be observed by comparaor C4. Then he buil-in blanking ime couner sars o coun. When i reaches 40ms, he odd skip Auo Resar Mode is acivaed (Figure 29) Brownou Mode When he AC inpu volage is removed, he volage a he bulk capacior will fall. When i reaches a poin ha he sysem is greaer han he sysem allowed maximum power, he sysem may go ino over load proecion. However, his kind of proecion is no expeced for some of he applicaions such as auxiliary power for PC/server sysem because he oupu is in hiccup mode due o over load proecion (auo resar mode). The brownou mode is o eliminae his phenomenon. The ICE3ARxx80CJZ will sense he Version Apr 2013

19 Funcional Descripion inpu AC volage o he BRL pin by an AC hold up circui and 2 poenial divider resisors. In some applicaions, i needs he IC o coninue o work for cerain ime when AC volage is disconneced. Afer ha, he IC will sop working. If he brownou connecion is aping from he bulk capacior, he delay ime is oo shor. Therefore, i needs he brown ou deecion a he AC inpu (Figure 30). The C BR0 is charged up by AC line volage hrough R BO0, which is hen fed o BRL pin hrough a volage divider. When he AC volage drops, if he BRL pin volage is lower han 1V for 270μs, he ICE3ARxx80CJZ will go ino brownou mode. If, however, he AC line goes up again, he BRL volage will be larger han 1.25V and he ICE3ARxx80CJZ will leave brown ou mode and recover o normal operaion. The brownou mode is defaul ON during he sysem sars up. When he sysem is powered up, he bulk capacior and he Vcc capacior are charged up a he same ime. When he Vcc volage is charged o >8V, he brownou circui sars o operae (Figure 30). Since he UVLO is sill a low level as he Vcc volage does no reach he 17V UVLO ON volage. The NAND gae G20 will release a low signal o he flip flop FF2 and he negaive oupu of FF2 will release a high signal. Hence i is in brownou mode during he sysem sars up. C BR0 Vac R BO0 R BO1 1.25V C1a S Q Brownou mode VVCC 17V 10.5V VCS Figure 31 Brownou deeced Sarup and deec BBL volage Brownou mode waveform If he brownou feaure is no needed, i needs o ie he BRL pin o he Vcc pin hrough a curren limiing resisor, 5MΩ~10MΩ. The BRL pin canno be in floaing condiion Fas AC rese During normal operaion, he ICE3ARxx80CJZ can be lached by pulling down he BRL volage below 0.4V for 210μs. There are 2 condions o rese he lach feaure. The firs one is o pull down he Vcc volage o below 8V. However, he Vcc drop would ake quie a long ime if i is by normal AC power down. The second one is o have a slow rise ime of he BRL volage from 0.4V o 1V for a leas 450μs afer he BRL pin is pulled down. This iming can be achieved by he AC recycle. And i is also called he fas AC rese (Figure 32). BRL R BO2 1V C1b G21 Blanking Time 270µs UVLO G20 R FF2 Q Conrol Uni CBR0 Vac RBO0 RBO1 0.4V 0.4V C3 C2a Blanking ime 210us Blanking ime 450µs Lach Mode & G2 Figure 30 Brownou deecion circui Once he sysem eners he brownou mode, here will be no swiching pulse and he IC eners ino anoher ype auo-resar mode which is similar o he proecion auo-resar mode bu he IC will monior he BRL signal in each resar cycle (Figure 31). TLE Lach Enable Signal Figure 32 BRL RBO2 1V Vcc 8V C2b C11 Lach and fas AC rese G3 Lach Rese Conrol Uni Figure 33 shows differen lach and rese cases. Case a : no lached (solid line); he iming below 0.4V is 150μs and is less han 210μs. Version Apr 2013

20 Funcional Descripion Case b : lached (dashed line); he iming below 0.4V is 450μs which is larger han 210μs. No lach rese as he rise ime from 0.4V o 1V is 300μs which is less han he 450μs. Case c : lached and rese (doed line); he iming below 0.4V is 710μs which is larger han 210μs. Bu he rise ime from 0.4V o 1V is 560μs which is larger han he lach rese blanking ime of 450μs. VBRL 150µs 710µs 450µs 300µs 560µs Lached and rese (c) Lached (b) No lached (a) 1V 0.4V Figure 33 Lach and fas AC rese example Version Apr 2013

21 Elecrical Characerisics 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 8). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 7 (VCC) is discharged before assembling he applicaion circui. T a =25 C unless oherwise specified. Parameer Symbol Limi Values Uni Remarks min. max. Drain Source Volage V DS V Pulse drain curren, p limied by T jmax I D_Puls A Avalanche energy, repeiive AR limied by max. T j =150 C 1) E AR mj Avalanche curren, repeiive AR limied by I AR A max. T j =150 C VCC Supply Volage V VCC V FBB Volage V FBB V BRL Volage V BRL V CS Volage V CS V Juncion Temperaure T j C Conroller & CoolMOS Sorage Temperaure T S C Thermal Resisance R hja - 96 K/W Juncion -Ambien Soldering emperaure, wavesoldering only allowed a leads 1) T sold C 1.6mm (0.063in.) from case for 10s ESD Capabiliy (incl. Drain Pin) V ESD - 2 kv Human body model 2) 2) Repeiive avalanche causes addiional power losses ha can be calculaed as P AV =E AR *f According o EIA/JESD22-A114-B (discharging a 100pF capacior hrough a 1.5kΩ series resisor) Version Apr 2013

22 Elecrical Characerisics 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. VCC Supply Volage V VCC V VCCoff 24.7 V Max value limied due o Vcc OVP Juncion Temperaure of Conroller T jcon C Max value limied due o hermal shu down of conroller Juncion Temperaure of T jcoolmos C CoolMOS 4.3 Characerisics Supply Secion Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range T J from 25 C o 125 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 17 V is assumed. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar μa V VCC =16V VCC Charge Curren I VCCcharge ma V VCC = 0V I VCCcharge ma V VCC = 1V I VCCcharge ma V VCC =16V Leakage Curren of Sar Up Cell and CoolMOS I SarLeak μa V Drain = 650V a T j =100 C 1) Supply Curren wih Inacive Gae I VCCsup ma Supply Curren wih Acive Gae I VCCsup ma I FBB = 0A Supply Curren in Lached Off Mode wih Inacive Gae Supply Curren in Auo Resar Mode wih Inacive Gae Supply Curren in Acive Burs Mode wih Inacive Gae I VCClach μa I FBB = 0A I VCCresar μa I FBB = 0A I VCCburs μa V FBB = 2.5V I VCCburs μa V VCC = 11.5V, V FBB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hyseresis V VCCon V VCCoff V VCChys V V V 1) The parameer is no subjeced o producion es - verified by design/characerizaion Version Apr 2013

23 Elecrical Characerisics Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF V measured a pin FBB I FBB = 0A PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC khz f OSC khz T j = 25 C Frequency Jiering Range f jier - ±4.0 - khz T j = 25 C Frequency Jiering period T jier ms T j = 25 C Max. Duy Cycle D max Min. Duy Cycle D min V FBB < 0.3V PWM-OP Gain A V Volage Ramp Offse V Offse-Ramp V V FBB Operaing Range Min Level V FBB Operaing Range Max level V FBmin V V FBmax V dv sense / d = 0.134V/μs, limied by Comparaor C4 1) FBB Pull-Up Resisor R FB kω Slope Compensaion rae M C mv/μs CS=0V 1) The parameer is no subjeced o producion es - verified by design/characerizaion Sof Sar ime Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sof Sar ime SS ms Version Apr 2013

24 Elecrical Characerisics Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Brownou reference volage for V BO_L V comparaor C1a Brownou reference volage for V BO_E V comparaor C1b Leakage curren of BRL pin I leakage μα Blanking ime o ener brownou mode V BKC1b μs Fas AC rese volage for comparaor V C2a V C2a Fas AC rese volage for comparaor V C2b V C2b Blanking ime for comparaor C2a V BKC2a μs Charging curren o selec burs mode I sel μα Burs mode selecion reference V ref V volage V ref V Over Load Limi for Comparaor C4 V FBC V Acive Burs Mode 15% P in_max V FB_burs V V fbb >V ref2 Enry level for Comparaor C5 10% P in_max V FB_burs V V ref1 <V fbb <V ref2 5% P in_max V FB_burs V V fbb <V ref1 Acive Burs Mode High Level for V FBC6a V In Acive Burs Mode Comparaor C6a Acive Burs Mode Low Level for V FBC6b V Comparaor C6b Acive Burs Mode Level for V FBC V Comparaor C9 Overvolage Deecion Limi for V VCCOVP V Comparaor C2 Lach enable reference volage for V LE V Comparaor C3 Buil-in Blanking Time o ener Lach BK_lach μs Mode Thermal Shudown 1) T jsd C Conroller Hyseresis for hermal Shudown 1) T jsd_hys C Buil-in Blanking Time for Overload BK ms Proecion Buil-in Blanking Time for enering BK_burs ms Acive Burs Mode Spike Blanking Time for Vcc OVP Spike μs Version Apr 2013

25 Elecrical Characerisics 1) The parameer is no subjeced o producion es - verified by design/characerizaion. The hermal shudown emperaure refers o he juncion emperaure of he conroller. Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Peak Curren Limiaion V csh V dv sense / d = 0.41V/μs V csh V dv sense / d = 0.134V/μs Peak Curren 27% P in_max V csh_burs V V fbb >V ref2 Limiaion in Acive Burs Mode 20% P in_max V csh_burs V V ref1 <V fbb <V ref2 11% P in_max V csh_burs V V fbb <V ref1 Leading Edge Blanking Normal mode LEB_normal ns Burs mode LEB_burs ns CS Inpu Bias Curren I CSbias μa V CS =0V CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Drain Source Breakdown Volage V (BR)DSS Drain Source On-Resisance R DSon V V Ω Ω Ω T j = 25 C T j = 110 C 1) T j = 25 C T j =125 C 1) T j =150 C 1) a I D = 0.58A Effecive oupu capaciance, energy C o(er) pf V DS = 0V o 480V relaed Rise Time rise ) - ns Fall Time fall ) - ns 1) 2) The parameer is no subjeced o producion es - verified by design/characerizaion Measured in a Typical Flyback Converer Applicaion Version Apr 2013

26 5 CoolMOS Perfromance Characerisic CoolSET -F3R80 CoolMOS Perfromance Characerisic 10 Safe Operaing Area for I D = f ( V DS ) parameer : D = 0, T C = 25deg.C ID [A] p = 0.1ms p = 1ms p = 10ms p = 100ms DC V DS [V] Figure 34 Safe Operaing Area (SOA) curve for 120 SOA emperaure deraing coefficien curve ( package dissipaion ) for F3 & F2 CoolSET SOA emperaure deraing coefficien [%] Figure Ambien/Case emperaure Ta/Tc [deg.c] Ta : DIP, Tc : TO220 SOA emperaure deraing coefficien curve Version Apr 2013

27 CoolMOS Perfromance Characerisic Allowable Power Dissipaion for F3 CoolSET in DIP-7 package 1.4 Allowable Power Dissipaion, P o [W] Ambien emperaure, T A [deg.c] Figure 36 Power dissipaion; P o =f(t a ) Figure 37 Drain-source breakdown volage; V BR(DSS) =f(t j ), I D =0.25mA Version Apr 2013

28 Inpu Power Curve 6 Inpu Power Curve Two inpu power curves giving he ypical inpu power versus ambien emperaure are showed below; Vin=85Vac~265Vac (Figure 38) and Vin=230Vac+/-15% (Figure 39). The curves are derived based on a ypical disconinuous mode flyback model which considers eiher 60% maximum duy raio or 150V maximum secondary o primary refleced volage (higher prioriy). The calculaion is based on no copper area as heasink for he device. The inpu power already includes he power loss a inpu common mode choke, bridge recifier and he CoolMOS.The device sauraion curren (I T j =125 C) is also considered. To esimae he oupu power of he device, i is simply muliplying he inpu power a a paricular operaing ambien emperaure wih he esimaed efficiency for he applicaion. For example, a wide range inpu volage (Figure 38), operaing emperaure is 50 C, esimaed efficiency is 85%, hen he esimaed oupu power is 17W (20W * 85%). Figure 38 Inpu power curve Vin=85~265Vac; P in =f(t a ) Figure 39 Inpu power curve Vin=230Vac+/-15%; P in =f(t a ) Version Apr 2013

29 Ouline Dimension 7 Ouline Dimension PG-DIP-7 (Plasic Dual In-Line Ouline) Figure 40 PG-DIP-7 (Pb-free lead plaing Plasic Dual-in-Line Ouline) Version Apr 2013

30 Marking 8 Marking Marking Figure 41 Marking for Version Apr 2013

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