Infineon LITIX TM Basic TLD1125EL. Data Sheet. Automotive. 1 Channel High Side Current Source. Rev. 1.1,

Transcription

1 Infineon LITIX TM Basic TLD1125EL 1 Channel High Side Curren Source Daa Shee Rev. 1.1, Auomoive

2 1 Overview Block Diagram Pin Configuraion Pin Assignmen Pin Definiions and Funcions General Produc Characerisics Absolue Maximum Raings Funcional Range Thermal Resisance EN Pin EN Funcion Inernal Supply Pin EN Unused EN - Pull Up o VS EN - Direc Connecion o VS PWMI Pin PWM Dimming Inernal PWM Uni Elecrical Characerisics Inernal Supply / EN / PWMI Pin IN_SET Pin Oupu Curren Adjusmen via RSET Smar Inpu Pin ST Pin Diagnosis Selecor Diagnosis Oupu Disable Inpu D Pin Load Diagnosis Open Load Shor Circui o GND deecion Elecrical Characerisics IN_SET Pin and Load Diagnosis Power Sage Proecion Over Load Behavior Reverse Baery Proecion Elecrical Characerisics Power Sage Applicaion Informaion Furher Applicaion Informaion Package Oulines Revision Hisory Daa Shee 2 Rev. 1.1,

3 1 Channel High Side Curren Source LITIX TM Basic TLD1125EL 1 Overview Feaures 1 Channel device wih inegraed oupu sage (curren source), opimized o drive LEDs Oupu curren up o 360mA Low curren consumpion in sleep mode PWM-operaion suppored via VS- and EN-pin Inegraed PWM dimming engine o provide wo LED brighness levels wihou exernal logic (e.g. µc) Oupu curren adjusable via exernal low power resisor and possibiliy o connec PTC resisor for LED proecion during over emperaure condiions Reverse polariy proecion Overload proecion Undervolage deecion Open load and shor circui o GND diagnosis Wide emperaure range: -40 C < T j < 150 C PG-SSOP14 package wih exposed heaslug Green Produc (RoHS complian) AEC Qualified PG-SSOP14 Descripion The LITIX TM Basic TLD1125EL is a one channel high side driver IC wih inegraed oupu sage. I is designed o conrol LEDs wih a curren up o 360 ma. In ypical auomoive applicaions he device is capable o drive i.e. 3 red LEDs wih a curren up o 180 ma, which is limied by hermal cooling aspecs. The oupu curren is conrolled pracically independen of load and supply volage changes. Table 1 Produc Summary Operaing volage V S(nom) 5.5 V 40 V Maximum volage 40 V V S(max) V OUT(max) Nominal oupu (load) curren I OUT(nom) 180 ma when using a supply volage range of 8V - 18V (e.g. Auomoive car baery). Currens up o I OUT(max) possible in applicaions wih low hermal resisance R hja Maximum oupu (load) curren I OUT(max) 360 ma; depending on hermal resisance R hja Type Package Marking TLD1125EL PG-SSOP14 TLD1125EL Daa Shee 3 Rev. 1.1,

4 Overview Table 1 Produc Summary Oupu curren accuracy a R SET = 12 kω k LT 2250 ± 7% Curren consumpion in sleep mode I S(sleep,yp) 0.1 µa Proecive funcions - ESD proecion - Under volage lock ou - Over Load proecion - Over Temperaure proecion - Reverse Polariy proecion Diagnosic funcions - OL deecion - SC o Vs (indicaed by OL diagnosis) - SC o GND deecion Applicaions Designed for exerior LED lighing applicaions such as ail/brake ligh, urn indicaor, posiion ligh, side marker,... The device is also well suied for inerior LED lighing applicaions such as ambien lighing, inerior illuminaion and dash board lighing. Daa Shee 4 Rev. 1.1,

5 Block Diagram 2 Block Diagram EN PWMI D VS Inernal supply Thermal proecion Oupu conrol OUT IN_SET TLD1125EL Curren adjus Saus ST GND Figure 1 Basic Block Diagram Daa Shee 5 Rev. 1.1,

6 Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen VS 1 14 NC VS 2 TLD1125EL 13 NC EN 3 12 OUT NC 4 EP 11 NC PWMI 5 10 ST IN_SET 6 9 GND D 7 8 NC Figure 2 Pin Configuraion Daa Shee 6 Rev. 1.1,

7 Pin Configuraion 3.2 Pin Definiions and Funcions Pin Symbol Inpu/ Funcion Oupu 1, 2 VS Supply Volage; baery supply, connec a decoupling capacior (100 nf - 1 µf) o GND 3 EN I Enable pin 4 NC Pin no conneced 5 PWMI I/O PWM Inpu 6 IN_SET I/O Inpu / SET pin; Connec a low power resisor o adjus he oupu curren 7 D I/O Delay for open load deecion 8 NC Pin no conneced 9 GND Ground 10 ST I/O Saus pin 11 NC Pin no conneced 12 OUT O Oupu 13 NC Pin no conneced 14 NC Pin no conneced Exposed Pad GND Exposed Pad; connec o GND in applicaion Connec all GND-pins ogeher. Daa Shee 7 Rev. 1.1,

8 General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings Absolue Maximum Raings T j = -40 C o +150 C; all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. Volages Supply volage V S V Inpu volage EN V EN V Inpu volage EN relaed o V S V EN(VS) V S - 40 V S + 16 V Inpu volage EN relaed o V OUT V EN V V EN - V OUT V OUT Oupu volage V OUT V Power sage volage V PS V V PS = V S - V OUT Inpu volage PWMI V PWMI V IN_SET volage V IN_SET V D volage V D V Saus volage V ST V Currens IN_SET curren I IN_SET D curren I D ma Oupu curren I OUT 390 ma Temperaures Juncion emperaure T j C Sorage emperaure T sg C ESD Suscepibiliy ESD resisiviy o GND V ESD -2 2 kv Human Body Model (100 pf via 1.5 kω) 2) ESD resisiviy all pins o GND V ESD V CDM 3) ESD resisiviy corner pins o GND V ESD V CDM 3) No subjec o producion es, specified by design 2) ESD suscepibiliy, Human Body Model HBM according o ANSI/ESDA/JEDEC JS ) ESD suscepibiliy, Charged Device Model CDM according o JESD22-C101E 2 8 ma Diagnosis oupu Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. Daa Shee 8 Rev. 1.1,

9 General Produc Characerisics 4.2 Funcional Range Pos. Parameer Symbol Limi Values Uni Condiions Min. Max Supply volage range for V S(nom) V normal operaion Power on rese hreshold V S(POR) 5 V V EN = V S R SET =12kΩ I OUT = 80% I OUT(nom) V OUT =2.5V Juncion emperaure T j C Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. 4.3 Thermal Resisance Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Juncion o Case R hjc 8 10 K/W 2) Juncion o Ambien 1s0p board R hja Juncion o Ambien 2s2p board R hja2 No subjec o producion es, specified by design. Based on simulaion resuls. 2) Specified R hjc value is simulaed a naural convecion on a cold plae seup (all pins and he exposed Pad are fixed o ambien emperaure). T a = 85 C, Toal power dissipaion 1.5 W. 3) The R hja values are according o Jedec JESD51-3 a naural convecion on 1s0p FR4 board. The produc (chip + package) was simulaed on a 76.2 x x 1.5 mm 3 board wih 70µm Cu, 300 mm 2 cooling area. Toal power dissipaion 1.5 W disribued saically and homogenously over power sage. 4) The R hja values are according o Jedec JESD51-5,-7 a naural convecion on 2s2p FR4 board. The produc (chip + package) was simulaed on a 76.2 x x 1.5 mm 3 board wih 2 inner copper layers (ouside 2 x 70 µm Cu, inner 2 x 35µm Cu). Where applicable, a hermal via array under he exposed pad conaced he firs inner copper layer. Toal power dissipaion 1.5 W disribued saically and homogenously over power sage K/W K/W 3) T a =85 C T a = 135 C 4) T a =85 C T a = 135 C Daa Shee 9 Rev. 1.1,

10 EN Pin 5 EN Pin The EN pin is a dual funcion pin: Inernal Supply EN Oupu Conrol V EN Figure 3 Block Diagram EN pin Noe: The curren consumpion a he EN-pin I EN needs o be added o he oal device curren consumpion. The oal curren consumpion is he sum of he currens a he VS-pin I S and he EN-pin I EN. 5.1 EN Funcion If he volage a he pin EN is below a hreshold of V EN(off) he LITIX TM Basic IC will ener Sleep mode. In his sae all inernal funcions are swiched off, he curren consumpion is reduced o I S(sleep). A volage above V EN(on) a his pin enables he device afer he Power on rese ime POR. V S V EN I OUT POR 100% 80% Figure 4 Power on rese Daa Shee 10 Rev. 1.1,

11 EN Pin 5.2 Inernal Supply Pin The EN pin can be used o supply he inernal logic. There are wo ypical applicaion condiions, where his feaure can be used: In DC/DC conrol Buck configuraions, where he volage V s can be below 5.5V. 2) In configuraions, where a PWM signal is applied a he Vba pin of a ligh module. The buffer capacior C BUF is used o supply he LITIX TM Basic IC during Vba low (V s low) periods. This feaure can be used o minimize he urn-on ime o he values specified in Pos Oherwise, he power-on rese delay ime POR (Pos ) has o be considered. The capacior can be calculaed using he following formula: C BUF = I EN( LS) LOW( max) V S V D1 V SPOR ( ) ( See also a ypical applicaion drawing in Chaper 12. V BATT VS D 1 CBUF EN Inernal supply Thermal proecion Oupu conrol OUT IN_SET Curren adjus RSET Basic LITIX LED TM Basic Driver GND GND Figure 5 Exernal circui when applying a fas PWM signal on V BATT Daa Shee 11 Rev. 1.1,

12 EN Pin V EN V BATT IOUT ON(VS) 100% 80% Swich off behavior depends on V BATT and load characerisics 20% Figure 6 Typical waveforms when applying a fas PWM signal on V BATT The parameer ON(VS) is defined a Pos The parameer OFF(VS) depends on he load and supply volage V BATT characerisics. 5.3 EN Unused In case of an unused EN pin, here are wo differen ways o connec i: EN - Pull Up o VS The EN pin can be conneced wih a pull up resisor (e.g. 10 kω) o V s poenial. In his configuraion he LITIX TM Basic IC is always enabled EN - Direc Connecion o VS The EN pin can be conneced direcly o he VS pin (IC always enabled). This configuraion has he advanage (compared o he configuraion described in Chaper 5.3. ha no addiional exernal componen is required. Daa Shee 12 Rev. 1.1,

13 PWMI Pin 6 PWMI Pin The PWMI pin is designed as a dual funcion pin. PWMI I PWMI(L) Oupu Conrol V PWMI Figure 7 Block Diagram PWMI pin The pin can be used for PWM-dimming via a push-pull sage of a micro conroller, which is connecing he PWMIpin o a low or high poenial. Noe: The micro conroller s push-pull sage has o able o sink currens according o Pos o acivae he device. Furhermore, he device offers also an inernal PWM uni by connecing an exernal-rc nework according o Figure PWM Dimming A PWM signal can be applied a he PWMI pin for LED brighness regulaion. The dimming frequency can be adjused in a very wide range (e.g. 400 Hz). The PWMI pin is low acive. Turn on/off hresholds V PWMI(L) and V PWMI(H) are specified in parameers Pos and Pos V PWMI IOUT ON(PWMI ) OFF(PWMI ) 100% 80% 20% Figure 8 Turn on and Turn off ime for PWMI pin usage Daa Shee 13 Rev. 1.1,

14 PWMI Pin 6.2 Inernal PWM Uni Connecing a resisor and a capacior in parallel on he PWMI pin enables he inernal pulse widh modulaion uni. The following figure shows he charging and discharging defined by he RC-nework according o Figure 10 and he inernal PWM uni. V PWMI Oupus OFF V PWMI(H) Inernal PWM V PWMI(L) Oupus ON OUT- ON OUT - OFF OUT- ON OUT - OFF OUT- ON OUT - OFF OUT- ON OUT - OFF Figure 9 PWMI operaing volages The PWM Duy cycle (DC) and he PWM frequency can be adjused using he formulas below. Please use only ypical values of V PWMI(L), V PWMI(H) and I PWMI(on) for he calculaion of PWMI(on) and PWMI(off) (as described in Pos o Pos ). PWMI( on) = R PWMI off PWMI C PWMI LN V PWMI( H) I PWMI( on) R PWMI ( ) R PWMI CPWMI LN V PWMI ( H ) = 1 f PWMI = PWMI( on) PWMI( off) V PWMI( L) I PWMI( on) R PWMI V PWMI( L) (2) (3) (4) DC = PWMI( on) f PWMI (5) Ou of his equaions he required C PWMI and R PWMI can be calculaed: I PWMI on V ( ) PWMI L ( ) PWMI( off) V PWMI( H) PWMI( on) PWMI( off) 1 C PWMI = LN V PWMI ( L ) V PWMI( H) V V PWMI ( L ) PWMI( L) V PWMI( H) PWMI( on) PWMI( off) V PWMI( H) (6) R PWMI PWMI( off) = C PWMI LN V PWMI ( H ) V PWMI( L) (7) Daa Shee 14 Rev. 1.1,

15 PWMI Pin See Figure 10 for a ypical exernal circuiry. Noe: In case of juncion emperaures above T j(crt) (Pos ) he device provides a emperaure dependen curren reducion feaure as descirbed in Chaper In case of oupu curren reducion I IN_SET is reduced as well, which leads o increased urn on-imes PWMI(on), because he C PWMI is charged slower. The urn off-ime PWMI(off) remains he same. V BATT 10kΩ VS EN Inernal supply Thermal proecion Oupu conrol PWMI OUT D C D IN_SET Curren adjus R PWMI C PWMI R SET Basic LED Driver GND GND Figure 10 Typical circui using inernal PWM uni 6.3 Elecrical Characerisics Inernal Supply / EN / PWMI Pin Elecrical Characerisics Inernal Supply / EN / PWMI pin Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Curren consumpion, sleep mode I S(sleep) µa V EN = 0.5 V T j < 85 C V S = 18 V V OUT = 3.6 V Curren consumpion, acive mode I S(on) ma 2) V PWMI = 0.5 V I IN_SET = 0µA T j < 105 C V S = 18 V V OUT = 3.6V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin Daa Shee 15 Rev. 1.1,

16 PWMI Pin Elecrical Characerisics Inernal Supply / EN / PWMI pin (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Curren consumpion, device disabled via ST Curren consumpion, device disabled via IN_SET Curren consumpion, device disabled via PWMI Curren consumpion, acive mode in faul deecion condiion wih STpin unconneced Curren consumpion, acive mode in faul deecion condiion wih STpin conneced o GND I S(dis,ST) I S(dis,IN_SET) I S(dis,PWMI) I S(faul,STu) I S(faul,STG) Power-on rese delay ime 3) POR 25 µs ma ma ma ma ma 2) V S = 18 V T j < 105 C V ST = 5 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C V IN_SET = 5 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C V PWMI = 3.4 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C R SET = 12 kω V PWMI = 0.5 V V OUT = 18 V or 0 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C R SET = 12 kω V PWMI = 0.5 V V OUT = 18 V or 0 V V ST = 0 V V EN =5.5V V EN =18V R EN = 10 kω beween VS and EN-pin V S = V EN = V V OUT(nom) = 3.6 ± 0.3V I OUT =80%I OUT(nom) Daa Shee 16 Rev. 1.1,

17 PWMI Pin Elecrical Characerisics Inernal Supply / EN / PWMI pin (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Required supply volage for oupu acivaion Required supply volage for curren conrol Min. Typ. Max. V S(on) 4 V V EN = 5.5 V V OUT = 3 V I OUT =50% I OUT(nom) V S(CC) 5.2 V V EN = 5.5 V V OUT = 3.6 V I OUT 90% I OUT(nom) EN urn on hreshold V EN(on) 2.5 V EN urn off hreshold V EN(off) 0.8 V EN inpu curren during low supply volage EN high inpu curren I EN(H) PWMI (acive low) Swiching low hreshold (oupu on) PWMI(acive low) Swiching high hreshold (oupu off) PWMI Swiching hreshold difference V PWMI(H) - V PWMI(L) PWMI (acive low) Low inpu curren wih acive channels (volage <V PWMI(L) ) PWMI(acive low) High inpu curren I EN(LS) 1.8 ma V S = 4.5 V T j < 105 C V EN = 5.5 V V PWMI(L) V ma T j < 105 C V S = 13.5 V, V EN = 5.5 V V S = 18 V, V EN = 5.5 V V S = V EN = 18 V V S = 18 V, R EN = 10 kω beween VS and EN-pin 4) V S = V V PWMI(H) V 4)5) V S = V ΔV PWMI V I PWMI(on) I IN_SET *3.1 I IN_SET *4 I IN_SET *4.9 µa 4)5) V S = V T j = C I IN_SET = 100 µa V PWMI = 1.7 V V EN = 5.5 V V S = V I PWMI(off) -5 5 µa V PWMI = 5 V V EN = 5.5 V V S = V No subjec o producion es, specified by design 2) The oal device curren consumpion is he sum of he currens I S and I EN(H), please refer o Pos ) See also Figure 4 4) Parameer valid if an exernal PWM signal is applied 5) If TTL level compaibiliy is required, use µc open drain oupu wih pull up resisor Daa Shee 17 Rev. 1.1,

18 IN_SET Pin 7 IN_SET Pin The IN_SET pin is a muliple funcion pin for oupu curren definiion, inpu and diagnosics: Logic IN_SET high impedance I IN_SET V IN_SET V IN_SET(OL/SC) GND Figure 11 Block Diagram IN_SET pin 7.1 Oupu Curren Adjusmen via RSET The curren adjusmen can be done by placing a low power resisor (R SET ) a he IN_SET pin o ground. The dimensioning of he resisor can be done using he formula below: R SET k = I OUT (8) The gain facor k (R SET * oupu curren) is specified in Pos and Pos The curren hrough he R SET is defined by he resisor iself and he reference volage V IN_SET(ref), which is applied o he IN_SET during supplied device. 7.2 Smar Inpu Pin The IN_SET pin can be conneced via R SET o he open-drain oupu of a µc or o an exernal NMOS ransisor as described in Figure 12. This signal can be used o urn off he oupu sage of he IC. A minimum IN_SET curren of I IN_SET(ac) is required o urn on he oupu sage. This feaure is implemened o preven glimming of LEDs caused by leakage currens on he IN_SET pin, see Figure 15 for deails. In addiion, he IN_SET pin offers he diagnosic feedback informaion, if he saus pin is conneced o GND. Anoher diagnosic possibiliy is shown in Figure 13, where he diagnosis informaion is provided via he ST pin (refer o Chaper 8 and Chaper 10) o a micro conroller. In case of a faul even wih he ST pin conneced o GND he IN_SET volage is increased o V IN_SET(OL/SC) Pos Therefore, he device has wo volage domains a he IN_SET-pin, which is shown in Figure 16. Daa Shee 18 Rev. 1.1,

19 IN_SET Pin Microconroller (e.g. XC866) OUT R SET /2 R SET /2 IN_SET Curren adjus Saus Basic LED Driver ST GND V DDP = 5 V IN Figure 12 Schemaics IN_SET inerface o µc, diagnosis via IN_SET pin Microconroller (e.g. XC866) OUT R SET IN_SET Curren adjus Saus Basic LED Driver ST GND V DDP = 5 V IN opional Figure 13 Schemaics IN_SET inerface o µc, diagnosis via ST pin The resuling swiching imes are shown in Figure 14: I IN_SET IOUT ON(IN_SET ) OFF(IN_SET) 100% 80% 20% Figure 14 Swiching imes via IN_SET Daa Shee 19 Rev. 1.1,

20 IN_SET Pin I OUT [ma] k = I OUTx * V IN_SET(ref) / I IN_SETx I OUTx I IN_SET(ACT) I IN_SETx I IN_SET [µa] Figure 15 I OUT versus I INSET V IN_SET V IN _SET(OL/SC)max Diagnosic volage range V IN_SET(OL/SC)min V IN _SET (ref ) m ax Normal operaion and high emperaure curren reducion range Figure 16 Volage domains for IN_SET pin, if ST pin is conneced o GND Daa Shee 20 Rev. 1.1,

21 ST Pin 8 ST Pin The ST pin is a muliple funcion pin. I ST(OL/SC) ST No faul Faul V ST(OL/SC) Oupu Conrol No faul Faul V ST I ST(PD) Figure 17 Block Diagram ST pin 8.1 Diagnosis Selecor If he saus pin is unconneced or conneced o GND via a high ohmic resisor (V ST o be below V ST(L) ), he ST pin acs as diagnosis oupu pin. In normal operaion (device is acivaed) he ST pin is pulled o GND via he inernal pull down curren I ST(PD). In case of an open load or shor circui o GND condiion he ST pin is swiched o V ST(OL/SC) afer he filer ime D (see Equaion (1). If he device is operaed in PWM operaion via he VS and/or EN pins he ST pin should be conneced o GND via a high ohmic resisor (e.g. 470kΩ) o ensure proper device behavior during fas rising VS and/or EN slopes. If he ST pin is shored o GND he diagnosic feedback is performed via he IN_SET-pin, which is shown in Chaper 7.2 and Chaper Diagnosis Oupu If he saus pin is unconneced or conneced o GND via a high ohmic resisor (V ST o be below V ST(L) ), i acs as a diagnosic oupu. In case of a faul condiion he ST pin rises is volage o V ST(OL/SC) (Pos ). Deails are shown in Chaper Disable Inpu If an exernal volage higher han V ST(H) (Pos ) is applied o he ST pin, he device is swiched off. This funcion is used for applicaions, where muliple drivers should be used for one ligh funcion. I is possible o combine he drivers faul diagnosis via he ST pins. If a single LED chain fails, he enire ligh funcion is swiched off. In his scenario e.g. he diagnosic circui on he body conrol module can easily disinguish beween he wo cases (normal load or load faul), because nearly no curren is flowing ino he LED module during he faul scenario - he drivers consume a curren of I S(faul,STu) (Pos ) or I S(dis,ST) (Pos ). As soon as one LED chain fails, he ST-pin of his device is swiched o V ST(OL/SC). The oher devices used for he same ligh funcion can be conneced ogeher via he ST pins. This leads o a swich off of all devices conneced ogeher. Applicaion examples are shown in Chaper 12. Daa Shee 21 Rev. 1.1,

22 ST Pin V ST IOUT ON(ST) OFF(ST) 100% 80% 20% Figure 18 Swiching imes via ST Pin Daa Shee 22 Rev. 1.1,

23 D Pin 9 D Pin The D pin is designed as a single funcion pin. D I D Oupu Conrol V D Figure 19 Block Diagram DIS pin The D pin can be used o exend he open load deecion filer ime OL by adding a small signal capacior o he D pin as shown in Figure 26. The filer ime D, which is defined by he charging curren I D (Pos ). The ime is adjusable according o he following equaion: C D V Dh ( ) yp = I D (9) Daa Shee 23 Rev. 1.1,

24 Load Diagnosis 10 Load Diagnosis 10.1 Open Load An open load diagnosis feaure is inegraed in he TLD1125EL driver IC. If here is an open load on he oupu, he oupu is urned off. The poenial on he IN_SET pin rises up o V IN_SET(OL/SC). This high volage can be used as inpu signal for an µc as shown in Figure 13. The open load saus is no lached, as soon as he open load condiion is no longer presen, he oupu sage will be urned on again. An open load condiion is deeced, if he volage drop over he oupu sage V PS is below he hreshold according Pos The oupu is deacivaed afer a filer ime D, which is defined by he charging curren I D Pos The ime is adjusable by he capacior conneced o he D pin according he following equaion: C D V Dh ( ), = D yp I D (10) V IN_SET V IN_SET(OL) V IN_SET(ref ) V D VD( h) V OUT D IN_SET(rese) V S VS VPS(OL) V F open load occurs open load disappears Figure 20 IN_SET behavior during open load condiion wih ST pin conneced o GND Daa Shee 24 Rev. 1.1,

25 Load Diagnosis V IN_SET V IN_SET(ref ) V ST V ST(OL) V D V D( h) V OUT D IN_SET(rese) VS V S V PS(OL) VF open load occurs open load disappears Figure 21 IN_SET and ST behavior during open load condiion (ST unconneced) To provide a Limp Home funcionaliy (reacivaion in case of open load insead of complee deacivaion) he filer ime D can be used. If a PWM signal wih a frequency higher han 1/ D is applied o he V S line and EN signal, he OL deecion feaure will no be acivaed. The implemenaion of he D-pin is shown in he following figure: D I D Oupu Conrol V D Figure 22 Block Diagram D pin Daa Shee 25 Rev. 1.1,

26 Load Diagnosis 10.2 Shor Circui o GND deecion The TLD1125EL has an inegraed SC o GND deecion. If he oupu sage is urned on and he volage a he oupu falls below V OUT(SC) he poenial on he IN_SET pin is increased up o V IN_SET(OL/SC) afer SC if he ST pin is conneced o GND. If he ST is open or conneced o GND via a high ohmic resisor he faul is indicaed on he ST pin according o Chaper 8 afer D. More deails are shown in Figure 24. This condiion is no lached. For deecing a normal condiion afer a shor circui deecion an oupu curren according o I OUT(SC) is driven by he channel. The filer ime D is defined by he charging curren I D Pos The ime is adjusable by he capacior conneced o he D pin according he following equaion: C D V Dh ( ), = D yp I D (1 V IN_SET V IN _SET(OL) V IN _SET( ref ) V D VD (h) V OUT D IN_SET(rese) V S V F VOUT ( SC) shor circui occurs shor circui disappears Figure 23 IN_SET behavior during shor circui o GND condiion wih ST conneced o GND Daa Shee 26 Rev. 1.1,

27 Load Diagnosis V IN_SET V IN _SET( ref ) V ST V ST(OL) V D VD (h) D IN_SET(rese) V OUT V S VF VOUT ( SC) shor circui occurs shor circui disappears Figure 24 IN_SET and ST behavior during shor circui o GND condiion (ST unconneced) 10.3 Elecrical Characerisics IN_SET Pin and Load Diagnosis Elecrical Characerisics IN_SET pin and Load Diagnosis Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET = 12 kω, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max IN_SET reference volage IN_SET open load/shor circui volage V IN_SET(ref) V V IN_SET(OL/SC) V V OUT =3.6V T j = C V S > 8 V T j = C V S = V OUT (OL) or V OUTx = 0 V (SC) Daa Shee 27 Rev. 1.1,

28 Load Diagnosis Elecrical Characerisics IN_SET pin and Load Diagnosis (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET = 12 kω, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. I IN_SET(OL/SC) ma IN_SET open load/shor circui curren ST device urn on hreshold (acive low) in case of volage applied from exernal (ST-pin acing as inpu) ST device urn off hreshold (acive low) in case of volage applied from exernal (ST-pin acing as inpu) V ST(L) 0.8 V V ST(H) 2.5 V ST pull down curren I ST(PD) 15 µa V EN =5.5V V ST =0.8V ST open load/shor circui volage (ST-pin acing as diagnosis oupu) ST open load/shor circui curren (ST-pin acing as diagnosis oupu) V S > 8 V T j = C V IN_SET = 4 V V S = V OUT (OL) or V OUT = 0V (SC) V ST(OL/SC) V V S > 8 V T j = C R ST = 470 kω V S = V OUT (OL) or V OUT = 0V (SC) I ST(OL/SC) µa V S > 8 V T j = C V ST = 2.5 V V S = V OUT (OL) or V OUT = 0V (SC) D high hreshold V D(h) V V S > 8 V D oupu curren I D µa V S > 8 V V D = 2 V OL deecion volage V PS(OL) V V S >8V V PS(OL) = V S - V OUT Shor circui o GND V OUT(SC) V V S >8V deecion hreshold IN_SET diagnosis rese ime IN_SET(rese) 5 20 µs V S > 8 V SC deecion curren in case of unconneced STpin I OUT(SC,STu) µa V S > 8 V V OUT = 0 V Daa Shee 28 Rev. 1.1,

29 Load Diagnosis Elecrical Characerisics IN_SET pin and Load Diagnosis (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET = 12 kω, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions SC deecion curren in case of ST-pin shored o GND IN_SET acivaion curren wihou urn on of oupu sage No subjec o producion es, specified by design Min. Typ. Max. I OUT(SC,STG) ma V S > 8 V V OUT = 0 V V ST = 0 V I IN_SET(ac) 2 15 µa See Figure 15 Daa Shee 29 Rev. 1.1,

30 Power Sage 11 Power Sage The oupu sage is realized as high side curren source wih a curren of 360 ma. During off sae he leakage curren a he oupu sage is minimized in order o preven a slighly glowing LED. The maximum curren of he channel is limied by he power dissipaion and used PCB cooling areas (which resuls in he applicaions R hja ). For an operaing curren conrol loop he supply and oupu volages according o he following parameers have o be considered: Required supply volage for curren conrol V S(CC), Pos Volage drop over oupu sage during curren conrol V PS(CC), Pos Required oupu volage for curren conrol V OUT(CC), Pos Proecion The device provides embedded proecive funcions, which are designed o preven IC desrucion under faul condiions described in his daa shee. Faul condiions are considered as ouside normal operaing range. Proecive funcions are neiher designed for coninuous nor for repeiive operaion Over Load Behavior An over load deecion circui is inegraed in he LITIX TM Basic IC. I is realized by a emperaure monioring of he oupu sage (OUT). As soon as he juncion emperaure exceeds he curren reducion emperaure hreshold T j(crt) he oupu curren will be reduced by he device by reducing he IN_SET reference volage V IN_SET(ref). This feaure avoids LED s flickering during saic oupu overload condiions. Furhermore, i proecs LEDs agains over emperaure, which are mouned hermally close o he device. If he device emperaure sill increases, he oupu curren decreases close o 0 A. As soon as he device cools down he oupu curren rises again. I OUT V IN_SET T j(crt) T j Figure 25 Oupu curren reducion a high emperaure Noe: This high emperaure oupu curren reducion is realized by reducing he IN_SET reference volage volage (Pos In case of very high power loss applied o he device and very high juncion emperaure he oupu curren may drop down o I OUT = 0 ma, afer a sligh cooling down he curren increases again Reverse Baery Proecion The TLD1125EL has an inegraed reverse baery proecion feaure. This feaure proecs he driver IC iself, bu also conneced LEDs. The oupu reverse curren is limied o I OUTx(rev) by he reverse baery proecion. Daa Shee 30 Rev. 1.1,

31 Power Sage Noe: Due o he reverse baery proecion a reverse proecion diode for he ligh module may be obsolee. In case of high ISO-pulse requiremens and only minor proecing componens like capaciors a reverse proecion diode may be reasonable. The exernal proecion circui needs o be verified in he applicaion Elecrical Characerisics Power Sage Elecrical Characerisics Power Sage Unless oherwise specified: V S = 5.5 V o 18 V, T j = -40 C o +150 C, V OUT = 3.6 V, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Oupu leakage curren I OUT(leak) Oupu leakage curren in boos over baery seup 21 9 µa V EN = 5.5 V I IN_SET = 0 µa V OUT =2.5V T j = 150 C T j = 85 C -I OUT(leak,B2B) 150 µa V EN = 5.5 V I IN_SET =0µA V OUT = V S = 40 V Reverse oupu curren -I OUT(rev) 3 µa V S = -16 V Oupu load: LED wih break down volage <-0.6V Oupu curren accuracy limied emperaure range Oupu curren accuracy over emperaure Volage drop over power sage during curren conrol V PS(CC) = V S - V OUT Required oupu volage for curren conrol k LT k ALL V PS(CC) 0.75 V V OUT(CC) 2.3 V T j = C V S = V V PS = 2 V R SET = kω R SET = 30 kω T j = C V S = V V PS = 2 V R SET = kω R SET = 30 kω V S = 13.5 V R SET = 12 kω I OUT 90% of (k LT(yp) /R SET ) V S = 13.5 V R SET = 12 kω I OUT 90% of (k LT(yp) /R SET ) Maximum oupu curren I OUT(max) 360 ma R SET = 4.7 kω The maximum oupu curren is limied by he hermal condiions. Please refer o Pos Pos Daa Shee 31 Rev. 1.1,

32 Power Sage Elecrical Characerisics Power Sage (con d) Unless oherwise specified: V S = 5.5 V o 18 V, T j = -40 C o +150 C, V OUT = 3.6 V, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max PWMI urn on ime ON(PWMI) 15 µs 2) V S = 13.5 V R SET = 12 kω PWMI L I OUT = 80% of (k LT(yp) /R SET ) PWMI urn off ime OFF(PWMI) 10 µs 2) V S = 13.5 V R SET = 12 kω PWMI H I OUT = 20% of (k LT(yp) /R SET ) ST urn on ime ON(ST) 15 µs 3) V S = 13.5 V R SET = 12 kω ST L I OUT = 80% of (k LT(yp) /R SET ) ST urn off ime OFF(ST) 10 µs 3) V S = 13.5 V R SET = 12 kω ST H I OUT = 20% of (k LT(yp) /R SET ) IN_SET urn on ime ON(IN_SET) 15 µs V S = 13.5 V I IN_SET = µa I OUT = 80% of (k LT(yp) /R SET ) IN_SET urn off ime OFF(IN_SET) 10 µs V S = 13.5 V I IN_SET =100 0µA I OUT = 20% of (k LT(yp) /R SET ) VS urn on ime ON(VS) 20 µs 4) V EN =5.5V R SET = 12 kω V S = V I OUT = 80% of (k LT(yp) /R SET ) Curren reducion emperaure hreshold T j(crt) 140 C I OUT = 95% of (k LT(yp) /R SET ) Oupu curren during curren reducion a high emperaure I OUT(CRT) No subjec o producion es, specified by design 2) see also Figure 8 3) see also Figure 18 4) see also Figure 6 85% of (k LT(yp) / R SET ) A R SET =12kΩ T j = 150 C Daa Shee 32 Rev. 1.1,

33 Applicaion Informaion 12 Applicaion Informaion Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. V ba BCM channel 1 inernal power supply IN1 ESD IS1 proecion SEN logic load curren sense gae conrol & charge pump open load deecion emperaure sensor PROFET clamp for inducive load muli sep load curren limiaion VBB OUT1 IN2 IS2 channel 2 conrol and proecion circui equivalen o channel 1 OUT2 RGND GND TAIL BRAKE C mod=2.2µf ISO-Pulse proecion circui depending on requiremens 10kΩ C VS =4.7nF EN VS Inernal supply Thermal proecion Oupu conrol Rear Ligh assembly 4.7nF** PWMI OUT D R PWMI C PWMI C D R SET IN_SET Curren adjus Basic LITIX TM LED Basic Driver Saus ST GND GND 470kΩ* Evenually o oher Basic LITIX TM LED Basic Driver CST=100pF** * In case PWM via VS is performed. ** For EMI improvemen, if required. Figure 26 Applicaion Diagram Noe: This is a very simplified example of an applicaion circui. In case of high ISO-pulse requiremens a reverse proecion diode may be used for LED proecion. The funcion mus be verified in he real applicaion Furher Applicaion Informaion For furher informaion you may conac hp:// Daa Shee 33 Rev. 1.1,

34 Package Oulines 13 Package Oulines Sand Off (1.45) 1.7 MAX. C 0.08 C 0.35 x ± C D ± MAX ±0.05 2) 0.15 M C A-B D 14x D 6 ± M D 8x Boom View A B 0.1 C A-B 2x 4.9 ±0.1 Exposed Diepad 3 ± ±0.2 Index Marking Does no include plasic or meal prorusion of 0.15 max. per side 2) Does no include dambar prorusion Dimensions in mm PG-SSOP-14-1,-2,-3-PO V02 Figure 27 PG-SSOP14 Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp:// Daa Shee 34 Rev. 1.1,

35 Revision Hisory 14 Revision Hisory Revision Dae Changes Inial revision of daa shee Updaed parameers K LT and K ALL in he chaper Power Sage. Daa Shee 35 Rev. 1.1,

36 Ediion Published by Infineon Technologies AG Munich, Germany 2015 Infineon Technologies AG All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.