CoolSET -F3 (Jitter Version)

Transcription

1 Daashee, Version 2.0, 14 Nov 2006 CoolSET F3 (Jier Version) ICE3B0365JG ICE3B0565JG OffLine SMPS Curren Conroller wih inegraed 650V Sarup Cell/Depleion CoolMOS Power Managemen Supply Never sop hinking.

2 ICE3B0365JG / ICE3B0565JG Revision Hisory: Daashee Previous Version:1.1 Page Subjecs (major changes since las revision) 3, 4, 5, 19 Updae o Pbfree package ( PCN A ) 6,8,12,13 Revise ypo o he rigger level in Vsofs ( C2 ) and VFB ( C6a ) 11 Revise ypo in figure Add pulse drain curren 20,21 Add schemaic for recommended PCB layou For quesions on echnology, delivery and prices please conac he Infineon Technologies Offices in Germany or he Infineon Technologies Companies and Represenaives worldwide: see our webpage a hp:// CoolMOS, CoolSET are rademarks of Infineon Technologies AG. Ediion Published by Infineon Technologies AG, S.MarinSrasse 53, D81541 München Infineon Technologies AG All Righs Reserved. Aenion please! The informaion herein is given o describe cerain componens and shall no be considered as warraned characerisics. Terms of delivery and righs o echnical change reserved. We hereby disclaim any and all warranies, including bu no limied o warranies of noninfringemen, regarding circuis, descripions and chars saed herein. Infineon Technologies is an approved CECC manufacurer. Informaion For furher informaion on echnology, delivery erms and condiions and prices please conac your neares Infineon Technologies Office in Germany or our Infineon Technologies Represenaives worldwide (see address lis). Warnings Due o echnical requiremens componens may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies Office. Infineon Technologies Componens may only be used in lifesuppor devices or sysems wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha lifesuppor device or sysem, or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body, or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

3 OffLine SMPS Curren Conroller wih inegraed 650V Sarup Cell/Depleion CoolMOS Produc Highlighs CoolSET F3 ICE3B0365JG ICE3B0565JG Acive Burs o reach he lowes Sandby Power Requiremens < 100mW Adjusable Blanking Window for High Load Jumps o increase Reliabiliy Frequency Jiering for Low EMI Pbfree lead plaing, RoHS compilan PGDSO16/12 PDSO127 Feaures 650V Avalanche Rugged CoolMOS wih buil in swichable Sarup Cell Acive Burs for lowes Sandby ligh load conrolled by Feedback Signal Fas Load Jump Response in Acive Burs 67 khz fixed Swiching Frequency Auo Resar for Over emperaure Deecion Auo Resar for Overvolage Deecion Auo Resar for Overload and Open Loop Auo Resar for VCC Undervolage User defined Sof Sar Minimum of exernal Componens required Max Duy Cycle 75% Overall Tolerance of Curren Limiing < ±5% Inernal Leading Edge Blanking BiCMOS echnology provides wide VCC Range Frequency jiering for Low EMI Descripion The CoolSET F3(Jier version) mees he requiremens for OffLine Baery Adapers and low cos SMPS for he lower power range. By use of a BiCMOS echnology a wide VCC range up o 26V is provided. This covers he changes in he auxiliary supply volage if a CV/CC regulaion is implemened on he secondary side. Furhermore an Acive Burs is inegraed o fullfill he lowes Sandby Power Requiremens <100mW a no load and V in = 270VAC. As during Acive Burs he conroller is always acive here is an immediae response on load jumps possible wihou any black ou in he SMPS. In Acive Burs he ripple of he oupu volage can be reduced <1%. Furhermore Auo Resar is enered in case of Overemperaure, VCC Overvolage, Oupu Open loop or Overload and VCC Undervolage. By means of he inernal precise peak curren limiaion, he dimension of he ransformer and he secondary diode can be lowered which leads o more cos efficiency. Typical Applicaion VAC C Bulk Snubber Converer DC Oupu VCC C VCC Drain Power Managemen Sarup Cell GND PWM Conroller Curren Precise Low Tolerance Peak Curren Limiaion Conrol Uni Acive Burs Auo Resar Depl. CoolMOS CoolSET F3 (Jier Version) CS FB SofS C SofS R Sense Type Package Marking V DS F OSC 1) R DSon 230VAC ±15% 2) VAC 2) ICE3B0365JG PGDSO16 12 ICE3B0365JG 650V 67kHz 6.45Ω 22W 10W ICE3B0565JG PGDSO16 12 ICE3B0565JG 650V 67kHz 4.70Ω 25W 12W 1) T=25 C 2) Calculaed maximum inpu power raing a T a =75 C, T j =125 C and wihou copper area as hea sink Version Nov 2006

4 Table of Conens Page 1 Pin Configuraion and Funcionaliy Pin Configuraion wih PGDSO16/ Pin Funcionaliy Represenaive Blockdiagram Funcional Descripion Inroducion Power Managemen Sarup Phase PWM Secion Oscillaor PWMLach FF Gae Driver Curren Limiing Leading Edge Blanking Propagaion Delay Compensaion Conrol Uni Adjusable Blanking Window Acive Burs Enering Acive Burs Working in Acive Burs Leaving Acive Burs Proecion s Auo Resar Elecrical Characerisics Absolue Maximum Raings Operaing Range Characerisics Supply Secion Inernal Volage Reference PWM Secion Conrol Uni Curren Limiing CoolMOS Secion Ouline Dimension Schemaic for recommended PCB layou Version Nov 2006

5 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion wih PGDSO16/12 Pin Symbol Funcion 1 N.C. No Conneced 2 SofS SofSar 3 FB Feedback 4 CS Curren Sense/ 650V 1) Depl. CoolMOS Source 5 Drain 650V 1) Depl. CoolMOS Drain 6 Drain 650V 1) Depl. CoolMOS Drain 7 Drain 650V 1) Depl. CoolMOS Drain 8 Drain 650V 1) Depl. CoolMOS Drain 9 N.C. No Conneced 10 N.C. No Conneced 11 VCC Conroller Supply Volage 12 GND Conroller Ground 1) a T j = 110 C 1.2 Pin Funcionaliy SofS (Sof Sar, Auo Resar Frequency Jiering Conrol) The SofS pin combines he funcion of Sof Sar during Sar Up and error deecion for Auo Resar. These funcions are implemened and can be adjused by means of an exernal capacior a SofS o ground. This capacior also provides an adjusable blanking window for high load jumps, before he IC eners ino Auo Resar. Furhermore his pin is also used o conrol he period of frequency jiering during normal load. FB (Feedback) The informaion abou he regulaion is provided by he FB Pin o he inernal Proecion Uni and o he inernal PWMComparaor o conrol he duy cycle. The FB Signal conrols in case of ligh load he Acive Burs of he conroller. CS (Curren Sense) The Curren Sense pin senses he volage developed on he series resisor insered in he source of he inegraed DeplCoolMOS. If CS reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore he curren informaion is provided for he PWM Comparaor o realize he Curren. Package PGDSO16/12 N.C 1 12 GND Drain (Drain of inegraed Depl. CoolMOS ) Pin Drain is he connecion o he Drain of he inernal Depl. CoolMOS TM. SofS FB VCC N.C VCC (Power supply) The VCC pin is he posiive supply of he IC. The operaing range is beween 10.3V and 26V. CS 4 9 N.C. GND (Ground) The GND pin is he ground of he conroller. Drain 5 8 Drain Drain 6 7 Drain Figure 1 Pin Configuraion PGDSO16/12 Noe: Pin 5, 6, 7, and 8 are shored wihin he package. Version Nov 2006

6 VAC SofS C SofS FB C Bulk 5V Power Managemen R SofS 3.25kΩ T2 T3 0.8V Inernal Bias Volage Reference 5V S1 3V 3.1V C2 T1 Thermal Shudown T j >140 C PowerDown Rese Spike Blanking 8.0us Undervolage Lockou 18V 10.3V Sof Sar C7 SofSar Comparaor G7 5V R FB 25kΩ 2pF Conrol Uni 4.0V 4.5V 1.35V 3.0V C3 C4 C5 C6a G5 Auo Resar ICE3xxx65J / CoolSET F3 Jier version 0.6V PWM OP x3.2 Curren PWM Comparaor C8 C VCC VCC Drain Depl. CoolMOS Oscillaor 0.75 PWM Secion Duy Cycle max Clock 1 G8 FF1 S R Q Gae Driver G9 PropagaionDelay Compensaion G10 C10 C12 V csh 0.32V Leading Edge Blanking 220ns 1pF 10kΩ D1 Curren Limiing GND CS R Sense + Converer DC Oupu V OUT 2 Represenaive Blockdiagram VCC 20.5V C13 UVLO G12 S Q R FF2 G V C6b G6 Acive Burs G11 Snubber Sarup Cell Freq Jier Figure 2 Represenaive Blockdiagram Version Nov 2006

7 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.1 Inroducion CoolSET F3 Jier version is he furher developmen of he CoolSET F2 o mee he requiremens for he lowes Sandby Power a minimum load and no load condiions. A new fully inegraed Sandby Power concep is implemened ino he IC in order o keep he applicaion design easy. Compared o CoolSET F2 no furher exernal pars are needed o achieve he lowes Sandby Power. An inelligen Acive Burs is used for his Sandby. Afer enering his mode here is sill a full conrol of he power conversion by he secondary side via he same opocoupler ha is used for he normal PWM conrol. The response on load jumps is opimized. The volage ripple on V ou is minimized. V ou is furher on well conrolled in his mode. The usually exernal conneced RCfiler in he feedback line afer he opocoupler is inegraed in he IC o reduce he exernal par coun. Furhermore a high volage Sarup Cell is inegraed ino he IC which is swiched off once he Undervolage Lockou onhreshold of 18V is exceeded. This Sarup Cell is par of he inegraed Depl. CoolMOS. The exernal sarup resisor is no longer necessary as his Sarup Cell is conneced o he Drain. Power losses are herefore reduced. This increases he efficiency under ligh load condiions drasically. The SofSar capacior is also used for providing an adjusable blanking window for high load jumps. During his ime window he overload deecion is disabled. Wih his concep no furher exernal componens are necessary o adjus he blanking window. An Auo Resar is implemened in he IC o reduce he average power conversion o in he even of malfuncion or unsafe operaing condiion in he SMPS sysem. This feaure increases he sysem s robusness and safey which would oherwise lead o a desrucion of he SMPS. Once he malfuncion is removed, normal operaion is auomaically iniiaed afer he nex Sar Up Phase. The inernal precise peak curren limiaion reduces he coss for he ransformer and he secondary diode. The influence of he change in he inpu volage on he power limiaion can be avoided ogeher wih he inegraed Propagaion Delay Compensaion. Therefore he maximum power is nearly independen on he inpu volage which is required for wide range SMPS. There is no need for an exra oversizing of he SMPS, e.g. he ransformer or he secondary diode. 3.2 Power Managemen Drain Power Managemen Inernal Bias PowerDown Rese T1 Sarup Cell SofS Undervolage Lockou 18V 10.3 Volage Reference Auo Resar Acive Burs Figure 3 Power Managemen The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is conneced o he VCC pin. The VCC charge curren ha is provided by he Sarup Cell from he Drain pin is 1.05mA. When V VCC exceeds he onhreshold V CCon =18V, bias circui is swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swichon a hyseresis is implemened. The swichoff of he conroller can only ake place afer Acive was enered and V VCC falls below 10.3V. The maximum curren consumpion before he conroller is acivaed is abou 300uA. 5V VCC Version Nov 2006

8 When V VCC falls below he offhreshold V CCoff =10.3V he bias circui is swiched off and he Power Down rese le T1 discharging he sofsar capacior C SofS a pin SofS. Thus i is ensured ha a every sarup cycle he volage ramp a pin SofS sars a zero. The bias circui is swiched off if Auo Resar is enered. The curren consumpion is hen reduced o 300uA. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar does no require disconnecing he SMPS from he AC line. When Acive Burs is enered, some inernal Bias is swiched off in order o reduce he curren consumpion o abou 500uA while keeping a comparaor (which rigger if V FB has exceeded 3.61V) and he Sof Sar capacior clamped a 3.0 V as his is necessary in his mode. When he Sof Sar begins, C SofS is immediaely charged up o approx. 0.8V by T2. Therefore he Sof Sar Phase akes place beween 0.8V and 3.1V. Above V SofsS = 3.1V here is no longer duy cycle limiaion DC max which is conrolled by comparaor C7 since comparaor C2 blocks he gae G7 (see Figure 5).This maximum charge curren in he very firs sage when V SofS is below 0.8V, is limied o 1.5mA. V SofS 4.0V 3.1V 0.8V max. Sof Sar Phase max. Sarup Phase 3.3 Sarup Phase DC max 3.25kΩ 5V DC 1 DC 2 R SofS SofS C SofS 3.1V Freq Jier Charging curren I FJ Freq Jier Discharging curren I FJ Sof Sar C7 C2 T2 SofSar Comparaor G7 x3.2 T3 Freq Jier Conrol 0.8V Gae Driver PWM OP CS 1 2 Figure 5 Sarup Phase By means of his exra charge sage, here is no delay in he beginning of he Sarup Phase when here is sill no swiching. Furhermore Sof Sar is finished a 3.1V o have faser he maximum power capabiliy. The duy cycles DC 1 and DC 2 are depending on he mains and he primary inducance of he ransformer. The limiaion of he primary curren by DC 2 is relaed o V SofS = 3.1V. Bu DC 1 is relaed o a maximum primary curren which is limied by he inernal Curren Limiing wih CS = 1V. Therefore he maximum Sarup Phase is divided ino a Sof Sar Phase unil 1 and a phase from 1 unil 2 where maximum power is provided if demanded by he FB signal. 0.6V Figure 4 Sof Sar A he beginning of he Sarup Phase, he IC provides a Sof Sar duraion whereby i conrols he maximum primary curren by means of a duy cycle limiaion. A capacior C Sofs in combinaion wih he inernal pull up resisor R SofS deermines he duy cycle unil V SofS exceeds 3.1V. Version Nov 2006

9 3.4 PWM Secion Oscillaor Duy Cycle max Clock 0.75 PWM Secion PWMLach FF1 The oscillaor clock oupu provides a se pulse o he PWMLach when iniiaing he inernal CoolMOS conducion. Afer seing he PWMLach can be rese by he PWM comparaor, he Sof Sar comparaor or he CurrenLimi comparaor. In case of reseing he driver is shu down immediaely. Frequency Jier Sof Sar Comparaor PWM Comparaor 1 G8 FF1 S R Q Gae Driver G Gae Driver The Gae Driver is a fas oem pole gae drive which is designed o avoid cross conducion currens. The Gae Driver is acive low a volages below he undervolage lockou hreshold V VCCoff. Curren Limiing VCC SofS Gae PWMLach 1 Figure 6 PWM Secion Gae Oscillaor and Jiering The oscillaor generaes a fixed frequency wih frequency jiering of ±4% from he fixed frequency (which is ±2.7kHz from 67kHz) a a jiering period T FJ. The swiching frequency of ICE3B0x65JG is f swich = 67kHz. A resisor, a capacior and a curren source and curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed, in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Once he Sof Sar period is over and when he IC goes ino normal mode, he Sof Sar capacior will be charged and discharged hrough inernal curren source, I FJ o generae a riangular waveform wih a jiering period,t FJ which is exernally adjusable by he Sof Sar capacior, C SofS (See Figure 4). Gae Driver Figure 7 Gae Driver Depl. CoolMOS T FJ = k FJ * C SofS where k FJ is a consan = 4 ms/uf eg. T FJ = 4 ms if C SofS = 1 uf Version Nov 2006

10 3.5 Curren Limiing Leading Edge Blanking V Sense PWM Lach FF1 Curren Limiing V csh LEB = 220ns PWMOP G10 Acive Burs PropagaionDelay Compensaion CS C10 C12 V csh 0.32V 10kΩ D1 Leading Edge Blanking 220ns 1pF Figure 8 Curren Limiing There is a cycle by cycle Curren Limiing realized by he CurrenLimi comparaor C10 o provide an overcurren deecion. The source curren of he inegraed Depl. CoolMOS is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense which is fed ino he pin CS. If he volage V Sense exceeds he inernal hreshold volage V csh he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down wihou delay of he inegraed inernal CoolMOS in case of Curren Limiing. The influence of he AC inpu volage on he maximum oupu power can hereby be avoided. To preven he Curren Limiing from disorions caused by leading edge spikes a Leading Edge Blanking is inegraed in he curren sense pah for he comparaors C10, C12 and he PWMOP. The oupu of comparaor C12 is acivaed by he Gae G10 if Acive Burs is enered. Once acivaed he curren limiing is hereby reduced o 0.32V. This volage level deermines he power level when he Acive Burs is lef if here is a higher power demand. Figure 9 Leading Edge Blanking Each ime when he inegraed inernal CoolMOS is swiched on a leading edge spike is generaed due o he primaryside capaciances and secondaryside recifier reverse recovery ime. This spike can cause he gae drive o swich off uninenionally. To avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220ns. During his ime, he gae drive will no be swiched off Propagaion Delay Compensaion In case of overcurren deecion, he swichoff of he inegraed inernal CoolMOS is delayed due o he propagaion delay of he circui. This delay causes an overshoo of he peak curren I peak which depends on he raio of di/d of he peak curren (see Figure 10). I peak2 I peak1 I Limi I Sense Signal2 I Overshoo2 Signal1 Propagaion Delay Figure 10 Curren Limiing The overshoo of Signal2 is bigger han of Signal1 due o he seeper rising waveform. This change in he slope is depending on he AC inpu volage. Propagaion Delay Compensaion is inegraed o limi he overshoo dependency on di/d of he rising primary curren. Tha means he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swich off of he inegraed inernal CoolMOS is compensaed over emperaure wihin a wide range. I Overshoo1 Version Nov 2006

11 Curren Limiing is now possible in a very accurae way. E.g. I peak = 0.5A wih R Sense = 2. Wihou Propagaion Delay Compensaion he curren sense hreshold is se o a saic volage level V csh =1V. A curren ramp of di/d = 0.4A/µs, ha means dv Sense /d = 0.8V/µs, and a propagaion delay ime of i.e. Propagaion Delay =180ns leads hen o an I peak overshoo of 14.4%. By means of propagaion delay compensaion he overshoo is only abou 2% (see Figure 11). V 1,3 1,25 1,2 wih compensaion wihou compensaion 3.6 Conrol Uni The Conrol Uni conains he funcions for Acive Burs and Auo Resar. The Acive Burs and he Auo Resar are combined wih an Adjusable Blanking Window which is depending on he exernal Sof Sar capacior. By means of his Adjusable Blanking Window, he IC avoids enering ino hese wo modes accidenally. Furhermore i also provides a cerain ime whereby he overload deecion is delayed. This delay is useful for applicaions which normally works wih a low curren and occasionally require a shor duraion of high curren Adjusable Blanking Window V Sense 1,15 1,1 1,05 1 SofS S3 R SofS 5V 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 dv Sense d V µ s S1 3.0V S2 Frequency Jier Figure 11 Overcurren Shudown The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (see Figure 12). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. 4.0V C3 V OSC max. Duy Cycle 4.5V C4 G5 Auo Resar off ime Acive Burs V csh V Sense Propagaion Delay FB C5 G6 1.35V Conrol Uni Signal1 Signal2 Figure 13 Adjusable Blanking Window Figure 12 Dynamic Volage Threshold V csh V SofS swings beween 3.2V and 3.6V afer he SMPS is seled and S2 is on while S3 is off, his is due o he frequency jiering funcion ha is making use of he Sof Sar pin. If overload occurs V FB is exceeding 4.5V. Auo Resar can be enered as he gae G5 is sill blocked by he comparaor C3. Bu afer V FB has Version Nov 2006

12 exceeded 4.5V he swich S2 is opened and S3 is closed. The exernal Sof Sar capacior can now be charged furher by he inegraed pull up resisor R SofS via swich S3. The comparaor C3 releases he gaes G5 and G6 once V Sofs has exceeded 4.0V. Therefore here is no enering of Auo Resar possible during his charging ime of he exernal capacior C SofS. The same procedure happens o he exernal Sof Sar capacior if a low load condiion is deeced by comparaor C5 when V FB is falling below 1.35V. Only afer V SofS has exceeded 4.0V and V FB is sill below 1.35V Acive Burs is enered Acive Burs The conroller provides Acive Burs for low load condiions a V OUT. Acive Burs increases significanly he efficiency a ligh load condiions while supporing a low ripple on V OUT and fas response on load jumps. During Acive Burs which is conrolled only by he FB signal he IC is always acive and can herefore immediaely response on fas changes a he FB signal. The Sarup Cell is kep swiched off o avoid increased power losses for he self supply. SofS FB Figure 14 S1 4.0V 4.5V 1.35V 3.61V 3.0V 3.0V C3 C4 C5 C6a C6b S3 S2 Acive Burs Conrol Uni R SofS Frequency Jier G6 5V Inernal Bias G11 Curren Limiing G10 Acive Burs The Acive Burs is locaed in he Conrol Uni. Figure 14 shows he relaed componens Enering Acive Burs The FB signal is always observed by he comparaor C5 if he volage level falls below 1.35V. In ha case he swich S1 and S2 is released which allows he capacior C SofS o be charged via S3 saring from he swinging volage level beween 3.2V and 3.6V in normal operaing mode. If V SofS exceeds 4.0V he comparaor C3 releases he gae G6 o ener he Acive Burs. The ime window ha is generaed by combining he FB and SofS signals wih gae G6 avoids a sudden enering of he Acive Burs due o large load jumps. This ime window can be adjused by he exernal capacior C SofS. Afer enering Acive Burs a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC down o approx. 500uA. Also, swich S1 is closed o clamped he Sof Sar volage o 3.0V. In his Off Sae Phase he IC is no longer self supplied so ha herefore C VCC has o provide he VCC curren (see Figure 15). Furhermore gae G11 is hen released o sar he nex burs cycle once V FB has 3.0V exceeded. I has o be ensured by he applicaion ha he VCC remains above he Undervolage Lockou Level of 10.3V o avoid ha he Sarup Cell is accidenally swiched on. Oherwise power losses are significanly increased. The minimum VCC level during Acive Burs is depending on he load condiions and he applicaion. The lowes VCC level is reached a no load condiions a V OUT Working in Acive Burs Afer enering he Acive Burs he FB volage rises as V OUT sars o decrease due o he inacive PWM secion. Comparaor C6a observes he FB signal if he volage level 3.6V is exceeded. In ha case he inernal circui is again acivaed by he inernal Bias o sar wih swiching. As now in Acive Burs he gae G10 is released he curren limi is only 0.32V o reduce he conducion losses and o avoid audible noise. If he load a V OUT is sill below he saring level for he Acive Burs he FB signal decreases down o 3.0V. A his level C6b deacivaes again he inernal circui by swiching off he inernal Bias. The gae G11 is released as afer enering Acive Burs he burs flag is se. If working in Acive Burs he FB volage is changing like a saw ooh beween 3.0V and 3.61V (see figure 15) Leaving Acive Burs The FB volage immediaely increases if here is a high load jump. This is observed by comparaor C4. As he curren limi is ca. 32% during Acive Burs a cerain load jump is needed ha FB can exceed 4.5V. A his ime C4 reses he Acive Burs which also Version Nov 2006

13 blocks C12 by he gae G10. Maximum curren can now be provided o sabilize V OUT. V FB 4.5V 3.61V 3.0V 1.35V V SofS 4.0V 3.6V~ 3.2V 3.0V Enering Acive Burs Blanking Window Leaving Acive Burs Proecion s The IC provides several proecion feaures ha increase he SMPS sysem s robusness and safey. The following able shows he possible sysem failures and he corresponding proecion modes. VCC Overvolage Over emperaure Overload Open Loop VCC Undervolage Shor Opocoupler Auo Resar I Auo Resar I Auo Resar I Auo Resar II Auo Resar II Auo Resar II Auo Resar II V CS SofS 1.0V 0.32V V VCC 10.3V I VCC Curren limi level during Acive Burs 4.0V UVLO VCC 20.5V C3 S R Q FF2 C13 G13 Spike Blanking 8.0us Auo Resar 2mA 4.5V C4 G12 Inernal Bias 500uA Thermal Shudown V OUT T j >140 C Conrol Uni Max. Ripple < 1% FB Figure 16 Auo Resar I Figure 15 Signals in Acive Burs The VCC volage is observed by comparaor C13 if 20.5V is exceeded. The oupu of C13 is combined wih boh he oupu of C3 which checks for V SofS < 4.0V and he oupu of C4 which checks for V FB > 4.5V. Therefore he overvolage deecion can only be acive during Sof Sar Phase (V SofS < 4.0V) and when FB signal is ouside he operaing range > 4.5V. This means any Version Nov 2006

14 small volage overshoos of V VCC during normal operaing canno rigger he Auo Resar I. In Order o ensure sysem reliabiliy and preven any false acivaion, a blanking ime is implemened before he IC can ener ino he Auo Resar I. The oupu of he VCC overvolage deecion is fed ino a spike blanking wih a ime consan of 8.0us. The oher faul deecion which can resul in he Auo Resar I and has his 8.0us blanking ime is he Overemperaure deecion. This block checks for a juncion emperaure of higher han 140 C for malfuncion operaion. Once Auo Resar is enered, he inernal bias is swiched off in order o reduce he curren consumpion of he IC as much as possible. In his mode, he average curren consumpion is only 300uA as he only working blocks are he reference block and he Undervolage Lockou(UVLO) which conrols he Sarup Cell by swiching on/off a V VCCon /V VCCoff. As here is no longer a self supply by he auxiliary winding, VCC sars o drop. The UVLO swiches on he inegraed Sarup Cell when VCC falls below 10.3V. I will coninue o charge VCC up o 18V whereby i is swiched off again and he IC eners ino he Sar Up Phase. As long as all faul condiions have been removed, he IC will auomaically power up as usual wih swiching cycle a he GATE oupu afer Sof Sar duraion. Thus he name Auo Resar. This charging of he Sof Sar capacior from 3.2V~3.6V o 4.0V defines a blanking window which prevens he sysem from enering ino Auo Resar II uninenionally during large load jumps. In his even, FB will rise close o 5.0V for a shor duraion before he loop regulaes wih FB less han 4.5V. This is he same blanking ime window as for he Acive Burs and can herefore be adjused by he exernal C SofS. In case of VCC undervolage, ie. VCC falls below 10.3V, he IC will be urned off wih he Sarup Cell charging VCC as described earlier in his secion. Once VCC is charged above 18V, he IC will sar a new sarup cycle. The same procedure applies when he sysem is under Shor Opocoupler faul condiion, as i will lead o VCC undervolage Auo Resar II SofS Inernal Bias 4.0V C3 4.5V FB C4 G5 Auo Resar Conrol Uni Figure 17 Auo Resar II In case of Overload or Open Loop, FB exceeds 4.5V which will be observed by C4. A his ime, he exernal Sof Sar capacior can now be charged furher by he inegraed pull up resisor R SofS via swich S3 (see Figure 13). If V SofS exceeds 4.0V which is observed by C3, Auo Resar II is enered as boh inpus of he gae G5 are high. Version Nov 2006

15 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 12). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 11 (VCC) is discharged before assembling he applicaion circui. Parameer Symbol Limi Values Uni Remarks min. max. Drain Source Volage V DS 650 V T j = 110 C Pulse drain curren, ICE3B0365JG I D_Puls1 1.6 A p limied by max. T j =150 C ICE3B0565JG I D_Puls2 2.3 A Avalanche energy, repeiive AR limied by max. T j =150 C 1) ICE3B0365JG ICE3B0565JG E AR1 E AR mj mj Avalanche curren, ICE3B0365JG I AR1 0.3 A repeiive AR limied by max. T j =150 C 1) ICE3B0565JG I AR2 0.5 A VCC Supply Volage V VCC V FB Volage V FB V SofS Volage V SofS V CS Volage V CS V Juncion Temperaure T j C Conroller CoolMOS Sorage Temperaure T S C Thermal Resisance R hja 110 K/W PGDSO16/12 JuncionAmbien ESD Capabiliy V ESD 2 kv Human body model 2) 1) Repeeive avalanche causes addiional power losses ha can be calculaed as P AV =E AR * f 2) According o EIA/JESD22A114B (discharging a 100pF capacior hrough a 1.5kΩ series resisor) 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. VCC Supply Volage V VCC V VCCoff 26 V Juncion Temperaure of Conroller T jcon C Max value limied due o inegraed hermal shu down Juncion Temperaure of CoolMOS T JCoolMOS C Version Nov 2006

16 4.3 Characerisics Supply Secion Noe: The elecrical characerisics involve he spread of values guaraneed wihin he specified supply volage and juncion emperaure range T J from 25 o C o 130 o C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 18 V is assumed. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar µa V VCC = 17V VCC Charge Curren I VCCcharge1 5.0 ma V VCC = 0V I VCCcharge ma V VCC = 1V I VCCcharge ma V VCC = 17V Leakage Curren of Sar Up Cell CoolMOS Supply Curren wih Inacive Gae I SarLeak µa V Drain = 450V a T j = 100 C I VCCsup_ng ma Sof Sar pin is open Supply Curren wih Acive Gae I VCCsup_g ma V SofS = 3.0V I FB = 0 Supply Curren in Auo Resar wih Inacive Gae Supply Curren in Acive Burs wih Inacive Gae I VCCresar 300 µa I FB = 0 I Sofs = 0 I VCCburs ua V FB = 2.5V V SofS = 3.0V I VCCburs ua V VCC = 11.5V V FB = 2.5V V SofS = 3.0V VCC TurnOn Threshold VCC TurnOff Threshold VCC TurnOn/Off Hyseresis V VCCon V VCCoff V VCChys V V V Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF V measured a pin FB I FB = 0 Version Nov 2006

17 4.3.3 PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC khz f OSC khz T j = 25 C Frequency Jiering Range f dela ±2.7 khz T j = 25 C Max. Duy Cycle D max Min. Duy Cycle D min 0 V FB < 0.3V PWMOP Gain A V Max. Level of Volage Ramp V MaxRamp 0.6 V V FB Operaing Range Min Level V FBmin 0.5 V V FB Operaing Range Max level V FBmax 4.3 V CS=1V limied by Comparaor C4 1) Feedback PullUp Resisor R FB kω SofSar PullUp Resisor R SofS kω 1) The parameer is no subjeced o producion es verified by design/characerizaion Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Deacivaion Level for SofS V SofSC V V FB = 5V Comparaor C7 by C2 Clamped V SofS Volage during V SofSclmp_bm V Burs Acivaion Limi of V SofSC V V FB = 5V Comparaor C3 SofS Sarup Curren I SofSsar 0.9 ma V SofS = 0V Over Load Open Loop Deecion Limi for Comparaor C4 V FBC V V SofS = 4.5V Acive Burs Level for Comparaor C5 Acive Burs Level for Comparaor C6a Acive Burs Level for Comparaor C6b V FBC V V SofS = 4.5V V FBC6a V Afer Acive Burs is enered V FBC6b V Afer Acive Burs is enered Overvolage Deecion Limi V VCCOVP V V FB = 5V, V SofS = 3V Thermal Shudown 1) T jsd C Spike Blanking Spike 8.0 µs 1) The parameer is no subjeced o producion es verified by design/characerizaion Version Nov 2006

18 Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Peak Curren Limiaion (incl. Propagaion Delay Time) (see Figure 11) V csh V dv sense / d = 0.6V/µs Peak Curren Limiaion during V CS V Acive Burs Leading Edge Blanking LEB 220 ns V SofS = 3.0V CS Inpu Bias Curren I CSbias µa V CS = 0V CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Drain Source Breakdown Volage Drain Source OnResisance V (BR)DSS ICE3B0365JG R DSon1 ICE3B0565JG R DSon ) The parameer is no subjeced o producion es verified by design/characerizaion V V Ω Ω Ω Ω T j = 25 C T j = 110 C T j = 25 C T j = 125 C 1) T j = 25 C T j = 125 C 1) Effecive oupu ICE3B0365JG C o(er) pf V DS = 0V o 480V capaciance, energy relaed ICE3B0565JG C o(er) pf V DS = 0V o 480V Rise Time rise 30 2) ns Fall Time fall 30 2) ns 2) Measured in a Typical Flyback Converer Applicaion Version Nov 2006

19 5 Ouline Dimension PGDSO16/12 (Plasic Dual InLine Ouline) Figure 18 PGDSO16/12 Dimensions in mm Version Nov 2006

20 Schemaic for recommended PCB layou 6 Schemaic for recommended PCB layou TR1 L Spark Gap 1 FUSE1 XCAP C1 Spark Gap 3 L1 BR1 C11 bulk cap R11 D11 C12 D21 C21 Vo GND Spark Gap 2 N C2 YCAP C3 YCAP Spark Gap 4 C4 YCAP D11 IC11 R12 CS DRAIN F3 SOFTS/BL VCC CoolSET GND FB NC Z11 R13 R14 C16 D13 R23 R22 C22 R21 GND C13 C15 * C14 C23 R24 IC12 IC21 F3 CoolSET schemaic for recommended PCB layou R25 Figure 19 Schemaic for recommended PCB layou General guideline for PCB layou design using F3 CoolSET (refer o Figure 19): 1. Sar Ground a bulk capacior ground, C11: Sar Ground means all primary DC grounds should be conneced o he ground of bulk capacior C11 separaely in one poin. I can reduce he swiching noise going ino he sensiive pins of he CoolSET device effecively. The primary DC grounds include he followings. a. DC ground of he primary auxiliary winding in power ransformer, TR1, and ground of C16 and Z11. b. DC ground of he curren sense resisor, R12 c. DC ground of he CoolSET device, GND pin of IC11; he signal grounds from C13, C14, C15 and collecor of IC12 should be conneced o he GND pin of IC11 and hen sar connec o he bulk capacior ground. d. DC ground from bridge recifier, BR1 e. DC ground from he bridging Ycapacior, C4 2. High volage races clearance: High volage races should keep enough spacing o he nearby races. Oherwise, arcing would incur. a. 400V races (posiive rail of bulk capacior C11) o nearby race: > 2.0mm b. 600V races (drain volage of CoolSET IC11) o nearby race: > 2.5mm 3. Filer capacior close o he conroller ground: Filer capaciors, C13, C14 and C15 should be placed as close o he conroller ground and he conroller pin as possible so as o reduce he swiching noise coupled ino he conroller. Guideline for PCB layou design when >3KV lighning surge es applied (refer o Figure 19): 1. Add spark gap Spark gap is a pair of sawooh like copper plae facing each oher which can discharge he accumulaed charge during surge es hrough he sharp poin of he sawooh plae. a. Spark Gap 3 and Spark Gap 4, inpu common mode choke, L1: Gap separaion is around 1.5mm (no safey concern) Version Nov 2006

21 Schemaic for recommended PCB layou b. Spark Gap 1 and Spark Gap 2, Live / Neural o GROUND: These 2 Spark Gaps can be used when he lighning surge requiremen is >6KV. 230Vac inpu volage applicaion, he gap separaion is around 5.5mm 115Vac inpu volage applicaion, he gap separaion is around 3mm 2. Add Ycapacior (C2 and C3) in he Live and Neural o ground even hough i is a 2pin inpu 3. Add negaive pulse clamping diode, D11 o he Curren sense resisor, R12: The negaive pulse clamping diode can reduce he negaive pulse going ino he CS pin of he CoolSET and reduce he abnormal behavior of he CoolSET. The diode can be a fas speed diode such as IN4148. The principle behind is o drain he high surge volage from Live/Neural o Ground wihou passing hrough he sensiive componens such as he primary conroller, IC11. Version Nov 2006

22 Toal Qualiy Managemen Qualiä ha für uns eine umfassende Bedeuung. Wir wollen allen Ihren Ansprüchen in der besmöglichen Weise gerech werden. Es geh uns also nich nur um die Produkqualiä unsere Ansrengungen gelen gleichermaßen der Lieferqualiä und Logisik, dem Service und Suppor sowie allen sonsigen Beraungs und Bereuungsleisungen. Dazu gehör eine besimme Geiseshalung unserer Miarbeier. Toal Qualiy im Denken und Handeln gegenüber Kollegen, Lieferanen und Ihnen, unserem Kunden. Unsere Leilinie is jede Aufgabe mi Null Fehlern zu lösen in offener Sichweise auch über den eigenen Arbeisplaz hinaus und uns sändig zu verbessern. Unernehmenswei orienieren wir uns dabei auch an op (Time Opimized Processes), um Ihnen durch größere Schnelligkei den enscheidenden Webewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leisung durch umfassende Qualiä zu beweisen. Wir werden Sie überzeugen. Qualiy akes on an allencompassing significance a Semiconducor Group. For us i means living up o each and every one of your demands in he bes possible way. So we are no only concerned wih produc qualiy. We direc our effors equally a qualiy of supply and logisics, service and suppor, as well as all he oher ways in which we advise and aend o you. Par of his is he very special aiude of our saff. Toal Qualiy in hough and deed, owards coworkers, suppliers and you, our cusomer. Our guideline is do everyhing wih zero defecs, in an open manner ha is demonsraed beyond your immediae workplace, and o consanly improve. Throughou he corporaion we also hink in erms of Time Opimized Processes (op), greaer speed on our par o give you ha decisive compeiive edge. Give us he chance o prove he bes of performance hrough he bes of qualiy you will be convinced. hp:// Published by Infineon Technologies AG