Quasi-Resonant Controller

Transcription

1 ICE5QSAG Quasi-Resonan Conroller Produc Highlighs Novel Quasi-resonan operaion and proprieary implemenaion for low EMI Enhanced Acive Burs Mode wih selecable enry and exi sandby power Acive Burs Mode o reach he lowes sandby power <00 mw Fas sarup achieved wih cascode configuraion Digial frequency reducion for beer overall sysem efficiency Robus line proecion wih inpu OVP and brownou Comprehensive proecion Pb-free lead plaing, halogen free mold compound, RoHS complian Feaures Minimum swiching frequency difference beween low & high line for higher efficiency & beer EMI Enhanced Acive Burs Mode wih selecable enry and exi sandby power Acive Burs Mode o reach he lowes sandby power <00 mw Fas sarup achieved wih cascode configuraion Digial frequency reducion up o 0 zero crossings Buil-in digial sof sar Cycle-by-cycle peak curren limiaion Maximum on/off ime limiaion o avoid audible noise during sar up and power down Robus line proecion wih inpu OVP and brownou Auo resar mode proecion for VCC Over Volage, VCC Under Volage, Over load/open Loop, Oupu Over Volage, Over Temperaure and CS (Curren Sense) shor o GND Limied charging curren for VCC shor o GND Pb-free lead plaing, halogen free mold compound, RoHS complian Applicaions Auxiliary power supply for Home Appliances/whie Goods, TV, PC & Server Blu-ray player, Se-op box & LCD/LED Monior Descripion PG-DSO-8 The Quasi-Resonan, ICE5QSAG is he 5 h generaion of quasiresonan conroller opimized for off-line swich power supply in cascode configuraion. The improved digial frequency reducion wih proprieary novel Quasi-Resonan operaion offers lower EMI and higher efficiency for wide AC range by reducing he swiching frequency difference beween low and high line. The enhanced acive burs mode enables flexibiliy in sandby power range selecion. The produc has a wide operaing range (0~25.5 V) of IC power supply and lower power consumpion. The numerous proecion funcions including he robus line proecion (boh inpu OVP and brownou) o suppor he proecions of he power supply sysem in failure siuaions. All of hese make he ICE5QSAG an ousanding conroller for Quasi-Resonan flyback converer in he marke. 85 ~ 300 VAC Cbus CVCC RSTARTUP RVCC DVCC Snubber Wp Ws DO CO Lf Cf VO DZC RZC Wa Ws2 DO2 CO2 Lf2 Cf2 VO2 Dr~Dr4 RI VCC ZCD CZC VIN Power Managemen D Power MOSFET CPS # Opional RSel (Burs mode level 2) Rovs3 (V02 feedback) RI2 GND PWM conroller Curren Mode Conrol Cycle-by-Cycle curren limiaion Digial Conrol Acive Burs Mode Zero Crossing Deecion Proecions RZCD Gae Driver ICE5QSAG Conroller GATE SOURCE CS FB RCS # RSel Opocoupler Rb TL43 Rb2 Rc Cc Rovs Cc2 Rovs2 # Rovs3 Figure Table Typical applicaion Oupu Power of 5 h generaion Quasi-Resonan Conroller Type Package Marking 220VAC ±20% VAC ICE5QSAG PG-DSO-8 5QSAG 09 W 60 W Calculaed maximum oupu power raing in an open frame design a Ta=50 C, TJ=25 C. The oupu power figure is for reference purpose only. The acual power can vary depending on paricular designs. Please conac o a echnical exper from Infineon for more informaion. Daashee Please read he Imporan Noice and Warnings a he end of his documen V page of 25

2 Table of Conens Table of Conens Produc Highlighs... Feaures... Applicaions... Descripion... Pin Configuraion and Funcionaliy Represenaive Block Diagram Funcional Descripion V CC Pre-Charging and Typical V CC Volage during Sar-up Sof-sar Normal Operaion Digial Frequency Reducion Minimum ZC Coun Deerminaion Up/down couner Zero crossing (ZC couner) Ringing suppression ime Swich on deerminaion Swich off deerminaion Modulaed gae drive Curren limiaion Acive Burs Mode wih selecable power level Enering Acive Burs Mode Operaion During Acive Burs Mode Operaion Leaving Acive Burs Mode Operaion Proecion Funcions Line Over Volage Brownou V CC Ovder Volage or Under Volage Over Load Oupu Over Volage Over Temperaure CS Shor o GND Elecrical Characerisics Absolue Maximum Raings Operaing Range Operaing Condiions Inernal Volage Reference Gae Driver PWM Secion Curren Sense Sof Sar Digial Zero Crossing Acive Burs Mode Line Over Volage Proecion Brownou Proecion V CC Over Volage Proecion Over Load Proecion Oupu Over Volage Proecion... 2 Daashee 2 of 25 V 2.0

3 Table of Conens 4.6 Thermal Proecion CS Shor o GND Proecion Low side MOSFET Ouline Dimension Marking Revision hisory Daashee 3 of 25 V 2.0

4 Pin Configuraion and Funcionaliy Pin Configuraion and Funcionaliy The pin configuraion is shown in Figure 2 and he funcions are described in Table 2. FB PG-DSO-8 8 GND VIN 2 7 VCC CS 3 6 SOURCE ZCD 4 5 GATE Figure 2 Pin Configuraion Table 2 Pin Definiions and Funcions Pin Symbol Funcion FB Feedback & Burs enry/exi conrol FB pin combines he funcions of feedback conrol, selecable burs enry/exi conrol and overload/open loop proecion. 2 VIN Inpu Line OVP & Brownou VIN pin is conneced o he bus via resisor divider (see Figure ) o sense he line volage. This pin combines he funcions of inpu Line OVP, Brownou, minimum and maximum ZC coun seing for low and high line. 3 CS Curren Sense The CS pin is conneced o he shun resisor for he primary curren sensing exernally and o he PWM signal generaor block for swich-off deerminaion (ogeher wih he feedback volage) inernally. Moreover, CS pin shor o ground proecion is sensed by his pin. 4 ZCD Zero Crossing Deecion ZCD pin combines he funcions of sar up, zero crossing deecion and oupu over volage proecion. During he sar up, i is used o provide a volage level o he gae of power swich Q (see Figure ) o charge V CC capacior. 5 GATE Gae Drive Oupu This oupu signal drives he exernal main power swich Q (see Figure ). 6 SOURCE SOURCE The SOURCE pin is conneced o he source of exernal power swich Q (see Figure ) which is in series connecion wih inernal low side MOSFET and inernal VCC diode D. 7 VCC VCC(Posiive Volage Supply) The VCC pin is he posiive volage supply o he IC. The operaing range is beween V VCC_OFF and V VCC_OVP. 8 GND Ground The GND pin is he common ground of he conroller. Daashee 4 of 25 V 2.0

5 Represenaive Block Diagram 2 Represenaive Block Diagram VCC ZCD VIN VVIN_LOVP C7a 250 µs Blanking ime S R Q Auoresar Proec LOVP Inpu OVP Mode VVIN_BO C6a C6b VVIN_BI 250 µs Blanking ime S R Q Auoresar Proec Brown In / Ou Brown Ou Mode Tj > Tjcon_OTP Tj < Tjcon_OTP-TjHYS_OTP 50 µs Blanking ime Thermal Proecion S R Q Auoresar Proec OTP Mode Zero Crossing Power Managemen D VZCD_CT C2 clk ZC couner Comparaor & G Undervolage Lockou 6V 0V Volage Reference Inernal Bias Proecion S Q D3 C8 VVIN_REF VZCD_OVP C6 VIN_REF Up/down couner Couner COUNT Couner PZCD_OVP_B VVCC_OVP Sof-sar C2 50us PWM Conrol G7 G2 R Auoresar Proec S Q R Auoresar Proec RZCD VREF RFB Burs Mode deec C VZCD_RS VFB_OLP/ VFB_LB VFB_R VFB_HLC C2 C5 C3 FB_OLP_B Ringing Suppression fsb en OSC & G5 & G6 G4 G3 S R G8 Q TOffMax TOnMax Gae Driver & G9 Gae Drive Gae Drive GATE SOURCE FB VFB_LHC C4 Regulaion C3 VCS_N VCS_BL VCS_BL2 25kΩ 2pF VFB_EBL VFB_EBL2 Burs Mode Level Selec VFB_BOn VFB_BOff C9 C0 C FB_BEB Acive Burs Mode C20 PWM Comparaor VPWM V PWM OP GPWM Curren Mode C5 VCS_FB Peak Curren Limi Leading Edge Blanking Delay CS_LEB CS_STG_SAM pf C7 D2 0kΩ VCS_STG CS GND Acive Burs Block Curren Limiing/ Curren Sense shor o Gnd Proecion Figure 3 Represenaive Block Diagram Daashee 5 of 25 V 2.0

6 Funcional Descripion 3 Funcional Descripion 3. VCC Pre-Charging and Typical VCC Volage during Sar-up As shown in Figure, once he line inpu volage is applied, a recified volage appears across he capacior C BUS. The pull up resisor R STARTUP provides a curren o charge he C iss (inpu capaciance) of CoolMOS and gradually generae one volage level. If he volage over C iss is high enough, CoolMOS on and V CC capacior will be charged hrough primary inducance of ransformer L P, CoolMOS and inernal diode D 3 wih wo seps consan curren source I VCC_ Charge and I VCC_ Charge3. A very small consan curren source (I VCC_Charge) is charged o he V CC capacior ill V CC reach V CC_SCP o proec he conroller from V CC pin shor o ground during he sar up. Afer his, he second sep consan curren source (I VCC_Charge3) is provided o charge he V CC capacior furher, unil he V CC volage exceeds he urned-on hreshold V VCC_ON. As shown in he ime phase I in Figure 4, he V CC volage increase almos linearly wih wo seps. V VCC (V VCC_ON )6V I II III (V VCC_OFF ) 0V (V VCC_SCP ).V I VCC (I VCC_Normal ) 0.9mA 0 (I VCC_Charge ) -0.2mA A B 2 I VCC_Charge2/3 ) -3/-3.2mA -I VCC Figure 4 VCC volage and curren a sar up The ime aking for he V CC pre-charging can hen be approximaely calculaed as: = A + B = V VCC_SCP C VCC I VCC_Charge + (V VCC_ON V VCC_SCP ) C VCC I VCC_Charge3 () When he V CC volage exceeds he V CC urned on hreshold V VCC_ON a ime, he IC begins o operae wih sof sar. Due o power consumpion of he IC and he fac ha here is sill no energy from he auxiliary winding o charge he V CC capacior before he oupu volage is buil up, he V CC volage drops (Phase II). Once he oupu volage is high enough, he V CC capacior receives he energy from he auxiliary winding from he ime 2 onward and delivering he I VCC_ Normal2 o he conroller. The V CC hen will reach a consan value depending on oupu load. 3.2 Sof-sar As shown in Figure 5, a he ime on, he IC begins o operae wih a sof-sar. By his sof-sar he swiching sresses for he MOSFET, diode and ransformer are minimized. The sof-sar implemened in ICE5QSAG is a digial ime-based funcion. The prese sof-sar ime is SS (2 ms) wih 4 seps. If no limied by oher funcions, he peak volage on CS pin will increase sep by sep from 0.3 V o V finally. During he firs 3 ms of IVCC_ Charge/2/3 is charging curren from he conroller o VCC capacior during sar up 2 IVCC_ Normal is supply curren from VCC capacior or auxiliary winding o he conroller during normal operaion Daashee 6 of 25 V 2.0

7 Funcional Descripion sof sar, he ringing suppression ime is se o 25 µs o avoid irregular swiching due o swich off oscillaion noise. Vcs (V) V CS_Peak on Time(ms) Figure 5 Maximum curren sense volage during sof sar 3.3 Normal Operaion During normal operaion, he ICE5QSAG works wih a digial signal processing circui composing an up/down couner, a zero-crossing couner (ZC couner) and a comparaor, and an analog circui composing a curren measuremen uni and a comparaor. The swich-on and -off ime poins are each deermined by he digial circui and he analog circui, respecively. The inpu informaion of he zero-crossing signal and he value of he up/down couner are needed o deermine he swich-on while he feedback signal V FB and he curren sensing signal V CS are necessary for he swich-off deerminaion. Deails abou he full operaion of he conroller in normal operaion are illusraed in he following paragraphs Digial Frequency Reducion As menioned above, he digial signal processing circui consiss of an up/down couner, a ZC couner and a comparaor. These hree pars are he key o implemen digial frequency reducion wih decreasing load. In addiion, a ringing suppression ime conroller is implemened o avoid mis-riggering by he high frequency oscillaion, when he oupu volage is very low under condiions such as sof sar period or oupu shor circui. Funcionaliy of hese pars is described as in he following Minimum ZC Coun Deerminaion To reduce he swiching frequency difference beween low and high line, minimum ZC coun deerminaion is implemened. Minimum ZC coun is se o if VIN less han V VIN_REF which represens for low line. For high line, minimum ZC coun is se o 3 afer VIN higher han V VIN_REF. There is also a hyseresis V VIN_REF wih cerain blanking ime VIN_REF for sable AC line selecion beween low and high line Up/down couner The up/down couner sores he number of he zero crossing which deermines valley numbers o swich-on he main MOSFET afer demagneizaion of he ransformer. This value is fixed according o he feedback volage, V FB, which conains informaion abou he oupu power. Indeed, in a ypical peak curren mode conrol, a high oupu power resuls in a high feedback volage, and a low oupu power leads o a low feedback volage. Hence, according o V FB, he value in he up/down couner is changed o vary he power Daashee 7 of 25 V 2.0

8 Funcional Descripion MOSFET off-ime according o he oupu power. In he following, he variaion of he up/down couner value according o he feedback volage is explained. The feedback volage V FB is inernally compared wih hree hreshold volages V FB_LHC, V FB_HLC and V FB_R a each clock period of 48 ms. The up/down couner couns hen upward, keep unchanged or coun downward, as shown in 0. Table 3 Operaion of up/down couner V FB up/down couner acion Always lower han V FB_LHC Coun upwards ill n=8/0 Once higher han V F_LHC, bu always lower han V FB_HLC Sop couning, no value changing Once higher han V FB_HLC, bu always lower han V FB_R Coun downwards ill n=/3 2 Once higher han V FB_R Se up/down couner o n=/3 2 The number of zero crossing is limied and herefore, he couner varies among o 8 (for low line) or 3 o 0 (for high line) and any aemp beyond his range is ignored. When V FB exceeds V FB_R volage, he up/down couner is rese o (low line) and 3 (high line) in order o allow he sysem o reac rapidly o a sudden load increase. The up/down couner value is also rese o (low line) and 3 (high line) a he sar-up ime, o ensure an efficien maximum load sar up. Figure 6 shows some examples on how up/down couner is changed according o he feedback volage over ime. The use of wo differen hresholds V FB_LHC and V FB_HLC o coun upward or downward is o preven frequency jiering when he feedback volage is close o he hreshold poin. clock T=48ms clock T=48ms V FB V FB V FB,R V FB,R3 V FB,HLC V FB,HLC V FB,LHC V FB,LHC Up/down couner n n+ n+2 n+3 n+3 n+3 n+2 n+ n Up/down couner n n+ n+2 n+3 n+3 n+3 n+2 n+ n 3 Case Case Case Case Case Case Figure 6 low line Up/down couner operaion High line Zero crossing (ZC couner) In he sysem, he volage from he auxiliary winding is applied o he ZCD pin hrough a RC nework, which provides a ime delay o he volage from he auxiliary winding. Inernally his pin is conneced o a clamping nework, a zero-crossing deecor, an oupu overvolage deecor and a ringing suppression ime conroller. During on-sae of he power swich, a posiive gae drive volage is applied o he ZCD pin due o R ZCD resisor, hence exernal diode D ZC (see Figure ) is added o block he negaive volage from he auxiliary winding. n=8 (for low line) and n=0 (for high line) 2 n= (for low line) and n=3 (for high line) Daashee 8 of 25 V 2.0

9 Funcional Descripion The ZC couner has a minimum value of (for low line) or 3 (for high line) and maximum value of 8 (for low line) or 0 (for high line). Afer he Q (see Figure ) is urned off, every ime when he falling volage ramp of on ZCD pin crosses he V ZCD_CT hreshold, a zero crossing is deeced and ZC couner will increase by. I is rese every ime afer he DRIVER oupu is changed o high. To achieve he swich on a volage valley, he volage from he auxiliary winding is fed o a ime delay nework (he RC nework consiss of R ZC and C ZC as shown in Figure ) before i is applied o he zero-crossing deecor hrough he ZCD pin. The needed ime delay o he main oscillaion signal Δ should be approximaely one fourh of he oscillaion period, T OSC (by ransformer primary inducor and drain-source capacior) minus he propagaion delay from he deeced zero-crossing o he swich-on of he main swich delay, heoreically: Δ = T OSC 4 (2) delay This ime delay should be mached by adjusing he ime consan of he RC nework which is calculaed as: R ZC R ZCD (3) τ d = C ZC. R ZC +R ZCD Ringing suppression ime Afer Q (see Error! Reference source no found.) is urned off, here will be some oscillaion on V DS, which will also appear on he V ZCD. To avoid mis-riggering by such oscillaions o urn on he Q, a ringing suppression imer is implemened. This suppression ime is depended on he volage V ZCD. If he volage V ZCD is lower han he hreshold V ZCD_RS, a longer prese ime ZCD_RS2 is applied. However, if he volage V ZCD is higher han he hreshold, a shorer ime ZCD_RS is se Swich on deerminaion Afer he gae drive goes o low, i canno be changed o high during ring suppression ime. Afer ring suppression ime, he gae drive can be urned on when he ZC couner value is equal o up/down couner value. However, i is also possible ha he oscillaion beween primary inducor and drain-source capacior damps very fas and IC canno deec zero crossings even. In his case, a maximum off ime is implemened. Afer gae drive has been remained off for he period of T OffMax, he gae drive will be urned on again regardless of he ZC couner values and V ZCD. This funcion can effecively preven he swiching frequency from going lower han 20 khz. Oherwise i will cause audible noise Swich off deerminaion In he converer sysem, he primary curren is sensed by an exernal shun resisor, which is conneced beween source erminal of he inernal MOSFET and he common ground. The sensed volage across he shun resisor V CS is applied o an inernal curren measuremen uni, and is oupu volage V is compared wih he feedback volage V FB. Once he volage V exceeds he volage V FB, he oupu flip-flop is rese. As a resul, he main power swich is swiched off. The relaionship beween he V and he V CS is described by (see Figure 3): V = G PWM V CS + V PWM (4) To avoid mis-riggering caused by he volage spike across he shun resisor a he urn on of he main power swich, a leading edge blanking ime, LEB, is applied o he oupu of he comparaor. In oher words, once he gae drive is urned on, he minimum on ime of he gae drive is he leading edge blanking ime. In addiion, here is a maximum on ime, OnMax, limiaion implemened in he IC. Once he gae drive has been in high sae longer han he maximum ON ime, i will be urned off o preven he swiching frequency from going oo low because of long on ime. Daashee 9 of 25 V 2.0

10 Funcional Descripion In addiion, here is a maximum on ime, OnMax, limiaion implemened in he IC. Once he gae drive has been in high sae longer han he maximum on ime, i will be urned off o preven he swiching frequency from going oo low because of long on ime Modulaed gae drive The drive-sage is opimized for EMI consideraion. The swich on speed is slowed down before i reaches he CoolMOS TM urn on hreshold. Tha is a slope conrol of he rising edge a he oupu of driver (see Figure 7). Thus he leading swich spike during urn on is minimized. V GATE (V) V GATE_HIGH yp. = 7ns 5V (ns) Figure 7 Gae rising waveform 3.4 Curren limiaion There is a cycle by cycle curren limiaion realized by he curren limi comparaor o provide over-curren deecion. The source curren of he CoolMOS is sensed via a sense resisor R CS. By means of R CS he source curren is ransformed o a sense volage V CS which is fed ino he pin CS. If he volage V CS exceeds an inernal volage limi, adjused according o he Line volage, he comparaor immediaely urns off he gae drive. When he main bus volage increases, he swich on ime becomes shorer and herefore he operaing frequency is also increased. As a resul, for a consan primary curren limi, he maximum possible oupu power is increased which is beyond he converer design limi. To compensae such effec, boh he inernal peak curren limi circui (V CS) and he ZC coun varies wih he bus volage according o Figure 8. V CS (V) V CS_N, 0.9 Saring ZC = Saring ZC = V VIN_REF V VIN (V) Figure 8 Variaion of he V CS limi volage according o he V IN volage Daashee 0 of 25 V 2.0

11 Funcional Descripion 3.5 Acive Burs Mode wih selecable power level A ligh load condiion, he IC eners Acive Burs Mode operaion o minimize he power consumpion. Deails abou Acive Burs Mode operaion are explained in he following paragraphs. The burs mode enry level can be seleced by changing he differen resisor R Sel a FB pin. There are 2 levels o be seleced wih differen resisor which are argeed for low range of acive burs mode power (Level ) and high range of acive burs mode power (Level 2). The following able shows he conrol logic for he enry and exi level wih he FB volage. Table 4 Two levels enry and exi acive burs mode power Level V FB V CS Enry level Exi level V FB_EBLX V FB_LB V FB > V REF_B V CS_BL = 0.3 V 0.90 V 2.75 V 2 V FB < V REF_B V CS_BL2 = 0.35 V.05 V 2.75 V During IC firs sarup, he inernal Ref GOOD signal is logic low when V CC < 4 V. I will rese he Burs Mode level Deecion lach. When he Burs Mode Level Deecion lach is low and IC is in OFF sae, he IC inernal R FB resisor is disconneced from he FB pin and a curren source I sel is urned on insead. From Vcc=4 V o Vcc on hreshold, he FB pin will sar o charge o a volage level associaed wih R Sel resisor. When Vcc reaches Vcc on hreshold, he FB volage is sensed. The burs mode hresholds are hen chosen according o he FB volage level. The Burs Mode Level Deecion lach is hen se o high. Once he deecion lach is se high, any change of he FB level will no change he hreshold selecion. The curren source I sel is urned off in 2 μs afer V CC reaches V CC on hreshold and he R FB resisor is re-conneced o FB pin (see Figure 9). V dd I sel UVLO S 2 Ref good S R 2μs delay Burs mode deecion lach S R FB FB V CS_BLx V FB _EBL x Selecion Logic Compare logic V REF_B RSel Conrol uni Figure 9 Burs mode deec and adjus 3.5. Enering Acive Burs Mode Operaion For deerminaion of enering Acive Burs Mode operaion, hree condiions apply: he feedback volage is lower han he hreshold of V FB_EBLX he up/down couner is 8 for low line or 0 for high line and he above wo condiions remain afer a cerain blanking ime FB_BEB (20 ms). Once all of hese condiions are fulfilled, he Acive Burs Mode flip-flop is se and he conroller eners Acive Burs Mode operaion. This muli-condiion deerminaion for enering Acive Burs Mode operaion prevens mis-riggering of enering Acive Burs Mode operaion, so ha he conroller eners Acive Burs Mode operaion only when he oupu power is really low during he prese blanking ime. Daashee of 25 V 2.0

12 Funcional Descripion During Acive Burs Mode Operaion Afer enering he Acive Burs Mode he feedback volage rises as V O sars o decrease due o he inacive PWM secion. One comparaor observes he feedback signal if he volage level V FB_BOn is exceeded. In ha case he inernal circui is power up o resar wih swiching. Turn-on of he power MOSFET is riggered by ZC couner wih a fixed value of 8 ZC for low line and 0 ZC for high line. Turn-off is resuled if he volage across he shun resisor a CS pin his he hreshold V CS_BLX. If he oupu load is sill low, he feedback signal decreases as he PWM secion is operaing. When feedback signal reaches he low hreshold V FB_BOff, he inernal circui is rese again and he PWM secion is disabled unil nex ime V FB signal increases beyond he V FB_BOn hreshold. In Acive Burs Mode, he feedback signal is changing like a saw ooh beween V FB_BOff and V FB_BOn (see Figure 0) Leaving Acive Burs Mode Operaion The feedback volage immediaely increases if here is a high load jump. This is observed by a comparaor wih hreshold of V FB_LB. As he curren limi is V CS_BLX (3% or 35%) during Acive Burs Mode, a cerain load is needed so ha feedback volage can exceed V FB_LB. Afer leaving acive burs mode, normal peak curren conrol hrough V FB is re-acivaed. In addiion, he up/down couner will be se o (low line) or 3 (high line) immediaely afer leaving Acive Burs Mode. This is helpful o minimize he oupu volage undershoo. V FB V FB_LB V FB_BOn V FB_BOff Enering Acive Burs Mode Leaving Acive Burs Mode V FB_EBx V CS Time o 8 h /0 h ZC and Blanking ime ( FB_BEB ) V CS_N Curren limi level during Acive Burs Mode V CS_BLx V VCC V VCC_OFF V O Max. Ripple < % Figure 0 Signals in Acive Burs Mode Daashee 2 of 25 V 2.0

13 Funcional Descripion 3.6 Proecion Funcions The ICE5QSAG provides numerous proecion funcions which considerably improve he power supply sysem robusness, safey and reliabiliy. The following able summarizes hese proecion funcions. There are 3 differen kinds of proecion mode; non swich auo resar, auo resar and odd skip auo resar. The deails can refer o he Figure, Figure 2 and Figure 3. Table 5 Proecion funcions Proecion Funcions Normal Mode Burs Mode Proecion Mode Burs ON Burs OFF Line Over Volage Non swich Auo Resar Brownou Non swich Auo Resar V CC Over Volage NA Odd skip Auo Resar V CC Under Volage Auo Resar Over Load NA NA Odd skip Auo Resar Oupu Over Volage NA Odd skip Auo Resar Over Temperaure Non swich Auo Resar CS Shor o GND NA Odd skip Auo Resar 3.6. Line Over Volage The AC Line Over Volage Proecion is deeced by sensing bus capacior volage hrough VIN pin via 2 poenial divider resisors, R l and R l2 (see Figure ). Once V VIN volage is higher han he line over volage hreshold V VIN_LOVP, he conroller eners Line Over Volage Proecion and i releases he proecion mode afer V VIN is lower han V VIN_LOVP Brownou The Brownou proecion is observed by VIN pin similar o line over volage Proecion mehod wih a differen volage hreshold level. When V VIN volage is lower han he brownou hreshold (V VIN_BO), he conroller eners Brownou Proecion and i releases he proecion mode afer V VIN higher han brownin hreshold (V VIN_BI) VCC Ovder Volage or Under Volage During operaion, he V CC volage is coninuously moniored. In case of a V CC Over Volage or Under Volage, he IC is rese and he main power swich is hen kep off. Afer he V CC volage falls below he hreshold V VCC_OFF, he new sar up sequence is acivaed. The V CC capacior is hen charged up. Once he volage exceeds he hreshold V VCC_ON, he IC begins o operae wih a new sof-sar Over Load In case of open conrol loop or oupu Over Load, he feedback volage will be pulled up and exceed V FB_OLP. Afer a blanking ime of FB_OLP_B, he IC eners auo resar mode. The blanking ime here enables he converer o operae for a cerain ime during a sudden load jump. No Applicable Daashee 3 of 25 V 2.0

14 Funcional Descripion Oupu Over Volage During off-ime of he power MOSFET, he volage a he ZCD pin is moniored for Oupu Over Volage deecion. If he volage is higher han he prese hreshold V ZCD_OVP for 0 consecuive pulses, he IC eners Oupu Over Volage Proecion Over Temperaure If he juncion emperaure of conroller chip exceeds T jcon_otp, he IC eners ino Over Temperaure proecion (OTP) Non swich auo resar mode. The conroller implemens wih a 40 C hyseresis. In anoher word, he conroller/ic can only resume from OTP if is juncion emperaure drops 40 C from OTP rigger poin. The over emperaure proecion of he conroller chip shall preven urn-on of he power supply if he componen emperaure is oo high. For appropriae sysem proecion, addiional measures may have o be aken by he designer CS Shor o GND If he volage a he curren sense pin is shored and lower han he prese hreshold V CS_STG wih cerain blanking ime CS_STG_B for 3 consecuive pulses during on-ime of he power MOSFET, he IC eners CS Shor o GND Proecion. Faul deeced Faul released V VCC Sar up and deec a every charging cycle Swiching sar a he following resar cycle V CC_ON V CC_OFF V CS No swiching Figure Non swich Auo Resar Mode Daashee 4 of 25 V 2.0

15 Funcional Descripion Faul deeced Faul released V VCC Sar up and deec a every charging cycle Swiching sar a he following resar cycle V CC_ON V CC_OFF V CS Figure 2 Auo Resar Mode Faul deeced Faul released V VCC No deec Sar up and deec a every even charging cycle No deec Swiching sar a he following even resar cycle V CC_ON V CC_OFF V CS Figure 3 Odd skip Auo Resar Mode Daashee 5 of 25 V 2.0

16 Elecrical Characerisics 4 Elecrical Characerisics Aenion: All volages are measured wih respec o ground (Pin 8). The volage levels are valid if oher raings are no violaed. 4. Absolue Maximum Raings Aenion: Sresses above he maximum values lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Maximum raings are absolue raings; exceeding only one of hese values may cause irreversible damage o he inegraed circui. Sysem design needs o ensure no o exceed he maximum limi. Ta=25 C unless oherwise specified. Table 6 Absolue Maximum Raings Parameer Symbol Limi Values Uni Noe / Tes Min. Max. Condiion VCC Supply Volage V CC V GATE Volage V GATE V SOURCE Volage V SOURCE V FB Volage V FB V ZCD Volage V ZCD V CS Volage V CS V VIN Volage V IN V Maximum DC curren a SOURCE pin Single pulse source curren a SOURCE pin I SOURCE A Limied by T j,max I S_pulse A Pulse widh P=20 µs and limied by T j,max ESD robusness HBM V ESD_HBM V According o ESD robusness CDM V ESD_CDM V EIA/JESD22 Juncion emperaure range T J C Sorage Temperaure T STORE C Thermal Resisance Juncion- Ambien 4.2 Operaing Range R hja - 85 K/W Seup according o he JESD5 sandard Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Table 7 Operaing Range Parameer Symbol Limi Values Uni Remark Min. Max. V VCC Supply Volage V VCC V VCC_OFF V VCC_OVP Juncion Temperaure of conroller T jcon_op -40 T jcon_otp C Max value limied due o OTP of conroller chip Daashee 6 of 25 V 2.0

17 Elecrical Characerisics 4.3 Operaing Condiions Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range T J from 40 C o 25 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 8 V is assumed. Table 8 Operaing Condiions Parameer Symbol Limi Values Uni Noe / Tes Condiion VCC Charge Curren Curren Consumpion, Sarup Curren Curren Consumpion, Normal I VCC_Charge I VCC_Charge2 I VCC_Charge ma ma ma I VCC_Sarup ma V VCC=5 V I VCC_Normal Curren Consumpion, Auo Resar I VCC_AR µa ma V VCC=0 V, R SarUp=50 MΩ and V DRAIN=90 V V VCC=3 V, R SarUp=50 MΩ and V DRAIN=90 V V VCC=5 V, R SarUp=50 MΩ and V DRAIN=90 V I FB=0 A (No gae swiching) Curren Consumpion, Burs Mode I VCC_Burs Mode ma V FB=.8 V VCC Turn-on Threshold Volage V VCC_ON V VCC Turn-off Threshold Volage V VCC_OFF V VCC Shor Circui Proecion Volage V VCC_SCP -..9 V VCC Turn-off blanking VCC_OFF_B µs 4.4 Inernal Volage Reference Table 9 Inernal Volage Reference Parameer Symbol Limi Values Uni Noe / Tes Condiion Inernal Reference Volage V REF V Measured a pin FB I FB=0 4.5 Gae Driver Table 0 Gae Driver Parameer Symbol Limi Values Uni Noe / Tes Condiion Oupu volage a logic low V GATE_LOW V Oupu volage a logic high V GATE_HIGH V Rise Time GATE_RISE ns Cou = nf Fall Time GATE_FALL ns Cou = nf Daashee 7 of 25 V 2.0

18 Elecrical Characerisics 4.6 PWM Secion Table PWM Secion Parameer Symbol Limi Values Uni Noe / Tes Condiion Feedback Pull-Up Resisor R FB 5 20 kω PWM-OP Gain G PWM Offse for Volage Ramp V PWM V Maximum on ime in normal operaion Maximum off ime in normal operaion 4.7 Curren Sense Table 2 Curren Sense OnMax µs OffMax µs Parameer Symbol Limi Values Uni Noe / Tes Condiion Peak curren limiaion in normal operaion V CS_N V Leading Edge Blanking ime CS_LEB ns Peak Curren Limiaion in Acive Burs Mode Level Peak Curren Limiaion in Acive Burs Mode Level 2 V CS_BL V V CS_BL V 4.8 Sof Sar Table 3 Sof Sar Parameer Symbol Limi Values Uni Noe / Tes Condiion Sof-Sar ime SS ms Sof-sar ime sep SS_S ms Inernal regulaion volage a firs sep Inernal regulaion volage sep a sof sar V SS V CS peak volage V SS_S V CS peak volage The parameer is no subjeced o producion es - verified by design/characerizaion Daashee 8 of 25 V 2.0

19 Elecrical Characerisics 4.9 Digial Zero Crossing Table 4 Digial Zero Crossing Parameer Symbol Limi Values Uni Noe / Tes Condiion Zero crossing hreshold volage V ZCD_CT mv Zero crossing Ringing suppression hreshold V ZCD_RS V Minimum ringing suppression ime ZCD_RS µs V ZCD > V ZCD_RS (excep s 3 ms of sof-sar) Maximum ringing suppression ime Threshold o rese Up/Down Couner ZCD_RS µs V ZCD < V ZCD_RS V FB_R V Threshold for downward couning V FB_HLC V Threshold for upward couning V FB_LHC V Couner Time COUNT ms ZCD resisance R ZCD kω Inernal resisor a ZCD pin VIN volage hreshold for line selecion Blanking ime for VIN volage hreshold for line selecion V VIN_REF V VIN_REF ms 4.0 Acive Burs Mode Table 5 Acive Burs Mode Parameer Symbol Limi Values Uni Noe / Tes Condiion Charging curren o selec burs mode Burs mode selecion reference volage Feedback volage for enering Acive Burs Mode for level Feedback volage for enering Acive Burs Mode for level 2 Blanking ime for enering Acive Burs Mode I sel µa V REF_B V V FB_EBL V V FB_EBL V FB_BEB ms Daashee 9 of 25 V 2.0

20 Elecrical Characerisics Feedback volage for leaving Acive Burs Mode V FB_LB V Feedback volage for burs-on V FB_BOn V Feedback volage for burs-off V FB_BOff V 4. Line Over Volage Proecion Table 6 Line OVP Parameer Symbol Limi Values Uni Noe / Tes Condiion Line Over Volage hreshold V VIN_LOVP V Line Over Volage Blanking VIN_LOVP_B µs 4.2 Brownou Proecion Table 7 Brownou Proecion Parameer Symbol Limi Values Uni Noe / Tes Condiion BrownIn hreshold V VIN_BI V BrownIn Blanking VIN_BI_B µs BrownOu hreshold V VIN_BO V BrownOu Blanking VIN_BO_B µs 4.3 VCC Over Volage Proecion Table 8 Vcc Over Volage Proecion Parameer Symbol Limi Values Uni Noe / Tes Condiion VCC Over Volage hreshold V VCC_OVP V VCC Over Volage blanking VCC_OVP_B µs 4.4 Over Load Proecion Table 9 Overload Proecion Parameer Symbol Limi Values Uni Noe / Tes Condiion Over Load Deecion hreshold for OLP proecion a FB pin Over Load Proecion Blanking Time V FB_OLP V FB_OLP_B ms Daashee 20 of 25 V 2.0

21 Elecrical Characerisics 4.5 Oupu Over Volage Proecion Table 20 Oupu OVP Parameer Symbol Limi Values Uni Noe / Tes Condiion Oupu Over Volage hreshold V ZCD_OVP V Oupu Over Volage Blanking Pulse P ZCD_OVP_B pulse Consecuive Pulse 4.6 Thermal Proecion Table 2 Thermal Proecion Parameer Symbol Limi Values Uni Noe / Tes Condiion Over emperaure proecion T jcon_otp C Juncion Over emperaure Hyseresis T jhys_otp C emperaure of he Over emperaure Blanking Time jcon_otp_b µs conroller chip 4.7 CS Shor o GND Proecion Table 22 CS Shor o GND Proecion Parameer Symbol Limi Values Uni Noe / Tes Condiion CS Shor o Gnd Proecion V CS_STG V CS Shor o Gnd Consecuive Trigger P CS_STG cycle CS Shor o Gnd Sample period CS_STG_SAM µs 4.8 Low side MOSFET Table 23 Low side MOSFET Parameer Symbol Limi Values Uni Noe / Tes Condiion Drain Source On-Resisance R DSon Ω Ω Tj = 25 C Tj = 25 C The parameer is no subjeced o producion es - verified by design/characerizaion Daashee 2 of 25 V 2.0

22 Ouline Dimension 5 Ouline Dimension Figure 4 PG-DSO-8 Daashee 22 of 25 V 2.0

23 Marking 6 Marking Figure 5 Marking for ICE5QSAG Daashee 23 of 25 V 2.0

24 Revision hisory Revision hisory Documen version Dae of release Descripion of changes V2.0 Aug 207 Page 7 ~6 Tex conen revised V.2 0 Mar 207 Page, 3 Updaed feaures and descripion Page 6 ~ 4 Typo error Daashee 24 of 25 V 2.0

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