Polytech Montpellier MEA M2 EEA Systèmes Microélectroniques. Advanced Analog IC Design

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1 Polyech Monpellier MEA M EEA Sysèmes Microélecroniques Adanced Analog IC Design Chaper I Inroducion Pascal Noue / noue@lirmm.fr hp:// Ouline of he complee course (four sessions 3 hours each) Fuure of CMOS circuis: FinFET or FDSOI Analog IC Design Flow Adanced specificaions Adanced design echniques 1

2 1.1. Hisory: oday and fuure Today: nm node CMOS bulk wih Na=10 18 aoms/cm 3 Wha is he number of dopan in a minimum size channel? Cubic olume of nm of side cm 3 10 dopans!!! Srong ariabiliy of he hreshold olage Increase of leakage currens "Sudy of Random-Dopan-Flucuaion (RDF) Effecs for he Trigae ulk MOSFET«, IEEE Trans. on Elecron Deices, 56(7): , July Hisory: oday and fuure Soluions for hreshold olage ariabiliy (and I on /I off ) If subsrae doping canno be conrolled hen le s work wih undoped silicon Soluion 1: SOITEC-ST Microelecronics planar Fully-Depleed SOI hp://hohardware.com/news/soitec-announces-new-soi-roadmap--indusry-upake-remains-unclear/

3 1.1. Hisory: oday and fuure Soluions for hreshold olage ariabiliy (and I on /I off ) If subsrae doping canno be conrolled hen le s work wih undoped silicon Soluion : INTE 3D FinFETs or ri-gae ransisors (erkeley, 1999) hp://en.wikipedia.org/wiki/muligae_deice hps://eda360insider.wordpress.com/011/06/19/are-finfes-ineiable-a-0nm- yes-no-maybe -says-professor-chenming-hu/ FD-SOI Technology 6 hp:// 3

4 FinFET Technology 7 hp:// Ouline of he complee course (four sessions 3 hours each) 8 Fuure of CMOS circuis: FinFET or FDSOI Analog IC Design Flow Adanced specificaions Adanced design echniques 4

5 Analog IC Design Flow 9 Specificaions Choice of he archiecure Iniial sizing (1s order models) Analog IC Design Flow 10 Specificaions Choice of he archiecure Iniial sizing (1s order models) MC Simulaions AC small-signal simulaions (gain, fc) DC simulaions (Op. poin) operaing From poin, he Jus designer o be sure poin!!! of sauraions, iew: gain, inpu nex THE bandwidh, sep fabricaion cos noise, $ slew-rae, number (10-100k$) sabiliy, of sages, and oupu (analog ranges, layou is more and exper CMRR, ime AC small-signal MC Simulaions PSRR, (few inpu weeks oupu and o sage, gain, oupu han digial oupu layou) few monhs) dynamic DC simulaions ranges, folded simulaions oupu cascode, resisance resisance, differenial and oupu curren, oupu, curren, erify cell specificaions s sabiliy, gain, echnology spreadings bandwidh, CMRR, (ariabiliy) Applicaion- and mismaches erify sysem-leel PSRR, capaciie load Temperaure Specific and Power specificaions Pos-layou ecs, ayou Simulaions Supplies simulaions (DC, AC, TRAN) Applicaion- Specific Simulaions (DC, TRAN, AC) ayou Pos-layou simulaions 5

6 Ouline of he complee course (four sessions 3 hours each) 11 Fuure of CMOS circuis: FinFET or FDSOI Analog IC Design Flow Adanced specificaions Offse consideraions Common Mode Rejecion Raio Design for low mismaches Noise fundamenals Characerizaion Adanced design echniques Offse consideraions 1 Definiion: inpu offse of a differenial amplifier is he differenial inpu olage ha leads o a zero oupu olage Symmerical power supplies!!! 6

7 Offse consideraions 13 Impac of offse on a simple design: high for low-inpu leels in os iin ou os RF. iin 596m 1k The gain is 60 insead of 100 Offse consideraions 14 Offse is a random phenomenon due o: Technology spreading low frequency ariaions (die o die ; wafer o wafer ; run o run) Mismaches high frequency ariaions (deice o deice) ariabiliy ho opic coering boh preious origins affecing echnology parameers and dimensions generally following a Gaussian disribuion. Propagaion o circui behaior Example: inceriude on sauraion curren µc, W/ and are affeced µc Idsa W gs 7

8 Offse consideraions 15 Gaussian disribuion basics For a large number of idenical deices he disribuion of acual (µc, W/) follows a Gaussian disribuion 0.5% of he alues are more han ±3 away from he aerage alue 6designs are hen he sandard in indusry 99.5% of yield in absence of defecs Run o run (echnology spreading) is much higher han deice o deice (mismaches) MC simulaions Offse consideraions 16 Sandard deiaions are relaed o design!!! Se of equaions can be A found in he lieraure W spreading increases wih he subsrae doping and he ide A 4 N ( m. µm ) hickness spreading decreases wih he area of he ransisor PMOS fabricaed in a N-well exhibis more spreading (N D >>N A ) Oerall, spreading reduces wih modern echnologies (seems o saurae a around 3m.µm) 8

9 Offse consideraions 17 µc mismaches Similar expressions han for µc A µc µc W 0,0056 µm AµC W/ mismaches Example: 100µm/1µm NMOS in a 0,6 µm ech. 1, m 0,% 600m µc µc 0,00056 W / 1 AW / W / W A 0,0µm W / 0,056% W / W / 1 50% more for a PMOS 10 imes less for MOST on he same die (mismaches) % Offse consideraions 18 Random offse in a curren mirror µc W I in IS IS Idsa T 1 T s I Design ips arge area and, long W=100µm ; =1µm ; =0,1 W=10µm ; =10µm ; =1 I S S gs. µc µc gs / W W / 0,4% 56 ppm 0,% 0,04% 56 ppm 0,08% 9

10 We e already sudied 19 Analog Some design ariabiliy flowparameers (wafer o wafer) A A design mus fi specificaions A in he ypical case µc µc A W design mus also fi W / 1 1 specificaions for all AW possible / µc A combinaions m µm of: process W (ariabiliy in process 1. W / W parameers and AµC dimensions), 0,0056µm emperaure A and µmpower W / 0,0 A supply 8m. µm 6 designs Adanced specificaions and ariabiliy Uncerainies i ranslae in a I dsa sandard d deiaion I. µc dsa W /... I µc W / dsa gs Random offse in a simple curren mirror arge ransisors and large Offse consideraions 0 Random offse in a differenial pair wih resisie load and symmerical supply olages od RI gmr Spreading in load resisance I R od R os R I Oher spreading I R. I od os I I dsa dsa dsa os os dsa dsa. µc W / µc W / R R µc µc W / W / 10

11 Offse consideraions 1 u offse can be also sysemaic due o he chosen archiecure, he bias poin, a wrong layou (sysemaic mismach) Mus be fixed by designer!!! Examples Relaed o design (layou) 3 1 R i S ou i ou i in g m Relaed o usage If ds > ds1 ( + 1 ) i ou1 i in g ou ds ds1 R i S ou aboraory work Random offse in a curren mirror Using T 1 and T a minimum size I in IS and I in =7µA, le s record I s =f( s ) T 1 T s e s idenify s0 such ha I s =I in. e s run MC simulaions (process only hen mismach only hen all) and analyze I s =f( s ) and I s ( s0 ). Do he same simulaion for W/ muliplied by en and hen diided by en e s compare he obained for he hree simulaions Conclusions 11

12 aboraory work 3 Fully differenial pair e s simulae a fully differenial pair wih I =14µA and W/=10 using ideal resisors of 00k. One inpu is fixed o 1.65 while he oher one is swep. Using he calculaor funcions compare and cross deermine inpu olage ha leads o o1 = o. Run a MC analysis o deermine ypical offse Do he same analysis for differen W/, real resisors and finally using he preious curren mirror. e s conclude. Connexion sereur inux MEARH14 mearh14.pedagogie-iruel.polyech.uni-monp.fr mkdir AMS035 mkdir = make direcory (dir name can be choosen freely) cd AMS035 cd = change direcory source /sof_eii/cadence/.config_ams410 ams_cds -64 -ech c35b4 -mode ir & will prepare your folder (direcory) o design in AMS C354 echnology Nex runs : ams_cds -64 1

13 Ouline of he complee course (four sessions 3 hours each) 5 Fuure of CMOS circuis: FinFET or FDSOI Analog IC Design Flow Adanced specificaions Offse consideraions Common Mode Rejecion Raio Design for low mismaches Noise fundamenals Characerizaion Adanced design echniques Common Mode Rejecion Raio, CMRR 6 Definiion: CMRR characerizes he abiliy of a differenial amplifier o rejec he common mode MC MC d d d + - s A d d A MC MC CMRR A A d MC CMRR d A d, d A MC, d A 0log A d MC 13

14 Common Mode Rejecion Raio, CMRR 7 Random CMRR in a differenial pair od R I Ad gmr A mc id inc 0 od inc id 0 0 CMRR Impac of spreading in R inc inc /R in he curren source oupu resisance od R A inc od mc R inc 0 id R R g CMRR R m R R Common Mode Rejecion Raio, CMRR 8 Wihou R spreading, inc /(.R ) in each load resisance Impac of spreading in MOST inc I dsa od RI( R ) R R I dsa od R. µc W A mc R µc W inc gmr gmr CMRR A R. µc W mc R µc W 14

15 Random CMRR and offse rade-off 9 Design for low offse and high CMRR os R R µc µc os W W CMRR g CMRR m R R R I g mr. µc µc R W W The lower he offse, he higher he CMRR!!! 1. Opimize for low offse ow (0,1), large ransisors, mached resisors reduce spreading and curren mismach. Opimize for large CMRR High g m (I ) & R Sysemaic CMRR 30 CMRR can be also sysemaic: example wih a differenial pair wih referenced oupu Curren source oupu resisance: R Common Mode MC dd change bias curren MC /R MC /R does no equally share beween T 1 and T Small-signal analysis o calculae T 3 I d1 T 4 I d4 I d induced oupu olage + - T 1 T ou CMRR g m g m3 r ds1 R I bias 15