High Gain Opamp based Comparator Design for Sigma Delta Modulator

Transcription

1 Indian Journal of Science Technology, Vol 9(9), DOI: /ijs/016/v9i9/90858, Augus 016 ISSN (Prin) : ISSN (Online) : High Gain Opamp based Comparaor Design for Sigma Dela Modulaor A. Naveena Venancias *, K. Hariharan R. Parameshwaran School of Compuing, SASTRA Universiy, Thanjavur , Tamil Nadu, India; naveenavenancias@gmail.com, harikalyan8@7ic.sasra.edu, paramu3@gmail.com Absrac Sigma dela ADC is mainly used in resoluion based applicaion. Bu he gain of he sigma dela modulaor is low. The main objecive of he paper is o design he comparaor wih high gain. Comparaor wih low gain canno drive he load effecively hrough he enire circui. This paper was designed simulaed using 180 nm process echnology (GPDK 180 nm library) in CADENCE Viruoso Analog Design Environmen. In sigma dela ADC, each block should drive he load effecively o he enire circui. So ha he oupu will come accuraely delay will be less. Based on ha concep, need o design he comparaor ha can be used in sigma dela ADC. In his poin of view, some comparaors are analysed. In his paper, analyse he performance of regeneraive comparaors op-amp based comparaors. And find which will efficien comparaor for using a sigma dela modulaor. Dynamic comparaor, double ail comparaor, modified double ail comparaor are analysed. The gain of hese operaional amplifiers are low. So high gain based operaional amplifier should be designed. For ha, firs one op-amp was designed which has 84 db gain. Using his opamp, one comparaor was designed. This comparaor has high gain. So i can be used for sigma dela ADC for drive he load. And also i mees cerain oher consrains like speed moderae power. Keywords: CMOS, Opamp Based Comparaor, Regeneraive Comparaors, Sigma Dela ADC, UDSM CMOS Technology 1. Inroducion Comparaor is used o compare wo inpus give larger one as an oupu. The inpus may be volage or curren. Basic comparaor has wo inpus ha are analog signals one oupu ha is digial signal. Comparaor is one of he basic block in Analog o Digial Converers (ADC). According o he purpose of he ADC differen ypes of comparaors are used. Some comparaors designed for reduced power dissipaion. Some may be regarding speed. Normally ADCs need high speed, low power low area comparaors. High speed comparaors which ac in UDSM CMOS echnologies undergo low volages paricularly while considering hreshold volages 1. I may no been mouned a he similar as he supply volages of he curren CMOS mehods. Challenging facor is designing a high speed comparaor wih low supply volage. I akes large area high power.. Clock Regeneraive Comparaors Clock regeneraive comparaors are widely used in high speed ADCs because hey have posiive feedback in regeneraive laches o ake fas decisions. Comprehensive analyses are used o analyse he performance of differen comparaors from differen aspecs like kick back noise noise offse. In his paper we analyse he performance of convenional dynamic comparaor, convenional double ail comparaor, modified double ail comparaor opamp based comparaor..1 Dynamic Comparaor Figure 1 displays he schemaic view of dynamic comparaor ha is generally used in ADC. The operaion of his comparaor follows: In he rese sage, he clock is zero ransisor M ail is off rese ransisors M 7, * Auhor for correspondence

2 High Gain Opamp based Comparaor Design for Sigma Dela Modulaor makes he oupu node Ou n, Ou p o VDD 3. During comparison phase, he clock is equal o VDD, ransisors M 7, ge off M ail ges on. A his phase oupu volages sars precharge o VDD. I sars discharging depending upon he inpu volage. If V inp > V inn, hen Posiive side of oupu ges discharged faser han anoher side. Because Oup falls down o VDD V hp before of anoher side. Here Ou p ges discharged by M drain curren. And Oun discharged by M 1 drain curren. Advanage of his comparaor is high inpu impedance, no saic power rail o rail swing. In order o minimize he offse volage, inpu ransisors will design. The disadvanage is, i needs more volage for mainaining correc delay period due o sacked ransisors. And anoher drawback is, i has only one pah for curren hrough ail ransisor M ail. I is used for differenial amplifier, lach. Though small ail curren is used o reain he differenial pair in paheic reversal achieve exended inegraion pause, large ail is needed for fas regeneraion in he lach. Mosly M ail operaes in riode sae ail curren res on inpu common ype volage. I is no advanageous for reinforcemen operaion. Figure 1. Schemaic view of dynamic comparaor. The ransisor M 5 will urn on iniiaing regeneraive lach because of back o back inverors ha is M 3, M 4, M 5, M 6. So he Oun sar precharge o VDD Ou p sar discharging owards ground 4. If V INP < V INN, hen acion is reverse. This comparaor has wo ime delays, hey are 0 lach. The 0 delay indicaes he discharging capaciy of C L upo M 5 or M 6 ges on. Tha is unil p-channel ransisor urns on. If V INP >V INN, hen Ou p discharge faser. Because of I d of ransisor M. This is driven by he ransisor M 1 wih very low curren. The delay, 0 is represened as: C V C V 0 I I L hp L hp ail The delay, lach is a laching delay beween he cross coupled inverers. The volage swing is he difference beween he iniial oupu volage falling oupu. In ha half supply volage is consider as hreshold volage. The lach delay is represened as: lach L D V ö ou L VDD /ö =.ln.ln g = ç V g V è D ø èç D ø m, eff 0 m, eff 0. Double-Tail Dynamic Comparaor Figure displays he schemaic view of convenional double ail comparaor. I has less sacking so ha i can operae a low volage han he dynamic comparaor. When he clock is zero, ransisors M ail1 M ail are in off condiion. And he ransisors M 3 precharge he nodes f n, f p o VDD M R1, M R ges discharge owards he ground [1]. When clock is a VDD, ransisors M ail1 M ail are in on condiion. And he ransisors M 3 urn off f n, f p nodes sar o discharge. I discharged in he rae defined by C fn (p) V fn (p) will buildup. The ransisors M R1, M R forms inermediae sage V fn (p) passes o he cross ied inverers i offers worhy proecing beween inpu node yield node. I reduces he kickback noise. I also has wo ypes of delay, 0 lach. 0 represened as capaciive charging of C Lou, ha is beween he saring of lach regeneraion urning on of firs n-channel ransisor, ha is urning on of M 9 or M 10. This is achieved from, 0 V C V C =» I I Thn Lou Thn Lou B1 ail Here I B1 is drain curren of ransisor M 9. And his drain curren is equals o half of he I ail. Here volage a he posiive node is higher han he volage a he negaive node. When he M 9 urns on, he oupu node ha is Ou n sared discharging o ground. And fron p-channel ransisor also urns on. I makes Ou p, charging owards VDD. The regeneraion ime is obain same like dynamic comparaor. A ime 0, he volage difference of oupu is achieved using, æ I ö D V0 = V - ç ø B Thn 1 çè IB1 Vol 9 (9) Augus Indian Journal of Science Technology

3 A. Naveena Venancias, K. Hariharan R. Parameshwaran Figure. Schemaic view of convenional double ail comparaor. From his, wo main facors are obained. They are: A ime 0, difference beween he volages a oupu has high effecs on lach primary differenial producion volage also in lach inerval. So by increasing his volage difference helps o decrease he delay of he comparaor. In his comparaor, ransiional sage ransisor does no have any effec on ransconducance. So hese ransisors are cu off a final sage. Because of nodes fn fp discharge owards ground, ransisors don have effec on ransconducance. A he rese phase, i needs o precharge from he boom level, i.e. i needs o charge from ground o power supply. So i akes more power consumpion..3 Modified Double Tail Dynamic Comparaor: Figure 3 displays he schemaic view of modified double ail dynamic comparaor. The dynamic comparaor has beer performance a low volage. So using dynamic comparaor archiecure, new archiecure will design. I increases he speed of lach regeneraion by increase V fn/fp. For his reason, wo ransisors are added wih archiecure. Tha are conrol ransisors, namely M c1 M c. These ransisors are cross coupled parallel o he ransisors M 3 /M 4. When CLK = 0, M ail1 is in off sage M ail also in off condiion. I avoids saic power dissipaion. The ransisors M 3 make he nodes f n o charge owards VDD. The ransisors a inermediae sage, rese all lach oupus as ground 5. Figure 3. Schemaic view of modified double ail dynamic comparaor. For he period of decision making phase, CLK is VDD. And ransisors M ail1, M ail are in on condiion. And M 3 are in off condiion. A saring of decision making phase, M c1 M c are a off condiion because, he nodes f n are a VDD. So as per he inpu volages, hese nodes are drop a differen raes. If V INP > V INN, hen f n drops faser. Because M provides high curren han M 1. Whereas f n falling, equivalen conrol ransisor, i.e. M c1 urns on. And node f p reurn o VDD. A he ime M c a off condiion f n fully discharged. When ime increases, difference of f n f p also increases as exponenial. Tha reduces he regeneraion ime of lach. There is one effeciveness in his archiecure. Tha is if any one of he conrol ransisors ges on, he curren drain from power supply o ground hrough he ransisors M c1, M 1, M ail1. i.e. hrough he ail ransisors inpu ransisors. So i akes saic power consumpion 6. Using nmos swiches below he inpu ransisors, his issue is overcome. Here M sw1, M sw are he nmos swiches. A he saring of his phase, nodes f n have been precharged o VDD. So boh swiches are closed hose nodes sars discharging wih differen raes. When he comparaor idenifies ha any one of he node discharging faser, hen conrol ransisors increase he difference beween he volages. If f p is precharged o VDD, hen f n discharged fully. So charging pah a f p will be open. I avoids curren drained from power supply. Bu anoher swich which is conneced o f n will close o permi he discharge in his node. Conrol ransisors operaion similar o he lach operaion. Modified double ail comparaor increases speed by affecing wo facors. They are, when ime is a 0 i Vol 9 (9) Augus Indian Journal of Science Technology 3

4 High Gain Opamp based Comparaor Design for Sigma Dela Modulaor increases he difference beween he volages. And second one is, i increases he lach ransconducance..3.1 Effecof Enhancing V 0 The delay, 0 is a ime akes ill he main nmos ransisor of back-o-back inverers goes on. I decreases one of he oupus sars regeneraion. A 0, volage difference of lach oupu has effec on lach regeneraion ime. Oupu volage is inversely proporional o he regeneraion ime. If V 0 high, hen regeneraion ime is less. æg. ö gmr1, D Vin gm 1, m, eff 1 0 D V0 = 4 VThn VT hp exp Iail I ail1 ç CL, f n( p).3. Enhancing Lach Operaive Transconducance In his comparaor, a saring sage of decision making phase, oupu nodes of firs sage will charge o VDD. Tha makes inermediae sage urns on. So ha lach ransconducance is increased. Tha means i reinforced he posiive feedback. Lou ln VDD ö lach = g + g ç V èd ø m, eff mr1, Opamp Based Comparaor In sigma dela ADC, he oupus should be drive hrough all he blocks. So i needs high gain. Based on his requiremen, opamp is designed ha will be used in comparaor 7. Consider he specificaion for required opamp ha is specially used in sigma dela modulaor In wo sage opamp, firs sage is differenial amplifier second sage is cascade amplifier. Curren mirror circui also presen in he archiecure. The arge gain is 75 db. CMR raio is minimum 0.8 V o maximum 1.6 V. Table 1 shows he specificaions of opamp. Table 1. Specificaions of opamp Specificaions Values DC Gain 75Db Gain Bwidh 30MHz Phase Margin 60 0 Slew rae 0V/µsec ICMR(+) 1.6V ICMR(-) 0.8V VDD 1.8V è ø Figure 4. Schemaic view of wo sage opamp. Figure 4 displays he schemaic view of wo sage opamp design. By modifying W/L raio will affec he ransconducance of ransisors. Thus i will help o increase he gain of he design. W/L raios of hese ransisors will calculae using some conceps. W/L raio of ransisor M 1, M will be achieved by: æw ö ( g ) m1 ç = è L ø m C 1, n ox *15 Here gm1 is ransconducance of ransisor M 1. I is represened as: g m1 = GBW * C * π Here GBW means Gain Bwidh. Consider ha as a 30 MHz. likewise every ransisors W/L raio should be find as per he calculaion. Some of he formulas used o calculae he W/L raios of various ransisors is shown below: (W/L) =I / (µ C )*[VDD-(ICMR+)-V +V ] 3, 4 5 p ox T3 T1min (W/L) 5 = I 5 / (µ n C ox (Vds 5sa ) ) (W/L) 6 = (g m6 /g m4 ) (W/L) 4 (W L) 7 = (I 7 I 5 ) (W L) 5 Table. W/L raios of ransisors Transisor Calculaed W/L raio W/L raio for increasing gain M 1, M 6 1µ/µ M 3, M µ/0.5µ M 5, 1 6µ/0.5µ M µ/µ M µ/1µ 4 Vol 9 (9) Augus Indian Journal of Science Technology

5 A. Naveena Venancias, K. Hariharan R. Parameshwaran Table shows he W/L values of ransisors. They are, M 1 = M = 6, M 3 = M 4 = 14, M 5 = = 1, M 6 = 174, M 7 = 75. If we increase he lengh, hen ransconducance of he ransisor will increase. So increase he lengh also achieve he obained value. Using his value he opamp is designed. And i reaches he gain value as 84 db. Figure 5. Schemaic view of opamp based comparaor. Using his opamp design, comparaor is designed. The schemaic diagram of opamp based comparaor is shown in Figure 5. This design me he funcionaliy of he basic comparaor. If he inpu volage is greaer han he reference volage i.e. hreshold volage i gives he oupu as high or 1. If he inpu volage is lesser han he reference volage hen i gives he oupu as low or 0. The oupu of he opamp based comparaor is shown in Figure 6. ail comparaor, modified double ail comparaor opamp based comparaor was performed. Among his, found ha opamp based comparaor is mos suiable one for sigma dela ADC. In fuure, using his comparaor can able o design a sigma dela modulaor. 5. References 1. Mesgarani A, Alam MN, Nelson FZ, Ay SU. Supply boosing echnique for designing very low-volage mixed-signal circuis in sard CMOS. Proc. IEEE In Midwes Symp Circuis Sys Dig Tech Papers; 010 Aug. p Nuzzo P, Bernardinis FD, Terreni P, Van der Plas G. Noise analysis of regeneraive comparaors for reconfigurable ADC archiecures. IEEE Trans Circuis Sys I Reg Papers. 008 Jul; 55(6): Figueiredo PM, Vial JC. Kickback noise reducion echnique for CMOS lached comaparors. IEEE Trans Circuis Sys II Exp Briefs. 006 Jul; 53(7): Babayan-Mashhadi S, Lofi R. An offse cancellaion echnique for comparaors using body- volage rimming. In J Analog Ineger. Circuis Signal Process. 01 Dec; 73(3): Babayan-Mashhadi S, Lofi R. Analysis design of a low-volage low-power double-ail comparaor. IEEE Transacions on Very Large Scale Inegraion (VLSI) sysems. 014 Feb; (): Tripahy S, Mal SK, Paro BS, Omprakash LB. Low power, High speed 8-bi magniude comparaor in 45 nm echnology for signal processing applicaion. Indian Journal of Science Technology. 016 Apr; 9(13): Prabhakaran G, Kannan V. Design analysis of high gain, low power low volage a-si TFT based operaional amplifier. Indian Journal of Science Technology. 015 Jul; 8(16): Ay SU. A sub-1 vol 10-bi supply boosed SAR ADC design in sard CMOS. In J Analog Ineger. Circuis Signal Process. 011 Feb; 66(): Goll B, Zimmermann H. A comparaor wih reduced delay ime in 65-nm CMOS for supply volages down o IEEE Trans Circuis Sys II Exp Briefs. 009 Nov; 56(11): Goll B, Zimmermann H. Low-power 600 MHz comparaor for 0.5 V supply volage in 0.1 μm CMOS. IEEE Elecron Le. 007 Mar; 43(7): Figure 6. Oupu of opamp based comparaor. 4. Conclusion Fuure Work In his paper, comparison of dynamic comparaor, double Vol 9 (9) Augus Indian Journal of Science Technology 5