Simulation Series Termination

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1 ESE370: Circui-Level Modeling, Design, and Opimizaion for Digial Sysems Day 35: December 5, 2012 Transmission Lines Implicaions 1 Transmission Line Agenda Where arise? General wire formulaion Lossless Transmission Line See in acion in lab Impedance End of Transmission Line? Terminaion Implicaions Discuss Lossy 2 Transmission Line Daa ravels as waves Line has Impedance May reflec a end of line w = 1 LC = c 0 µ r = L C Series Terminaion Wha happens here? V 0 i = V r V i 2R = V 3 4 Simulaion Series Terminaion 5 R series = Iniial volage divider Half volage pulse down line End of line open circui sees single ransiion o full volage Reflecion reurns o source and sees erminaion R series = No furher reflecions 6 1

2 Terminaion Cases CMOS Driver / Receiver Parallel a Sink Series a Source Driver: Wha does a CMOS driver look like a he source? I d,sa 45nm Receiver: Wha does a CMOS inverer look like a he sink? 7 8 Coaxial Cable Some Transmission Lines Characerisics arise form heir geomery 9 Inner core conducor: radius r Insulaor: ou o radius R Ouer core shield (ground) L = µ 2π ln R r RG-58 = 50Ω neworking, lab (RG-59 = 75Ω video) = 1 2π µ ε ln R r 10 Prined Circui Board Prined Circui Board Sripline Trace beween planes w b Microsrip line Trace over single supply plane ε 0 w h = 1 4 µ ln 1+W b ε b + W b = 1 2π µ ( )ε 0 ln 4h 0.536W

Twised Pair Terminaion Cases Caegory 5 eherne cable Parallel a Sink 100Ω V=0.64c0 Series a Source Source: hp://en.

14 Example Pipeline Bis 25meer caegory-5e cable (100Ω, 0.

a sink Can sick new bis ono wire Time o send daa from one end o he oher? Time beween bis a 250Mb/s? Bis in he cable?

3 Twised Pair Terminaion Cases Caegory 5 eherne cable Parallel a Sink 100Ω V=0.64c0 Series a Source Source: hp://en.wikipedia.org/wiki/file:ca_5.jpg 13 Eiher: desinaion sees source volage afer delay. 14 Example Pipeline Bis 25meer caegory-5e cable (100Ω, 0.64c) Supporing 1Gb/s eherne 4 pairs a 250Mb/s For properly erminaed ransmission line Do no need o wai for bis o arrive a sink Can sick new bis ono wire Time o send daa from one end o he oher? Time beween bis a 250Mb/s? Bis in he cable? Eye Diagrams Limis o Bi Pipelining Wach bis over line on scope Look a disorion open eye clean place o sample Wha limis? (why only 250Mb/s) Consisen iming of ransiions Well defined high/low volage levels Riseime/disorion Clocking hp://en.wikipedia.org/wiki/file:on-off_keying_eye_diagram.svg Skew Jier hp://focus.i.com/analog/docs/genconen.sp?familyid=361&genconenid=41762&dcmp=esd_soluions&hqs=oher+ot+esd For bus Wire lengh differences beween lines

Bad eye Terminaion / Mismach Wires do look like hese ransmission lines We are erminaing hem in some way when we connec o chip (gae) Need o be deliberae abou how erminae, if we care abou high

Branches Connecors Board-o-cable Cable-o-cable hp://www.fpga4fun.com/hands-on_flashy.hml Impedance Change Wha happens if here is an impedance change in he wire?

4 Bad eye Terminaion / Mismach Wires do look like hese ransmission lines We are erminaing hem in some way when we connec o chip (gae) Need o be deliberae abou how erminae, if we care abou high performance hp://archive.chipcener.com/knowledge_ceners/asic/odays_feaure/showaricle.jhml?aricleid= Where Mismach? Vias Wire corners? Branches Connecors Board-o-cable Cable-o-cable hp:// Impedance Change Wha happens if here is an impedance change in he wire? =75Ω, Z 1 =50Ω Wha reflecions and ransmission do we ge? hp://wiki.alium.com/display/adoh/an+overview+of+elecronic+produc+developmen+in+alium+designer A juncion: Reflecs =75, Z 1 =50 V r =(50-75)/(50+75)V i Transmis V =(100/(50+75))V i V 0 2R i = V r V i = V 23 Impedance Change =75, Z 1 =

5 Lossy Transmission Line Lossy Transmission Line How do addiion of R s change? Concreely, discreely hink abou R=0.2Ω every meer on =100Ω wha does each R do? R s cause signal aenuaion (loss) Volage divider R Reduced signal swing a sink Limis lengh of ransmission line before need o resore signal Wha happens a branch? Branch Transmission line sees wo in parallel Looks like / A juncion: Reflecs =50, Z 1 =25 V r =(25-50)/(25+50)V i Transmis End of Branch Wha happens a end? If ends in mached, parallel erminaion No furher reflecions V =(50/(25+50))V i V 0 2R i = V r V i = V

6 Branch Simulaion Branch wih Open Circui? Wha happens if branch open circui? Branch wih Open Circui Open Branch Simulaion Reflecs a end of open-circui sub Reflecion reurns o branch and encouners branch again Send ransmission pulse o boh Source and oher branch Sink sees original pulse as muliple smaller pulses spread ou over ime Open Branch Simulaion Bus hp://en.wikipedia.org/wiki/file:dimms.jpg Common o have many modules on a bus E.g. PCI slos DIMM slos for memory High speed bus lines are rans. lines

7 Muli-drop Bus Ideal Open circui, no load Muli-Drop Bus Impac of capaciive load (sub) a drop? If igh/regular enough, change Z of line = L C Muli-Drop Bus Transmission Line Noise Long wire sub? Looks like branch may produce reflecions Frequency limis Imperfec erminaion Mismached segmens/juncions/vias/ connecors Loss due o resisance in line Limis lengh Transmission lines high-speed Idea high hroughpu long-disance signaling Terminaion Signal qualiy V r = V 0 i R + w = 1 LC = c 0 µ r = L C 41 Admin HW7 due Thursday Las lecure Friday Final following Friday (12/14) 2011 final available o pracice 2010 final up wih soluions Good ransmission line problem Problem 2 precharge logic (skipped his erm) Ok crossalk problem, memory problem Review by Udi on Wed. 12/

Transmission Lines. Transmission Lines :: Topics. Introduction Wave Propagation Termination Reflections Summary. Introduction.

Transmission Lines. Transmission Lines :: Topics. Introduction Wave Propagation Termination Reflections Summary. Introduction. Transmission Lines Digial Design and Compuer Archiecure David Money Harris and Sarah L. Harris Transmission Lines :: Topics Inroducion Wave Propagaion Terminaion Reflecions Summary TL- TL- Inroducion