Design Considerations for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
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1 Applicaion Repor SCAA054A January 2002 Revised November 2005 Dung Nguyen and Kal Musafa Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL ABSTRACT This applicaion is a general guide for using Texas Insrumens CDCV857/CDCV857A/CDCV855 double daa rae (DDR) clock driver. This repor presens mehods for using he device efficienly along wih resuls of evaluaion on device performance. In addiion, several mehods of erminaing oupu signals and layou recommendaion are provided for differen applicaions. HPA/CDC Conens 1 Inroducion Definiions of Imporan Parameers Period Jier Half-Period Jier Cycle-o-Cycle Jier Saic Phase Offse Dynamic Phase Offse Oupu Skew Tesing CDCV857/CDCV857A/CDCV Tesing Equipmen Tesing Circui Diagram Tesing Procedure Measuring Jier Recommended Layou How o Choose Bypass Capacior Values Preven Noise Translaing From Clock Driver o he Main PCB DDR Terminaion Zero-Delay Tuning References
2 Figures Figure 1. Period Jier...3 Figure 2. Half-Period Jier...4 Figure 3. Cycle-o-Cycle Jier...4 Figure 4. Saic Phase Offse...5 Figure 5. Dynamic Phase Offse...5 Figure 6. Oupu Skew...6 Figure 7. Tesing Circui...7 Figure 8. M1 Window for Jier Measuremen...8 Figure 9. M1 Windows for Selecing O Scope Channels o Measure Jier...9 Figure 10. M1 Window for Delay Measuremen...10 Figure 11. Selecing Channels o Measure Delay in M Figure 12. CDCV857/CDCV857A/CDCV855 Filer Circui...11 Figure 13. CDCV857/CDCV857A/CDCV855 Alernae Filer Circui...12 Figure 14. CDCV857/CDCV857A/CDCV855 in DDR Regiser DIMM...14 Figure 15. Using CDCV857/CDCV857A/CDCV855 for Single-Ended Oupus...15 Figure 16. Using CDCV857/CDCV857A/CDCV855 as a Single-Ended Inpu...16 Figure 17. Normalized Delay From Y0/Y0# o CLK/CLK# as a Funcion of Feedback Capaciance (Cfb) Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
3 1 Inroducion The CDCV857/CDCV857A/CDCV855 is a high performance, low-skew, low-jier phase-lock loop clock driver. I akes one pair of differenial inpu signal and fans ou o 10 pairs of differenial oupu wih low skew and low jier. The CDCV855 is similar o he PLL of he CDCV857 wih four oupus. The feedback signals (FBOUT/FBOUT#) are required o exernally connec o FBIN/FBIN# in order for he PLL o funcion. The CDCV857/CDCV857A/CDCV855 uses he PLL o precisely align boh phase and frequency of FBIN/FBIN# o inpu signal (CLK/CLK#). Delay from CLK/CLK# o oupus FBOUT/FBOUT# or Yn/Yn# can be adjused o zero by changing he delay pah from FBOUT/FBOUT# o FBIN/FBIN#. 2 Definiions of Imporan Parameers 2.1 Period Jier Period jier is he maximum deviaion of measured clock period wih respec o ideal clock period over a large number of cycles. In DDR applicaion, period jier is he maximum deviaion of measured clock period wih respec o he average clock period measured over a large number of cycles. Yx, FBOUT Yx, FBOUT Yx, FBOUT Yx, FBOUT cycle n 1 f O ji (per) = cycle n 1 fo Figure 1. Period Jier Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 3
4 2.2 Half-Period Jier Half-period jier is he maximum deviaion of every crossing poin measured on clock waveforms wih respec o half of ideal clock period over a large number of cycles. In he DDR applicaion, half period jier is he maximum deviaion of every crossing poins measured on clock waveforms wih respec o he average of crossing poins measured on clocked waveforms over a large number of cycles. Yx, FBOUT Yx, FBOUT half period n half period n+1 1 f O ji(hper) = half period n 1 2 x fo Figure 2. Half-Period Jier 2.3 Cycle-o-Cycle Jier Cycle-o-cycle jier is he difference in he period of successive cycles of a coninuous clock pulse. Yx, FBOUT Yx, FBOUT cycle n cycle n+1 ji(cc) = cycle n - cycle n+1 Figure 3. Cycle-o-Cycle Jier 4 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
5 2.4 Saic Phase Offse Saic phase offse is he difference beween he averaged phase of he inpu clock and he averaged phase of he FBIN signal. CK CK FBIN FBIN ( ) n ( ) n + 1 N = N 1 ( ) n = ( ) N (N is a large number of samples) Figure 4. Saic Phase Offse 2.5 Dynamic Phase Offse Dynamic phase offse is he maximum phase deviaion of he FBIN signals from he saic phase offse. CK CK FBIN FBIN ( ) ( ) d( ) d( ) Figure 5. Dynamic Phase Offse Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 5
6 2.6 Oupu Skew Oupu skew is he skew beween any oupus on a single device when he oupus have idenical loads and are swiching in he same direcion. Yx Yx Yx, FBOUT Yx, FBOUT sk(o) Figure 6. Oupu Skew 3 Tesing CDCV857/CDCV857A/CDCV855 TI s es board and esing mehodology have been chosen as a sandard ool o evaluae DDR clock for he indusry. Wih TI s esing mehodology, users can easily evaluae CDCV857/CDCV857A/CDCV855 accuraely before puing he device in he sysem. Following is he required equipmen, esing block diagram and esing procedure for evaluaing CDCV857/CDCV857A/CDCV Tesing Equipmen 1. Tekronix scope TDS694C or equivalen 2. M1 sysem 3. DC power supply 4. Funcion generaor HP8133A or Tekronix HFS9003 or equivalen 6 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
7 3.2 Tesing Circui Diagram Circui Load for CDCV850 on Sysem V DD CDCV857 / CDCV Ω 14 pf GND 120 Ω 60 Ω GND 14 pf GND V DD /2 Equivalen Circui for Lab Tes CDCV857 / CDCV pf 60 Ω -V DD /2 10 Ω 50 Ω SCOPE 60 Ω 10 Ω 50 Ω 50 Ω V TT GBIP Cable PC Wih M1 Sofware 50 Ω -V DD /2 14 pf V TT Noe: V = GND TT -V DD /2 Figure 7. Tesing Circui 3.3 Tesing Procedure Measuring Jier Afer connecing he board as shown in Figure 7, open he M1 sofware from he PC. Selec he radio buon as shown in Figure 8 for measuring jier. Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 7
8 Figure 8. M1 Window for Jier Measuremen Selec OK afer he selecion has been made. Anoher window will be opened afer OK has been seleced. If Y and Y# are conneced o channel 1 and channel 2 of he oscilloscope, he radio buons on M1 display will be seleced (+) for channel 1 and (-) for channel 2 and click OK as shown in Figure 9. To measure jier, selec conrol run single sho (or coninuous). Single sho akes only one acquisiion while coninuous akes acquisiions coninuously. Period jier is displayed in min and max places, cycle-cycle jier is displayed in Lg Disp+ and Lg Disp-, and peak-peak jier is shown in peak-peak. To measure saic and dynamic phase offses, connec CLK and CLK# o channel 1 and 2 and connec FBIN and FBIN# o channel 3 and 4 respecively. On he firs M1 window, selec he Delay radio buon as shown in Figure 10 and hen click OK. When anoher window appears, selec Delay from channel 1 and 2 o channel 3 and 4 as shown in Figure 11. Taking measuremen acquisiions in single sho (or coninuous) is he same as aking measuremen on jier. The saic phase offse shows in Mean. Dynamic phase offse is he difference from max and min o he mean value. 8 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
9 Figure 9. M1 Windows for Selecing O Scope Channels o Measure Jier To measure oupu skew, connec one pair of oupus o channel one and wo and he oher pair o channel 3 and 4. The measuremen procedure is he same as measuring phase offse. The oupu skew is shown in he Mean value. Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 9
10 Figure 10. M1 Window for Delay Measuremen Figure 11. Selecing Channels o Measure Delay in M1 10 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
11 4 Recommended Layou SCAA054 Avoid making vias if possible o reduce signal reflecion due o disconinuiy caused by vias. Trace lenghs of clock signal should be mached and each oupu should have equal load o minimize oupu skew. Impedance on clock signals should be well-conrolled o eliminae signal reflecion and oupu skew. I is recommended o erminae he clock signals differenially a he end of he ransmission line. Use a leas one bypass capacior of 0.1 µf for each VDDQ pin. The capacior is placed as closed o he device pin as possible. I is recommended o use a high-qualiy, surface-moun, low-inducance, and low-esr capacior. A surface moun capacior in size of 0603 and ypes of mica or monolihic, ceramic are recommended. If possible, isolae he analog power plane (AVDD) from he digial power hrough a ferrie bead. Figure 12 and Figure 13 are wo recommended circuis for filering power. Figure 12 is recommended where here are no real esae consrains, while Figure 13 is he choice where here is limied board space. Board VCC For Each VDD Pin Ferrie Bead To Analog VDD Pin uf 0.1 uf 47 uf 0.01 uf 0.1 uf GND AGND Pin 17 Figure 12. CDCV857/CDCV857A/CDCV855 Filer Circui Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 11
12 Board VCC For Each VDD Pin Ferrie Bead To Analog VDD Pin uf 10 uf 0.01 uf 0.1 uf GND AGND Pin 17 Figure 13. CDCV857/CDCV857A/CDCV855 Alernae Filer Circui 4.1 How o Choose Bypass Capacior Values Figure 12 and Figure 13 are common circuis for power filering. However, choosing efficien values for bypass capaciors requires a lile mah analysis. In a sysem where here are many gaes swiching simulaneously, he dc volage may flucuae producing ac ripple volage or noise componens. If he ripple volage is oo high, i renders he circui nonfuncional. The main funcion of bypass capaciors is o dampen his ac ripple componen or noise. One funcion of a bypass capacior conneced beween VDD and GND is o allow he ac ripple componen of VDD o pass hrough o ground. Anoher funcion is o help compensae for volage droop caused by large I CC ransien when muliple oupus swich simulaneously. Assume he maximum sep change in supply curren is I, he maximum amoun supply noise ha CDCV857/CDCV857A/CDCV855 can olerae is V, and hen he maximum common-pad (beween Power and GND) impedance ha CDCV857/CDCV857A/CDCV855 can olerae is: X max = V I Assume all drivers on he board swich a he same frequency, hen: (1) V I = NC (2) where C is he load capaciance on each driver, N is he number of drivers in he sysem (number of oupus), and is he rise ime from 10% o 90%. 12 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
13 Assume he power supply has inducance of L PSW, hen he circui needs bypass capaciors if he swiching frequency is above F PSW. Where F PSW is calculaed using he following formula. F PSW X max = 2 ΠL PSW (3) The capaciance ha has impedance X MAX a F PSW is: C MIN = 1 2 ΠF X PSW MAX (4) The bypass capaciance (C BYPASS ) is chosen a leas as big as C MIN. The common range of C BYPASS is from C MIN o 100C MIN. The noise volage is due o he changing curren hrough oal inducance in he sysem when drivers are swiching. The maximum inducance ha he sysem can olerae is: L o = X max Π T r (5) where T r is he rise ime from 10% o 90%. Since each bypass capacior has series inducance L C due o he lead package, an array of parallel capaciors is needed o reduce he inducance. The number of capaciors is deermined based on equaion 6. L C N = (6) Lo From he oal capaciance calculaed in equaion 4, he capaciance of each capacior in he array is: C elemen C min = (7) N prevening noise ranslaing from he clock driver o he main PCB. The clock drivers have swiching noise associaed wih hem. Using a ferrie bead beween he clock driver s power supply and he main PCB power plane effecively eliminaes his problem. The ferrie bead does no enhance nor degrade he performance of he driver; i is only used o provide noise isolaion. 4.2 Preven Noise Translaing From Clock Driver o he Main PCB The clock driver has swiching noise associaed wih hem. Using a ferrie bead beween he clock driver s power supply and he main PCB power plane is a good mehod o effecively eliminae his problem. The ferrie bead does no enhance or degrade he performance of he driver; i is only used o provide noise isolaion. Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 13
14 5 DDR Terminaion Common use of CDCV857/CDCV857A/CDCV855 is for DDR DIMM. The erminaion scheme in DDR DIMM is shown in Figure 14. SDRAM Sack 120 CLKIN 120 SDRAM Sack CLKIN# CDCV857 / CDCV Regiser 1 FBIN# 240 Regiser 2 Cfb 120 FBOUT# FBIN FBOUT Figure 14. CDCV857/CDCV857A/CDCV855 in DDR Regiser DIMM The impedance of all races connecing CDCV857/CDCV857A/CDCV855 in DDR DIMM is 60-Ω single ended or 120-Ω differenial. The lengh of each race o mee he iming requiremen for differen raw cards of DDR DIMM is specified in he DDR SDRAM specificaion wrien by he IBM or JEDEC commiee. In some applicaions such as SERDES where single-ended clock is required, he CDCV857/CDCV857A/CDCV855 oupus can be erminaed single-ended o Vcc/2 as shown in Figure 15. The unused signal can be lef floaing. 14 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
15 Vcc/2 CLKIN 120 CLKIN# CDCV857 / CDCV855 Y Y# FBIN# Cfb 120 FBOUT# FBIN FBOUT Figure 15. Using CDCV857/CDCV857A/CDCV855 for Single-Ended Oupus In some applicaions where he driver of CDCV857/CDCV857A/CDCV855 is available in singleended only, he CDCV857/CDCV857A/CDCV855 can ake single-ended inpu wih a bias nework as shown in Figure 16. For single-ended operaion, he recommended maximum inpu frequency for CDCV857/CDCV857A/CDCV855 is 150 MHz. The designer mus pay special aenion on how o choose he values for R1, R2, R3, R4, and C in Figure 3. The dc volage (Vbias) a nodes CLK and CLK# should be equal o Vcc/2 when no inpu signal is conneced o inpu node. Thus, R2 R3 = R1 + R2 R3 + R4 R 1 R2 = Z = 1 2 and where Z is he impedance of he ransmission line of he driver driving he CDCV857/CDCV857A/CDCV855. Typically, Z = 60 Ω. One selecion for a 60-Ω ransmission line is R1 = R2 = R3 = R4 = 120 Ω. C and a combinaion of parallel nework R1 and R2 form a high-pass filer. Therefore, C should be large enough o pass he lowes frequency. A recommended value of C is 680 pf. Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 15
16 Vcc Vcc Inpu C R1 Vbias R3 CLK R2 Vbias CLK# R4 CDCV857 / CDCV855 Yn Yn# FBIN# Cfb 120 FBOUT# FBIN FBOUT Figure 16. Using CDCV857/CDCV857A/CDCV855 as a Single-Ended Inpu 5.1 Zero-Delay Tuning The CDCV857/CDCV857A/CDCV855 is a PLL clock driver. The propagaion delay from he PLL inpu (CLK, CLK#) o he SDRAM inpu can be uned o zero hrough he feedback capacior (Cfb) as shown in Figure 14, Figure 15, or Figure 16. For zero delay from he PLL inpu o he SDRAM inpu, he race lengh and race characerisics of he feedback (FBOUT, FBOUT#) and he oupus (Yn, Yn#) have o be mached. Since he inpu capaciance of he FBIN and FBIN# pins of he CDCV857/CDCV857A/CDCV855 is less han he loading capaciance on he oupu pins (oal inpu capaciance of SDRAM), SDRAM inpu is slighly lagging he PLL inpu when Cfb = 0. Increasing he Cfb advances he SDRAM inpus relaive o he PLL inpus. Wih a small value increase in Cfb, delay from he PLL inpu o he SDRAM inpu can be uned o zero. If he SDRAM inpu is leading PLL inpu, decreasing Cfb adjuss he PLL inpu o SDRAM inpu o zero. Figure 17 is he graph of he normalized delay from Y0/Y0# o CLK/CLK# measured on he Texas Insrumens es board on a CDCV857A/CDCV855 device. This delay is normalized o zero when here is no discree feedback capacior on feedback race. Wih a small amoun of capaciance added on each pin of FBOUT and FBOUT# o V CC /2, he oupu Y0/Y0# advances wih respec o inpu and increases he delay from oupu o inpu. The designer can use his graph as a reference o une zero-delay from inpu o oupus. 16 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL
17 Tp d (p s) MHz 100 MHz Added Cfb (pf) Figure 17. Normalized Delay From Y0/Y0# o CLK/CLK# as a Funcion of Feedback Capaciance (Cfb) 6 References 1. DDR SDRAM Regisered DIMM Design Specificaion revision 1.0, July 2000, IBM, Micron Technology, and ServerWorks 2. Johnson, H.W., and Gram, M. High-Speed Digial Design. Prenice Hall, JEDEC Sandard No. 65, Sepember Using he CDC857 and CDCV850 o Transform a Single-Ended Clock Signal Ino Differenial Oupus Texas Insrumens applicaion noe, lieraure number SCAA043 Design Consideraions for TI s CDCV857 / CDCV857A / CDCV855 DDR PLL 17
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