A 4 th Order Continuous-Time ΔΣ ADC with VCO-Based Integrator and Quantizer

Transcription

1 A 4 th Orer Continuous-Time ΔΣ ADC with VCO-Base Integrator an Quantizer ISSCC 2009, Session 9.5 Matt Park 1, Michael H. Perrott 2 1 Massachusetts Institute of Technology, Cambrige, MA USA 2 SiTime Corporation, Sunnyvale, CA, USA

2 Motivation Analog Anti-Alias Filter Digital Channel Filter ADC I LNA cos(w o t) sin(w o t) Sample Clock ADC Q A highly igital receive path is very attractive for achieving multi-stanar functionality A key issue is achieving a wie banwith ADC with high resolution an low power - Minimal anti-alias reuirements are esirable for simplicity Continuous-Time Sigma-Delta ADC structures have very attractive characteristics for this space 2

3 A Basic Continuous-Time Sigma-Delta ADC Structure IN H(s) Multi-Level Quantizer OUT DAC clock Sampling occurs at the uantizer after filtering by H(s) Quantizer noise is shape accoring to choice of H(s) - High open loop gain reuire to achieve high SNR We will focus on achieving an efficient implementation of the multi-level uantizer by using a ring oscillator 3

4 Application of Ring Oscillator as an ADC Quantizer V tune Ring Oscillator Ref V tune Reset Counters Oscillator Phases Ref Register Count Out Similar approaches: Alon, Stojanovic, Horowitz JSSC 2005 Kim, Cho, ISCAS 2006 Count Out Input: analog tuning of ring oscillator freuency Output: count of oscillator cycles per Ref clock perio 4

5 VCO-Base Quantizer Also Shapes Delay Mismatch Measurement 1 Enable Measurement 2 Enable Measurement 3 Enable Measurement 4 Enable Barrel shifting through elay elements - Mismatch between elay elements is first orer shape 5

6 Benefits of VCO-base Quantization N-Stage Resistor Laer Pre-Amp Comparator IN N-Stage Ring Oscillator A 0 V V N A A 1 1 CLK Buffer N-bit Register IN CLK Much more igital implementation - No resistor laer or ifferential gain stages Offset an mismatch is not of critical concern Metastability behavior is improve Implementation is high spee, low power, low area 6

7 Freuency Domain Moel of VCO Quantizer VCO moele as integrator an K v nonlinearity Sampling of VCO phase moele as scale factor of 1/T Quantizer moele as aition of uantization noise V tune VCO T Ref Quantizer First Orer Difference Out 1- z -1 Key non-iealities: - Quantization noise - First orer shape! - VCO noise - VCO K v nonlinearity VCO Noise -20 B/ec f Quantization Noise f Output Noise 20 B/ec f V tune 2πK v s 1 T 1- z -1 Out VCO K v Nonlinearity VCO Sampler First Orer Difference 7

8 Example SNDR with 20 MHz BW (1 GHz Sample Rate) 60 Simulate ADC Output Spectrum Conitions SNDR Amplitue (B) VCO noise: MHz Kvco: ± 5% linearity Ieal VCO Thermal Noise VCO Thermal + Nonlinearity 68.2 B 65.4 B 32.2 B Freuency (Hz) VCO Noise -20 B/ec f Quantization Noise f Output Noise 20 B/ec f VCO K v nonlinearity is key SNDR bottleneck V tune VCO K v Nonlinearity 2πK v s VCO 1 T Sampler 1- z -1 First Orer Difference Out 8

9 Reucing the Impact of Nonlinearity using Feeback Ref In Gain an Filtering V tune VCO-base Quantizer Out DAC Iwata, Sakimura, TCAS II, 1999 Naiknaware, Tang, Fiez, TCAS II, 2000 Place VCO-base uantizer within a continuous-time Sigma-Delta ADC structure - Quantizer nonlinearity suppresse by preceing gain stage 9

10 A Secon Orer Continuous-Time Sigma-Delta ADC V IN 973 MHz V tune V A V B VCO-base Quantizer & Barrel-Shift DEM D OUT Straayer, Perrott VLSI u CMOS IC I DAC1 I DAC2 31 Thir orer noise shaping with a secon orer structure! Peak SNDR limite by Kv non-linearity to 67 B (20 MHz BW) 10

11 How Do We Overcome K v Nonlinearity to Improve SNDR? 11

12 Voltage-to-Freuency VCO-base ADC (1 st Orer Σ Δ) In prior work, VCO freuency is esire output variable - Input must span the entire non-linear voltage-to-freuency (K v ) characteristic to exercise full ynamic range - Strong istortion at extreme ens of the Kv curve 12

13 Propose Voltage-to-Phase Approach (1 st Orer Σ Δ) VCO output phase is now the output variable - Small perturbation on V tune allows large VCO phase shift - VCO acts as a CT integrator with infinite DC gain High SNDR reuires higher orer Σ Δ 13

14 Propose 4 th Orer Architecture for Improve SNDR Goal: ~80 B SNDR with 20 MHz banwith - Achievable with 4 th orer loop filter, 4-bit VCO-base uantizer - 4-bit uantizer: traeoff resolution versus DEM overhea Combine freuency/phase feeback for stability/sndr 14

15 Schematic of Propose Architecture Opamp-RC integrators - Better linearity than Gm-C, though higher power Explicit DWA 15

16 Schematic of Propose Architecture Passive summation performe with resistors - Low power Explicit DWA - Must esign carefully to minimize impact of parasitic pole 16

17 Schematic of Propose Architecture DEM explicitly performe on phase feeback - NRZ DAC unit elements DEM implicitly performe on freuency feeback - RZ DAC unit elements (Note: Miller, US Patent (2004)) 17

18 Behavioral Simulation (available at AMPLITUDE (B) MHz Banwith Selecte Noise, Non-Linearity: SNDR ~ 85 B FFT PLOT -160 Only VCO Kv -180 Non-Linearity: SNDR ~ 95 B ANALOG INPUT FREQUENCY (MHz) Key Noniealities VCO Kv nonlinearity Device noise Amplifier finite gain, finite BW DAC an VCO unit element mismatch 85 B SNDR! VCO nonlinearity is not the bottleneck for achievable SNDR!

19 Circuit Details 19

20 VCO Integrator Schematic en0 en1 en2 en4 15 stage current starve ring-vco - 7 stage ring-vco shown for simplicity - Pseuo ifferential control - PVT variation accommoate by enable switches on PMOS/NMOS en0 en1 en2 en4 Straayer, VLSI 2007 Rail-to-rail VCO output phase signals (VDD to GND) 20

21 VCO Quantizer Schematic outm clk outp Phase uantization with senseamp flip-flop - Single phase clocking inp clk clk inm Rail-to-rail uantizer output signals (VDD to GND) Nikolic et al, JSSC

22 Phase Quantizer, Phase an Freuency Detector Phase Output Freuency Output Highly igital implementation - Phase sample & uantize by SAFF - XOR phase an freuency etection with FF an XOR Automatic DWA for freuency etector output coe - Must explicitly perform DWA on phase etector output coe 22

23 Main Feeback DAC Schematic (same cell for V inm ) ap am ata clk VDD VSS DB QB D V inp Q Retiming Flip-Flop i out,p i out,m V inp V inm Yan et al JSSC 2004 Low-Swing Buffer i out,p V inp i out,m Current DAC Unit-Element V inm V casc,n V bias,n i out,p i out,m Low-swing buffers - Keeps switch evices in saturation - Fast on / Slow off reuces glitches at DAC output - Uses external V/Vss Resistor egeneration minimizes 1/f noise

24 Bit-Slice of Minor Loop RZ DAC PMOS Drivers clk up VDD clkb ump,p up Vbias,p Vcasc,p ump,p NMOS Drivers VDD clk ump,n outp inp outm inm ump,n ata clkb atab inp inm Vcasc,n Vbias,n vcm RZ DAC unit elements transition every sample perio - Breaks coe-epenency of transient mismatch (ISI) - Uses full-swing logic signals for switching 24

25 Opamp Schematic Vcm Gm Vcm Gm Mitteregger et al, JSSC 2006 Vbp outm outp inm Vcm inp Vbn Parameter DC Gain Unity-Gain Freuency Value 63 B 4.0 GHz Phase Margin 55 Input Referre Noise Power (20 MHz BW) Power (V DD = 1.5 V) 11 uv (rms) 22.5 mw Moifie neste Miller opamp - 4 cascae gain stages, 2 feeforwar stages - Behaves as 2-stage Miller near cross-over freuencies - Opamp 1 power is 2X of opamps 2 an 3 (for low noise) Gm Vcm 25

26 DEM Architecture (3-bit example) Barrel Shift Phase Quantizer Output Therm. to Binary Accumulator 3 3 clk See also: Yang ISSCC NRZ DAC Inputs Achieves low-elay to allow 4-bit DEM at 900 MHz - Coe through barrel shift propagates in half a sample perio

27 Die Photo (0.13u CMOS) Die photo courtesy of Annie Wang (MTL) Active area 0.45 mm 2 Sampling Fre 900 MHz Input BW 20 MHz Supply Voltage 1.5 V Analog Power 69 mw Digital Power 18 mw 27

28 Measure Results SNDR/SNR (B) SNDR (20MHz) SNR (20MHz) Peak SNDR = 78.1 B Peak SNR = 81.2 B Input Amplitue (BFS) 0 Magnitue (B) ,000 pt. FFT Freuency (Hz) 78 B Peak SNDR performance in 20 MHz - Bottleneck: transient mismatch from main feeback DAC Architecture robust to VCO K v non-linearity Figure of Merit: 330 fj/conv with 78 B SNDR 28

29 Behavioral Moel Reveals Key Performance Issue AMPLITUDE (B) MHz Banwith Selecte Noise, Non-Linearity: SNDR ~ 78 B FFT PLOT -160 Only VCO Kv -180 Non-Linearity: SNDR ~ 95 B ANALOG INPUT FREQUENCY (MHz) Amplifier nonlinearity egraes SNDR to 81 B DAC transient mismatch egraes SNDR to 78 B - DEM oes not help - Coul be improve with ual RZ structure Transient DAC mismatch is likely the key bottleneck

30 Conclusion VCO-base uantization is a promising component to achieve high performance Σ Δ ADC structures - High spee, low power, low area implementation - First orer shaping of uantization noise an mismatch - Kv non-linearity was a limitation in previous approaches Demonstrate a 4 th -orer CT ΔΣ ADC with a VCO-base integrator an uantizer - Propose voltage-to-phase conversion to avoi istortion from Kv non-linearity - Achieve 78 B SNDR in 20 MHz BW with 87 mw power Key performance bottleneck: transient DAC mismatch 30