Analog Input. Current

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1 A Continuous-Time Switche- Moulator with Reuce Loop Delay Louis Luh John Choma,Jr. Jerey Draper Electrical Engineering Information Sciences Institute University of Southern California University of Southern California Los Angeles, CA Marina el Rey, CA Abstract A novel architecture forasecon-orer continuoustime switche-current moulator is presente. The loop elay is reuce bypreicting the states of the secon integrator an feeing the preicte states to the comparator. The preicte states are generate by summing three scale current moe signals. A Gain- Manager is use toaccurately control the integrator gain to generate the preicte states an stabilize the system. A newly esigne high-spee current-moe comparator is capable of summing the three scale current inputs an comparing them. With a 50 MHz sampling rate, it has achieve 60 B ynamic range (10- bit) at 1 MHz. The moulator has been fabricate ina 2um CMOS process with an active area of 0.37 mm 2. The power issipation is 16.6 mw from a 5V single power supply. 1 Introuction research on high-spee low-power A-to-D conversion is mostly focuse on high-spee high-orer multi-bit switche-capacitor moulators. However, the spee of the switche-capacitor moulator is limite by the settling time of the OPAMP. To reuce the settling time of the OPAMP, the cost of higher power issipation an larger size must be pai. A multi-bit moulator requires the use of a ash A-to-D converter resulting in increase power issipation an size of the moulator. A continuous-time switche-current moulator can operate at high sampling spees with a lower power consumption. It irectly integrates the current on capacitors as shown in gure 1, which eliminates the nee of high spee OPAMPs. It also has the avantage of smaller size ue to a simplie circuit structure an fewer capacitors. However, continuoustime switche-current moulators suer from scaling, clock fee-through, an clock jitter problems, which limit their use to lower spee or lower resolution applications[1, 2]. In the past, the integrator gain of a continuous-time switche-current moulator has been etermine by the RC time constant of the on-chip resistors an capacitors[2, 3]. This RC time constant is not well Analog Input 1st Stage CINT1 2n Stage Figure 1: The simplie scheme of a secon-orer continuous-time switche-current moulator. controlle ue to processing variations of the resistance an capacitance, an therefore leas to gain error of the integrator. This gain error can cause a stability problem an a scaling problem which must be counterbalance by external compensation [3], otherwise the moulator can only be realize for rst-orer moulation[2]. In our previous work [4], the clock fee-through problem was successfully solve by newly esigne current switches as shown in gure 2. The scaling problem was solve by using a Reference- Generator for the secon stage. This circuit, implemente in a stanar 2um ouble-metal ouble-poly CMOS technology, achieve 50B ynamic range at 1 MHz with a 50MHz clock. However, this moulator contains an extra loop elay. This elay may cause a stability problem an must be compensate by reucing the loop gain, which egraes the performance of the moulator. The improve esign presente in this paper eliminates the elay by new circuit architecture. With preicte \next states" fe to the comparator, the loop elay is compensate without egraing the performance. In the following sections, we will iscuss how the elay can be reuce an how the circuit is implemente to achieve this goal.

2 From Input D-FF D-FF C INT1 SRD SRD M3 CMFB M4 Voltage energy of noise towar the higher frequency ban, an hence the in-ban noise is reuce. A moulator with only one clock cycle loop elay (rst-orer moulator) shoul have an ile channel peak output noise at 1/2 of the clock frequency. For an ieal secon-orer moulator, two elays are require by the two integrators (assuming each integrator requires one clock elay), an accoringly, the ile channel peak output noise shoul be aroun 1/4 of the clock frequency. 3 System Architecture Clock Note: D-FF = D-type Flip-Flop SRD = Swing-Reuce Driver CMFB = Common-Moe Feeback Analog Input First Stage Secon Stage I1 I2 Σ a Σ b Figure 2: The simplie scheme of the high-spee current switch. 2 Loop Delay in Continuous-Time Switche- Moulator In a switche-current moulator, the comparator (or the A-to-D converter for a multi-bit moulator) oes not require extra elay. If the comparator (ADC) can settle into a result within the rst half of the clock cycle, the reference voltage will be integrate on the integrator within the secon half of the clock. In most SC moulators, the clock spee is limite by the settling time of the OPAMPs, not the comparator, an therefore the extra loop elay oes not exist in switche-capacitor moulators. In continuous-time switche-current moulators, extra loop elay is require for the comparator to settle to a result an for the D-type ip-ops to synchronize the current switches. The synchronization of the current switches is very important since the integration relies on the time interval. This extra elay can cause a stability problem. The integrators ten to be overloae an cause the moulator to settle into a long perio of limit cycle. The stability problem can be solve by reucing the loop gain. However, this will eteriorate the noise-transfer function (NTF) to have less ynamic range an more in-ban noise. The extra loop elay also increases the time perio of the noise pattern an causes the pattern noise to enter the lower frequency ban. In the previous esign [4], the scaling factor between the rst an secon stage (the integrator gain of the rst stage) ha to be smaller than 0.5 to avoi the stability problem an even smaller to avoi overloa on the integrators an to have a reasonable input range. The scaling factor was set to be 0.25, resulting in an input range within 0:5I REF an an ile channel (no input) peak output noise of -20B at 5MHz, which is 1/10 of the clock frequency. Without the extra loop elay, the upper boun of the scaling factor is 1 (compare with 0.5 for the moulator with extra elay as state above). The noise transfer function (NTF) is improve by moving the Figure 3: The block iagram of a secon-orer moulator. The loop elay can be reuce by feeing the comparator with a preicte \next state". Figure 3 shows the block iagram of a secon-orer moulator, where I1, I2, an represent the output of the rst integrator, the secon integrator, an the respectively, an a an b represent the scaling factors. Set b to be 1 an the next state of the secon integrator is I2 N1 = I2 N a I1 N, N (1) By feeing this to the comparator, the comparator performs analog-to-igital conversion accoring to the \next state" of the secon integrator. This metho reuces the loop elay by 1 clock cycle an hence compensates the elay introuce by the comparator an the D-type ip-ops. The new circuit architecture is shown on gure 4. Analog Input Σ a Σ First Stage I1 Secon Stage a I2 Σ Figure 4: The block iagram of a secon-orer moulator with reuce elay. Equation (1) hols true if the rst integrator is a iscrete-time integrator. However, as the integrator is a continuous-time integrator, the output value is

3 changing continuously. If the moulator input current, I IN,isaslowly changing signal, as is normally true for moulators, the change at the output of the rst integrator within one clock cycle is I1 =I IN, (2) The next state of the secon integrator shoul be I2 N1 = I2 N a I1 N, N a I1 (3) 2 I2 N1 = I2 N a I1 N, (1 a 2 ) N a 2 I IN (4) To achieve the architecture in gure 4, the integrator gains of both the rst stage an secon stage have to be accurately controlle. In contrast, in the previous work [4], only the integrator gain of the rst stage neee to be well controlle, while the gain of the secon stage was arbitrary, as it only aecte the resolution of the comparator. controlle. A Gain-Manager is introuce to control the transconuctance gains of all the voltage-tocurrent converters. The etaile esign of each block is presente in the next section. 4 Circuit Design The propose new architecture uses a fully ierential esign to minimize the injecte noise from an the environment. Instea of switching between the current source an current sink as shown in gure 5, the current switch architecture switches only one current sink between two capacitors as shown in gure 6. This architecture eliminates the switching time mismatch problem an the parasitic capacitance problem [4, 2,3]. The etails of each builing block are escribe in the following paragraphs. Analog Input 1st Stage 2n Stage 1st Stage 2n Stage Reference Input Analog Input CINT1 -Moe Figure 6: The architecture of the new secon-orer continuous-time switche-current moulator. Figure 5: The circuit implementation of a seconorer moulator with preicte \next state". The new architecture can be implemente by introucing two voltage-to-current converters an one D- to-a (current switch) as shown in gure 5. Dierent scales of the voltage-to-current converter are achieve by sizing the transistors an current sources in the voltage-to-current converter. In this esign, the scaling factor a is set to be 0.5 for optimizing the loop stability, the available moulator input range, an the ratios of transistor sizes of the voltage-to-current converters. The higher orer correction terms, a 2 N an a 2 I IN as shown in equation (4), are not implemente ue to the availability of the uplicate of the input current, I IN. The noise transfer function (NTF) is egrae less than 3B ue to the lack of higher orer correction terms. However, the system is stabilize with the lack of the correction terms when large input is applie (I IN I REF ). To generate the preicte \next state" an the scaling factor correctly, the transconuctance gains of the voltage-to-current converters nee to be accurately 4.1 The Switch The current switch is realize by an NMOS ierential pair (, ) as shown in gure 2. D-type ip- ops are use to synchronize the switching with the clock to guarantee each integration is exactly one clock cycle. The Common-Moe Feeback (CMFB) block is a continuous-time common-moe feeback use to stabilize the common-moe voltage. The Swing-Reuce Drivers are use to reuce the voltage swing on the gates of { M4. This minimizes the clock feethrough problem an also reuces the charges which are move into an remove from the gates uring the switching. M3 an M4 are two ummy transistors with the same sizes as an, an are use to cancel out the feethrough charges from the gates. From the experiment of the previous work [4], all these blocks have very excellent performance as expecte. 4.2 The Voltage-Controlle (VCVCC) The Voltage-Controlle (VCVCC) is realize by the cross-couple qua cell [5] shown in gure 7a. The cross-couple qua cell compose by { M4 is a traitional NMOS crosscouple qua cell. However, the ierent commonmoe output currents cause by ierent ierential input voltages will cause a stability problem of the common-moe voltages of the integrators. M5 an

4 M6 are ae to solve this problem. Figure 8b shows the complete circuit iagram of the VCVCC. The controlling voltage input (V CONT ROL ) is use to control the transconuctance gain of the VCVCC. As the controlling voltage increases, the transconuctance gain of VCVCC increases. Reference Input 1/2 Iref S2 Integrate S1 Reset Differential to single-en converter A Ajust an Hol S4 Ajust C HOLD Controlling Voltage 1/2 Iref CINT1 S3 Precharge 1 CPRE M5 M6 M5 M6 IOUT VIN V CONTROL M3 M4 IOUT V IN V CONTROL VIN IOUT M3 M4 IOUT VIN VBIAS Figure 8: The simplie circuit scheme of the Gain Manager. (a) Figure 7: (a) The simplie circuit iagram of the Voltage-Controlle which utilizes the cross-couple qua cell. (b) The complete circuit iagram of the VCVCC. To minimize the nonlinear error an gain error of the transconuctance gain, the aspect ratio (W/L) is set to M3 = M4 = 5 = 5. From simulation, the nonlinear error an gain error are less than 5% within the whole input range. From system level simulation, a 10% error is tolerable without egraing the performance or introucing any stability problem. 4.3 The Gain Manager The Gain Manager controls the transconuctance gain by integrating the input reference current (I REF ) for two clock cycles, holing the current level, comparing the current level with the reference current input, I REF, an then ajusting the transconuctance gain. As shown in gure 8, the Voltage-controlle (VCVCC) is ientical to all the other VCVCCs in the system. A capacitor is use to memorize (hol) the controlling voltage of the VCVCC. The Gain Manager uses four successive clocke states to complete the task an operates repeately. The four states operate in the orer S 1, S 2, S 3, S 3, an then back tos 1. Each state is two clock perios long (40ns), an hence, the transconuctance gains of the VCVCCs are upate every 160ns. The function of each state is: S 1 : Reset the integrator by shorting C INT1 an C INT2. S 2 : Integrate the input reference current on C INT1 an C INT2. S 3 : Precharge. If point A is not precharge, charge sharing will aect the voltage of C HOLD, which may cause an error voltage an increase the time neee for the Gain Manager to converge to the nal value. During the precharge state, point (b) A is precharge to the voltage level of the last convergence point. S 4 : Ajust the controlling voltage. During this state, the Gain Manager becomes a close loop. The Gain Manager ajusts the controlling voltage of VCVCC so that the output current of VCVCC is exactly equal to the input reference current,. After this state, the holing capacitor, C HOLD, will hol this controlling voltage until the next S 4 state. 4.4 The High-Spee -Moe The high-spee -Moe is a two stage regenerative comparator [6, 7] as shown in gure 9. The input stage compose by { M8 is a current gain stage. The rst regenerative stage is compose by M9 { 2. The secon stage is compose by 3 { 6. 7 an 8 are use to precharge points c an. 9 is use to reset points a an b. 1 an 2 are two non-overlapping clocks. During the clock phase 2, the comparator is being reset. Point a an point b are shorte. When 2 rops from to groun, the rst stage begins the rst regeneration process. When 1 turns high, the secon stage starts the secon regeneration process. Either point c or point will rop to low voltage an trigger the RS latch. The input stage serves the following purposes, Decouples the charge feeback eect cause by the regeneration process (charges feeback from points a an b to the inputs). Guarantees voltages of the two input noes are within the output range of the VCVCC to have the VCVCCs operate properly. Oers a current gain for the two current inputs. By carefully esigning the layout an sizes of transistors, the -Moe has a resolution of 0.05uA with a 50 MHz clock by SPICE simulation. The charge feeback eect has been successfully eliminate. Together with the D-type ip-ops, only one clock elay is require.

5 Input Stage First Stage Secon Stage S R latch M5 M6 M Φ 1 Input current c Q M3 M4 M7 M8 5 a Φ 2 9 b 6 Q 1 2 Figure 9: The circuit iagram of the high spee current-moe comparator. 5 Experimental Results The continuous-time switche-current moulator has been implemente in a stanar 2-um N- well ouble-metal ouble-poly CMOS technology. Figures 10 shows the microphotograph of the moulator. The size of the active area is mm 2. With a single 5 V power supply, a 50 MHz clock, an a 10 ua reference current input, it achieves 60 B ynamic range in 1 MHz banwith. It has achieve 10B improvement in ynamic range compare to the previous work[4]. The total power issipation is 16.6 mw an more than 10 mw is issipate by the igital circuitry. With the use of a more avance process, the power issipation of the igital circuitry can be reuce resulting in a much lower power consumption. Figure 11 shows the output spectrum with a 100 KHz input. Compare to the previous work [4], the peak noise moves from 5MHz to 8.3 MHz (from 1/10 of the clock frequency to 1/6 of the clock frequency). The energy of noise is move to a higher frequency ban, reucing the in-ban noise in this esign. Figure 11: The moulator output spectrum with a 100 KHz sinusoi input. Figure 10: The microphotograph of the secon-orer continuous-time switche-current moulator. 6 Conclusions A new architecture of continuous-time switchecurrent moulator has successfully reuce the loop elay an attaine 10B improvement on the ynamic range compare to previous work. The novel Gain Manager, Voltage-Controlle, an the -Moe allow the continuous-time switche-current moulator to have complex feeback an fee-forwar signal

6 Table 1: The experimental result Previous Work moulator w/ [4] reuce elay Power supply voltage 5V 5V Clock frequency 50MHz 50MHz Signal Banwith 1MHz 1MHz Dynamic range 50 B 60 B Input reference current 10 A 10 A Input current range 5A 5A Power issipation 15 mw 16.6 mw Active area 0.37 mm mm 2 ( m) ( m) Technology 2m CMOS 2m CMOS paths, which cannot be achieve in traitional approaches. This new architecture oers a low cost way to realize a high-spee, low-power, an small-size A- to-d converter. Furthermore, it provies the founation for builing higher-orer moulators. Acknowlegements This project is sponsore bydarpa (Contract No. DABT ). References [1] F. O. Eyne an W. Sansen, Analog interfaces for igital signal processing systems, Kluwer Acaemic Publishers, [2] V. Comino et al. A rst-orer current-steering sigma-elta moulator, IEEE J. Soli-State Circuits, vol SC-26, pp , Mar, [3] R. Koch et al, A 12 bit sigma-elta analog-toigital converter with 15 MHz clock rate, IEEE J. Soli-State Circuits, vol. SC-21, pp , Dec, [4] L. Luh, J. Choma, an J. Draper, A 50MHz continuous-time switche-current moulator, submitte to International Symposium on Circuits an Systems 98 (ISCAS 98). [5] C. Ioumazou, F. J. Ligey, an D. G. Haigh, Analogue IC esign, the current-moe approach, IEE press, [6] G. M. Yin, F. O. Eyne, an W. Sansen, A highspee CMOS comparator with 8-b resolution, IEEE J. Soli-State Circuits, vol. SC-27, pp , Feb, [7] J. Wu an B. A. Wooley, A 100-MHz pipeline CMOS comparator, IEEE J. Soli-State Circuits, vol. SC-23, pp , Dec, 1988.