Clocking Techniques (II)

Transcription

1 Phase-Locke Loops Clocking Techniques (II) Ching-Yuan Yang National Chung-Hsing University Department of Electrical Engineering

2 Three-stage ifferential current moe ring oscillator 0.8-m n-well CMOS process I CR I CR I out I out Bias circuit I in I in M 1 M M 3 M 4 1 : A A : 1 I CR Delay Stage (1 of 3-stage Ring Osc.) EL, Jun

3 Current-controlle oscillator Differential-current steering logic (DCSL) V Bp M 1 M D1 M D M V Bn 8-

4 Current-controlle oscillator (ICO) Double input DCSL V Bp By using input main transistors M 1 an M larger than the auxiliary input transistors, the evice sizes of the main an auxiliary ifferential input transistors must be ratioe to operate properly. a a M 1a M 1 M D1 M D M M a Multiple-feeback-loop ring architecture V Bn Using the multiple-feebackloop ring architectures, the operation frequencies of ICO s are consierably improve. Frequency range, operation frequencies. a a a a a a ISSCC,

5 VCO circuit esign: voltage-controlle resistor (VCR) Differential elay element Bias I s Delay through the elay element is a function of the tail current (I s ), the ifferential voltage swing (V sig ), an the output noe capacitance (C out ). R cont VCR VCR (C out is the capacitance at the output noe consisting of the junction parasitics an the gate capacitance of the next stage.) By controlling signal R cont to the VCR loa, the voltage swing is hel constant an inepenent of supply voltage. C out, V sig constant T (I s ) 1 f vco I s T C out I V s sig For high rejection of power supply noise the ifferential signal is reference to V SS an the variable current source is cascoe for high impeance to V DD supply. 8-4

6 VCO circuit esign: voltage-controlle resistor (VCR) Voltage-controlle resistor IN I IN R cont M 1 M M 3 8-5

7 Differential elay element VCO Young, JSSC, Nov. 199 V cont I s I s V-to-I Converter Reference Generator R cont V ref VCR VCR VCR VCR Replica Biasing Delay Stage (1 of 5-stage Ring Osc.) The replica biasing circuit uses the same elay cell as the VCO, together with a ifferential amplifier. One input to the source-couple p-channel pair is groune, while the other input is connecte to V ref. All the current I s flows on the left sie of the ifferential pair. This is the maximum signal conition. Since R cont is use to bias the resistors in the VCO elay stages, the signal amplitue in the VCO is equal to V ref. 8-6

8 Symmetric loa I-V characteristics 8-7 Maneatis, JSSC, Dec. 1993

9 Differential symmetric loa VCO Replica-feeback current source bias circuit Differential buffer V Bp V ctrl (V ctrl ) Bias Init. V Bn Amplifier Bias Diff. Amplifier Half-Buffer Replica V ctrl Buffer Delay Stage (1 ofn-stage Ring Osc.) Maneatis, JSSC, Nov

10 Differential symmetric loa VCO I I D V ctrl (V Bp ) M 1 M V I D I V ctrl / V ctrl V Delay time of one elay stage: Assume the rain current for one of two equally size evices biase at V ctrl, an V = V ctrl, I I W D1 I D pcox ( Vctrl VT ) L p I W pcox ( Vctrl V 1 T ) V L R t Cout pcox( W / L) p ( Vctrl VT ) p eq Oscillation frequency for an n-stage VCO : f osc 1 pcox( W / L) p ( Vctrl V n t nc f osc out T ) 8-9 V ctrl

11 VCO circuit esign with a reference clamp voltage Differential elay element V cont P cont M 3 M 6 V op I s M4 To reuce the supply voltage noise, an ECL-like ifferential CMOS pair is introuce as a elay cell. It consists of a NMOS source-couple pair with PMOS loas. M 1 M V on N cont for M 5 is controlle by a bias to maintain constant voltage swing, an the use of M 5 an M 6 allows separate control of maximum an minimum output voltage from the power supply an groun. N cont M 5 C out, V sig constant T (I s ) 1 f vco I s T C out I V s sig 8-10

12 VCO circuit esign with a reference clamp voltage V cont M B4 M 6 I s V obp P con V op I s M 3 M 4 V H M B b V oc Reference Generator M B1 b M 1 M V on V obn V L M B3 N con M 5 Replica Biasing Delay Stage (1 of 3-stage Ring Osc.) Lee, JSSC, May 1997 Supply inepenent biasing of the elay cell is important for effective supply noise rejection an control of the free-running frequency. This is accomplishe by means of the replica biasing an the power supply inepenent reference generator. The biasing circuit forces the maximum voltage of the waveforms to be at V H an the minimum voltage to be V L. The value of V max (V H ) an V min (V L ) are always fixe an inepenent of the supply voltage an supply current. Note: Assume = V max (V H ) an b = V min (V L ) M is off, M 1 an M 4 are trioe, an M 3 is in saturation. b = V L, V op = V H =. 8-11

13 Barkhausen criteria Feeback system X(s) H(s) Y(s) Y X H ( s) ( s) 1 H ( s) If for s = j 0, H(j 0 ) = 1, then the close-loop gain approaches infinity at 0. Uner this conition, the circuit amplifies its own noise components at 0 inefinitely. Barkhausen criteria If a negative-feeback circuit has a loop gain that satisfies two conitions: H(j 0 ) 1 an H(j 0 ) = 180 o, then the circuit may oscillate at 0. In orer to ensure oscillation in the presence of temperature an process variations, we typically choose the loop gain to be at least twice or three times the require value. 8-1

14 Noise shaping in oscillators The system oscillates at = 0 if the transfer function X(j) Y H ( j) ( j) X 1 H ( j) goes to infinity at this frequency. H(j 0 ) = 1. For frequencies close to carrier, = 0 +, the open-loop transfer function: the noise transfer function: Y X j( ) H H H ( j0) H 1 H ( j0) H(j) H j) H ( j ) ( 0 1 H Y(j) 0 since H(j 0 ) = 1, an 1 the noise power spectral ensity function: Y X j( 0 ) ( ) 1 H Noise Power Spectral Density Y X H Output Spectrum 8-13

15 8-14 Noise shaping in oscillators ) ( Q j X Y Let H(j) = A() exp[j()], an hence Since for 0, A 1, We efine the open-loop Q as exp( ) j ja A H 0 1 ) ( A j X Y 0 A Q Noise shaping function Note: In an LC tank at resonance, A / = 0. Q 0 B. Razavi, IEEE JSSC, Mar. 1996

16 Linearize moel of CMOS ring oscillator Three-Stage Ring Oscillator G m R C In G m R C In G m R C In R an C represent the output resistance an the loa capacitance of each stage, respectively, an G m R is the gain require for steay oscillations. The noise of each stage is moele as current source I n. Open-loop transfer function 3 A0 H ( s) s 1 1 where A 0 = G m R an 1 = 1/(RC). Determine open-loop Q A 9, m RC 8 H ( j) 3 1 j 3 0 Oscillation:, G R an Open - Loop Q 1. 3 B. Razavi, IEEE JSSC, Mar

17 Linearize moel of CMOS ring oscillator Three-Stage Ring Oscillator G m R C In G m R C In G m R C In Noise shaping in power spectrum V I Four-stage ring oscillator: 0 n j R 0 ( 0 ) 7 Open - Loop Q 1.4 V I 0 n j R 0 ( 0 ) 16 (noise shaping function) The open-loop Q in the ring oscillators is generally very small. 8-16

18 Low-noise ring oscillator Base on the switching behavior of the elay cell, ring oscillators can be classifie into two types: Nonsaturate type: In the nonsaturate-type ring oscillator, the evices in the elay cell o not perform full-switching operation, an all MOS evices are always turne on uring the oscillation perio. Since the MOS evices operate uner a properly biase conition, each elay cell can be moele as a linear amplifier, an the overall VCO can be escribe as a linear feeback system. The analysis base on the linear moel shows the poor phase-noise characteristics of the nonsaturate-type ring oscillator. Saturate type: The saturate-type ring oscillator allows the full switching of some evices in the elay cell an shows better phase-noise performance. The saturate-type ring oscillator cannot be moele as a linear feeback system since the elay cells are completely turne on an off. The nonlinear characteristics of the oscillation system make the noise process nonstationary since no noise is generate in the elay cell for a certain time in one oscillation perio. 8-17

19 Effect of switching on thermal noise current in a elay element n p (t) (t) PMOS on NMOS on PMOS on n n (t) (t) n p (t) n n (t) Base on the analysis of the fully switching ring oscillators, the generate noise power is where T is the oscillation perio, T is the on-time of the T 4kTR transistors of the elay cell, f Pnoise m is the offset frequency from T 1 (f mrc) the carrier, an RC is the time constant of the 1 st -orer moel of the elay cell. The ring oscillator that has a short on- time or a short transition time for which noise current is generate is expecte to exhibit low output phase noise. During the off-time, since either NMOS or PMOS transistors are turne off, no noise current is generate from the transistor. In this case, the amount of the thermal noise current at the output noe of the elay cell is reuce. T Pnoise The noise power is proportion to the percentage of the on-time in one oscillation perio. T Park, IEEE JSSC, May

20 Fully switching ifferential elay cell M 3 M 4 M 5 M 6 M 1 V cont M Operation: A pair of PMOS loa transistors, M 3 an M 4, are ae to the elay cell to constitute a CMOS latch. The cross-couple NMOS transistors, M 5 an M 6, control the maximum gate voltage of the PMOS loa transistors an limit the strength of the ae latch. When V cont is low, the strength of the latch becomes weak, an the output riving current of the PMOS loa increases. elay time. When V cont is high, the latch becomes strong, an it resists the voltage switching in the ifferential elay cell. elay time. With the help of the positive feeback of the latch, the transition eges of the output waveform remain sharp in spite of slow elay time. 8-19

21 Ring-oscillator structure with ual-elay path Double input ifferential cell a M 1a M 3 M 4 M a a M 5 M 6 M 1 V cont M Dual-elay-path ring architecture Higher operation frequency, an wier tuning range are achieve. The ae skewe elay path ecrease the unit elay time of ring oscillator below the single inverter elay time. As a result, higher operation frequency can be obtaine. Since the normal elay paths also exist, the frequency range of VCO can be wier than that of an oscillator with only skewe elay paths. a a a a a a a a 8-0 Park, IEEE JSSC, May 1999

22 Latch-cell time constant G m V y C L R L V x V y V x Linear moel V y R L C L G m V y G G m m V V y x C C L L V t V t x y V R V R x L y L V t x V x A V V y Vy Vy AV Vx where RLCL an AV GmRL. t Johns, Analog Integrate Circuit Design,

23 Latch-cell time constant V AV 1 t Time constant latch V latch where V V RLCL C AV 1 AV G CL WLCox k Gm W Cox V L x V y V V e 0 ( A V 1) t / Latch time: If V L is obtaine to safely recognize the correct output value, then the time is given by T latch L m eff unity-gain frequency of each inverter. L k V epens primarily on the technology an not on esign (assuming a reasonable esign is use that maximizes V eff an minimizes C L ). C G L m V ln V L 0 L k V eff V ln V If V L /V 0 is larger, this latch time can be large, perhaps larger than the allowe time. L 0 eff 8-

24 Source couple multivibrator: relaxation oscillator Timing iagram M 1 off M 1 on M 1 off M 1 on M on M off M on M off V DD M 1 M C V DD V V DD V V tn Y V DD V V Bn V DD V V tn X R R t where V = I D R, an V DS(on) is very small. t (off ) M 1 M (on) I D X C I D I D Y I D V t C I tn D f osc 1 t ID 4CV tn 8-3

25 Open-loop Q of relaxation oscillator (linear moel) R R R R The open-loop transfer function M 1 M C Reraw M 1 C A C D M 1 C A C D gmrcs A H( s) ( )( 1) gm CA s RCs D I SS I SS I SS I SS C A = C For the circuit to oscillate at 0, H(j 0 ) = 1, an each stage must have a phase shift of 180 o, with 90 o contribute by each zero an the remaining 90 o by the two pole at g m / C A an 1/(RC D ). g m 0 p1 p RCACD H 4 RCA 0 an g m R C A CA C C D C open - loop Q 1 CA C D D A For C D = 0.5C A, Q reach its maximum value unity. B. Razavi, IEEE JSSC, Mar

26 Source couple VCO V ctrl preamplifier V osc I ctrl I ctrl V osc C M C M 1 Keeth, EL, Aug Assume the preamplifiers are esigne to have a switching threshol of V THS. The oscillating frequency is given by f osc V I THS ctrl 1 C t L where t L is the total elay through the logic gates. 8-5

27 Ring oscillator base on MOS inverter ring structure Ring oscillator an RC basic relation oscillator configuration R 1 V o1 V o C 1 R VCO Simplifie three-stage moifie ring oscillator V cont 8-6

28 VCO moifie D-latch ring oscillator V DD V DD V cont V DD V DD 8-7

29 VCO moifie flip-flops oscillator V cont Oscillator loop Latch Oscillator loop 8-8 Thamsirianunt, JSSC, Oct. 1997

30 All-igital phase-locke loop (ADPLL) Block iagram PLL_Go Control Ref. Clock Phase Detector Freq Comp. Phase Gain Freq Gain A m u x A m u x Aer Anchor Subtractor D C O C o n t r o l DCO DCO OUT 8-9 Dunning, JSSC, Apr. 1995

31 All-igital phase-locke loop (ADPLL) PLL lock begins with frequency acquisition. In this moe an algorithm sweeps the DCO frequency range to match that of the reference clock. The algorithm makes incremental changes to the DCO control wor base on the output of the frequency comparator. The value hel in the frequency-gain register etermines the magnitue of the incremental changes. At the en of frequency acquisition, the ADPLL transfers the DCO control wor efining the correct (baseline) frequency to the anchor register. When frequency acquisition is complete, the ADPLL enters phase acquisition moe. During phase acquisition, the ADPLL increments or ecrements the DCO control wor until the phase etector senses a change in the phase polarity of the reference clock relative to the internal clock.the value hel by the phase-gain register ictates the magnitue of the changes to the DCO control wor in phase acquisition moe, as well as in phase an frequency maintenance moes. Phase acquisition is finishe when a change in phase polarity occurs. To complete the phase-lock process, the anchor register transfers its contents to the DCO control register, restoring the DCO control wor value representing the baseline frequency. The ADPLL enables both phase maintenance an frequency maintenance moes after phase lock completes; these moes operate concurrently. 8-30

32 Digitally-controlle oscillator (DCO) Constituent DCO cell DCOX[9] DCOX[10] DCOX[11] DCOX[1] DCOX[13] DCOX[14] DCOX[15] 56y 18y 64y 3y 16y IN OUT 56x 18x 64x 3x 16x DCO[15] DCO[14] DCO[13] DCO[1] DCO[11] DCO[10] DCO[9] 8-31

33 Digitally-controlle oscillator (DCO) 8-cell DCO DCO[5..0] DCO[15..6] ENABLE 8-3

34 Direct igital synthesis 8-33

35 Direct igital synthesis (cont ) DDS using an accumulator f out P f CK M f f out,min out,max f CK M f CK Waveforms in a 3-bit DDS 8-34

36 Direct igital synthesis (cont ) Avantages Low phase noise: avoiing the analog VCO. Fine frequency steps Faster channel switching Continuous-phase channel switching at the output Direct moulation of the output signal in the igital omain Drawbacks Low-frequency generator: f ck is typically 3 or 4 times f out Power issipation DAC performance Settling time Harmonic istortion Spurious response Power issipation 8-35