A NOVEL ARCHITECTURE FOR SUPPLY-REGULATED VOLTAGE-CONTROLLED OSCILLATORS

Transcription

1 A NOVEL ARCHITECTURE FOR SUPPLY-REGULATED VOLTAGE-CONTROLLED OSCILLATORS A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University By Anu Chakravarty, B. E. Electrical & Computer Engineering Graduate Program * * * * * The Ohio State University 2010 Thesis Committee: Professor Mohammed Ismail, Adviser Professor Waleed Khalil

2 c Copyright by Anu Chakravarty 2010

3 ABSTRACT Voltage-controlled oscillators (VCOs) are critical components in the design of phase-locked loops (PLLs) for a variety of applications such as high speed digital communication systems, on-chip clock generators and RF transceivers. VCOs experience large supply noise variations due to digital switching currents. This degrades the jitter performance of the VCO, thus limiting system performance. Supply noise is a major concern in ring oscillators in particular, since the frequency of a ring VCO is highly dependent on the supply voltage. This thesis presents a novel power supply insensitive voltage controlled ring oscillators. This thesis also discusses some previously adopted VCO buffer stage designs implemented to achieve high supply noise rejection, and compares their results with those achieved with the proposed architecture. Based on the concepts developed in this thesis, a differential ring oscillator was designed in a 0.13-um CMOS technology, to demonstrate the robustness against supply fluctuation. The VCO operates from MHz to MHz, and displays complete rejection to power supply noise. ii

4 This is dedicated to my family and friends iii

5 ACKNOWLEDGMENTS I would like to acknowledge the contributions of people who were very helpful and supportive throughout my research here at The Ohio State University. I extend my sincere appreciation and gratitude to my advisor Professor Mohammed Ismail for providing me academic guidance and opportunity to perform research at the Analog VLSI Laboratory. I am grateful to him for providing me considerable freedom in defining and directing my research. And, am really thankful to him for being a wonderful mentor. I am also indebted to my co-advisor, Dr. Waleed Khalil, whose wisdom and expertise have enabled the successful completion of my thesis. He has helped me concentrate all my efforts on this work and has provided me constant encouragement and confidence throughout my research. He has always been there to clear my doubts and has always inspired me with his enthusiasm to do novel research. A special thanks to Bou-Sleiman at the Analog VLSI Lab for his continued support and helpful advice. I would like to thank my friends at Columbus with whom I have had many interesting discussions and who have made my time at the department enjoyable. I would like to thank Sarang Vadnerkar, Harsha, Mansi, Bhalchandra and Subhash in particular for their constant support and encouragement. It has been a pleasure having all of you around. iv

6 Finally, I would like to thank my family, my mother, my father and my sister for their continued love and support. I am really grateful to them for providing me a good home and for encouraging me to study as far as I can. I could not have asked for better parents and am really thankful to them for never losing confidence in me, even when I was beginning to doubt my own capabilities. v

7 VITA January 3, Born - New Delhi, India June 30, B.E. First Class with Distinction Electrical and Electronics Engg., Netaji Subhas Institute of Technology, New Delhi, India September December The Analog VLSI Lab, The Ohio State University. FIELDS OF STUDY Major Field: Electrical and Computer Engineering Studies in Analog and Mixed Signal Circuit Design : Prof. Mohammed Ismail vi

8 TABLE OF CONTENTS Page Abstract Dedication Acknowledgments Vita List of Tables ii iii iv vi ix List of Figures x Chapters: 1. Introduction Motivation Previous Work Maneatis Delay Cell Self-Calibration Thesis Outline Oscillator Theory Criteria for Oscillation Magnitude Criterion Phase Criterion Types of Oscillators Ring Oscillators LC-Oscillators Voltage-controlled Oscillators Oscillator Parameters vii

9 3. Previous Work Maneatis Delay Cell Implementation Wilson and Moon Calibration Technique - Sub-banding VCO Design Implementation Simulation Results Voltage-Controlled Oscillator Design and Analysis VCO Block Filtering effect Path from the output of the first stage to the input of the second stage: Path from the supply to the input of the delay stage: Bias Parameters Bias Generation Block Derivation Implementation Digital Calibration Block Simulation Results V CT RL = 50 mv V CT RL = 200 mv Conclusion Future Work and Conclusion Design Summary Future Extensions and Major Contributions Resistor tun-ability Increasing the frequency of operation Sub-banding Appendices: A. Complete Circuit Schematics Bibliography viii

10 LIST OF TABLES Table Page 3.1 Effect of supply variation on frequency (K F V SUP ) Variation of frequency with change in V BIAS = 0 volts Bias Parameters Bias voltage variation to maintain constant oscillation frequency Variation of frequency with change in V CT RL = 50 mv Variation of frequency with change in V CT RL = 200 mv.. 51 ix

11 LIST OF FIGURES Figure Page 1.1 Ring Oscillator Differential Ring Oscillator LC-Tank LC-VCO Maneatis Delay Cell with Symmetric Load Maneatis Delay Cell with Replica Feedback Self-Calibration Technique Block diagram of a feedback system Ring Oscillator Differential CMOS LC Oscillator Definition of a VCO Differential buffer stage with MOS symmetric load elements [1], [2], [3] Symmetric load I-V characteristics, dashed lines show the effective resistance of the loads and highlights the symmetry of the I-V characteristics [1] Self-biased replica-feedback current source bias circuit for the differential buffer stage [1] x

12 3.4 Maneatis VCO Voltage-controlled oscillator - Wilson and Moon [4] L operating modes of VCO [4] Voltage-controlled oscillator - Wilson and Moon Voltage-current converter Current multiplier ICO - delay stage ICO - delay stage Reduction in K V CO due to sub-banding Overall VCO block diagram Delay stages followed by RC Delay Stage with R P and R N Three Stage Ring Oscillator Delay stage with PMOS load Three Stage Ring Oscillator Effect of variation in supply fixed V BIAS - Frequency spectrum (DFT using hamming V BIAS = 0 V, Delay stage followed by resistor and capacitor (Filter effect) High-pass filter effect HPF - Effect of varying R B and C B Low-pass filter effect xi

13 4.12 LPF - Effect of varying R B and C B Bias voltage V BIAS variation with V SUP (V DD 1.1)0.6 + V CT RL Implementation Digital calibration block Digital Calibration Algorithm Resistor tunability VCO - voltage V CT RL = 50mV Frequency spectrum (DFT using hamming V CT RL = 50mV Frequency spectrum (DFT using hamming V CT RL = 50mV Resistor tun-ability (K F V SUP = R 1X R 0 ) Ring oscillator - adding another stage of RB-CB network A.1 Manetais VCO with symmetric loads and replica-feedback A.2 Voltage-controlled oscillator - Wilson and Moon A.3 Voltage-current converter A.4 Current multiplier - Wilson and Moon A.5 ICO - delay stage A.6 ICO - delay stage A.7 Proposed voltage-controlled oscillator xii

14 CHAPTER 1 INTRODUCTION This thesis focuses on the design and simulation of a power supply insensitive voltage-controlled ring oscillator. The first section presents the reasons to develop a ring VCO that has high power supply rejection ratio (PSRR). It discusses the difference between ring oscillators and LC-VCOs, which have better supply noise rejection by definition. Section 1.2 discusses some of the relevant, existing research. Some of the techniques in this thesis are derived from the works mentioned here. The last section lists the format of the remaining thesis. 1.1 Motivation Voltage-controlled ring oscillators are used in a variety of integrated circuit applications because of their ability to generate delays with very high precision at high operating frequencies. They are extensively used in phase-locked loops (PLLs)in high performance applications such as clock recovery, clock generation and frequency synthesis. In such applications the VCOs jitter performance can impact the output clocks timing jitter, thus limiting system performance. With the scaling of CMOS technology, and enhanced levels of integration more noise is coupled from the switching of digital circuits. This noise translates to jitter 1

15 at the the output and directly impacts the signal purity [5], [6]. Consequently, the design of VCOs that are noise tolerant is vital. In particular, for ring VCOs, supply noise is a major design concern as the oscillation frequency of a ring VCO is highly dependent on the supply voltage. This thesis, therefore, is the design of a ring VCO with complete rejection to power supply noise. Two principal topologies for the modern monolithic VCOs exist. They are the ring oscillator and LC-oscillator topologies [7], [8]. The ring oscillator, is composed of a ring of inverters with a net inversion around the loop as shown in Figure 1-1. This is achieved by using a chain of odd number of inverters. The frequency of oscillation is a function of the delay through each stage and the number of stages. To change the oscillation frequency the propagation delay of each stage could be adjusted in a number of ways, such as varying the current through each stage of varying the capacitative load at the output of each stage. The ring oscillator could Figure 1.1: Ring Oscillator 2

16 also be implemented using differential signaling by flipping the output of the last stage as it is fed back to the input of the first stage, as shown in Figure 1-2. In this thesis differential signaling approach is used, as it helps improve noise performance. The other class of VCOs, the LC-oscillator,is a subclass of resonant oscillators. The Figure 1.2: Differential Ring Oscillator circuit oscillates at the resonant frequency of the inductor and the capacitor, ω o = 1 LC. In an ideal LC-tank with no resistive losses, the inductor and capacitor oscillate indefinitely. However, since in practice it is impossible to build lossless passive circuits, active devices are used to produce negative resistance to cancel out any parasitic losses in the tank, as shown in Figure 1-3. A simple differential LC-VCO is shown in Figure 1-4. Figure 1.3: LC-Tank 3

17 Figure 1.4: LC-VCO The LC-tank inherently has excellent supply noise rejection since the frequency of oscillation is a function of only the values pf the inductor ans the capacitor. These values do no vary with supply fluctuations hence the frequency of oscillation is relatively stable. Also, the LC-tank inherently filters out frequencies away from the resonant peak, thus improving phase noise performance. However the tuning range of LC-VCOs is limited compared to the ring oscillator since tuning is achieved by using a varactor as voltage controlled capacitance, which has limited tuning range. 4

18 1.2 Previous Work To suppress the change in frequency of a ring VCO with supply noise, many methods have been adopted. Some of them use differential structures [9], voltage regulators [10] and calibration techniques [4]. Others use compensation techniques to cancel the VCOs intrinsic positive supply sensitivity with additional negative supply sensitivity circuitry [11], [12]. This thesis, draws comparison between the new proposed approach and the existing approaches by Maneatis [1], [2] and Wilson and Moon [4] Maneatis Delay Cell The Maneatis delay cell [1], [2], [3] as shown in Figure 1-5 relies on symmetric loads and dynamic biasing to achieve VCOs with superior power supply rejection and wide tuning range. The concept behind using symmetric loads is that the load Figure 1.5: Maneatis Delay Cell with Symmetric Load 5

19 elements should ideally have linear I-V characteristics which helps provide differentialmode resistance that is independent of common-mode voltage. Since the delay of the buffer stage is dependent only on the differential mode resistance, it is not affected by the common-mode disturbances resulting from the supply noise. However since adjustable resistive loads made with real MOS devices do not maintain linearity while generating wide frequency range, Maneatis proposes the concept of symmetric loads which have symmetric I-V characteristics. This symmetric characteristics helps inhibit the conversion of common-mode noise into differential-mode noise, and hence achieves high supply noise rejection. Maneatis also uses the concept of replica-bias Figure 1.6: Maneatis Delay Cell with Replica Feedback to vary the current in the buffer delay stage to provide correct symmetric load swing limits. The replica-bias also helps counteract the effect of finite output impedance 6

20 of the NMOS current tail source to achieve high supply noise rejection as shown in Figure Self-Calibration Wilson and Moon [4] employ the concept of self-calibration techniques to design low-noise frequency synthesizers. They use a digitally programmable VCO as shown in Figure 1-7, that helps cover wide range of output frequencies while keeping a very low control voltage to output frequency gain. This is the sub-banding approach to achieve lower VCO gain that has been proposed for the new architecture as well, to achieve lower Kvco, and hence lower jitter at the output. The self-calibration approach helps overcome a significant amount of process variation. This concept of self-calibration is also incorporated in this thesis as part of future work. The concepts Figure 1.7: Self-Calibration Technique of variable resistive loads to achieve better supply noise rejection and self-calibration to overcome process variations are used in this thesis to develop a novel power supply insensitive voltage-controlled oscillator architecture. 7

21 The Maneatis and Wilson and Moon, architectures are further discussed in detail in chapter Thesis Outline The next chapter deals with general oscillator theory, explaining different oscillator types and parameters. The second chapter describes the proposed novel voltage-controlled oscillator architecture. The simulation results are also presented in this chapter. Chapter three discusses the Maneatis architecture, its variations and the Wilson and Moon architecture in detail. Chapter four compares the simulation results of the new VCO with those achieved with existing architectures developed to reduce supply noise rejection. Finally, Chapter 5 reviews the principal contributions of this thesis and includes a number of suggestions for future work using the ideas presented herein. 8

22 CHAPTER 2 OSCILLATOR THEORY Oscillators have been essential components since Edwin Armstrong discovered the heterodyne principle, wherein they effect frequency translation by multiplying the oscillators signal with other input signals. Since then oscillators have been an integral part of many electronic systems. Their applications range from clock generation to carrier synthesis, and are one of the most challenging blocks in the design of a PLL. This theoretical chapter deals with the design of CMOS oscillators, more specifically voltage-controlled oscillators (VCOs) [7], [8]. It discusses the criteria that must be fulfilled by a circuit to produce oscillations, introduces the two main types of oscillators, the ring oscillator and the LC-oscillator. It further discusses the methods of varying the oscillators output frequency and finally lists some of the important performance metrics used to evaluate oscillators. 2.1 Criteria for Oscillation A simple oscillator produces a periodic output, usually a voltage signal. The oscillator circuit has no input however it sustains an output indefinitely. This is possible only if the overall feedback becomes positive in an amplifier. Thus, the 9

23 behavior of oscillators can be modeled as a feedback system as shown in Figure 2-1. In the block diagram, block A represents an amplifier and block β represents a Figure 2.1: Block diagram of a feedback system feedback network that is connected from the output of the amplifier to its input. The two conditions that are necessary but not sufficient to make a circuit oscillate are defined as the Barkhausen Criteria. When using the notations of the model in Figure 2-1, this criteria can be given as Aβ = 1 (2.1) The criteria can be divided into two parts, i.e, the magnitude criterion and the phase criterion Magnitude Criterion The magnitude criterion for oscillation states that the gain Aβ of the oscillator loop must be equal to one during standard operation. In practice the loop gain has to be larger than one for the oscillator to begin to oscillate and for the oscillation amplitude to grow. The amplitude will eventually saturate due to device nonlinearities, reducing the loop gain to one and providing a signal with stable amplitude. 10

24 2.1.2 Phase Criterion The phase criterion for oscillation states that the phase shift of the oscillator loop must be zero or a multiple of 2π. This means that the signals with the same phase are summed at some point in the oscillator. If the phase shift was an odd multiple of π, then the signals would have opposite phases and would cancel each other out. In that case there will be no oscillation. 2.2 Types of Oscillators Ring Oscillators Ring Oscillators are a subset of the class of delay based oscillators wherein one or more delay elements are connected in feedback configuration. A ring oscillator consists of a number of gain stages in a loop. Figure 2-2 shows the schematic of a three stage inverter ring oscillator. The oscillation frequency f o of the oscillator can Figure 2.2: Ring Oscillator 11

25 be calculated as: f o = 1 3(T 1 + T 2 ) (2.2) where T 1 is the delay of the rising edge and T 2 is the delay of the falling edge. The delay varies with change in bias current or supply voltage and hence changes the frequency of oscillation. Delay based oscillators have poor phase noise-performance compared to resonator based oscillators. However, since delay based oscillators do not need an inductor to operate, they can be implemented using small chip area. Ring oscillators also have another advantage of high tuning-range. Ring oscillators have a major disadvantage though, i.e, they are highly susceptive to supply noise, which effects the delay of each stage and hence the frequency of oscillation. Thus, in thesis, we discuss a new approach to build the ring oscillator such that it is completely insensitive to power supply noise. This architecture uses the differential implementation of delay stages, which help cancel out common-mode noise. Differential implementations also may use even number of delay cells by simply configuring one cell such that it does not invert. This flexibility demonstrates another advantage of differential circuits over single-ended counterparts LC-Oscillators LC-oscillator belongs to the class of resonator based oscillators, which are the most common topology in radio applications. In resonator based oscillators, the oscillation frequency is determined by a resonance circuit such as an LC-tank. An amplifier compensates for the loss in the resonance circuit and keeps a sustained oscillator. 12

26 Figure 2-3 shows an LC-VCO. Due to the differential architecture and relatively good phase noise it is one of the most popular oscillator configurations used in fully differential integrated RF CMOS applications. The LC-VCO contains two major Figure 2.3: Differential CMOS LC Oscillator parts, the passive LC tank which determines the frequency of oscillation and the active devices that compensate the loss in the tank. The LC tank contains an inductor (L) and capacitor (C). The oscillator will oscillate at a frequency where the reactance of the inductor cancels the reactance of the capacitor. The oscillation frequency is given by the equation: f o = 1 LC (2.3) In order to vary the frequency of oscillation, the capacitor is often implemented using a voltage-controlled capacitor (varactor) or an array of digitally controllable capacitors, 13

27 or a combination of both. The other ways of tuning the frequency are varying the inductance using MEMS or by changing the bias current. The LC-VCO is highly insensitive to supply noise fluctuations since the frequency is a function of discrete components L and C only. However, this thesis intends to develop delay stage architectures for ring VCOs such that the oscillation frequency is independent of supply noise fluctuations. 2.3 Voltage-controlled Oscillators Applications such as clock recovery and clock synthesis, require the oscillators to be tunable. Tunability means that the output frequency must be a function of some control input, usually voltage. This voltage could be for example the output of the loop filter in an analog PLL. In an ideal voltage-controlled oscillator, the output frequency is a linear function of its control voltage. ω OUT = ω O + K V CO V CONT (2.4) Where ω OUT represents the intercept corresponding to V CONT = 0 and K V CO denotes Figure 2.4: Definition of a VCO 14

28 the gain or sensitivity of the circuit (expresses in rad/s/v). The achievable range, ω 2 ω 1 is called the tuning range as shown in Figure Oscillator Parameters Some of the important performance metrics of the voltage-controlled oscillator are discussed below. These parameters help select the best oscillator for a particular application. Oscillation frequency The oscillation frequency f 0 or the fundamental frequency of an oscillator is defined as the frequency at which the main peak in the oscillator s output spectrum is located. Frequency tuning range The tuning range of an oscillator is defined as the distance between the lowest and highest output frequencies that the oscillator can produce. Tuning voltage or tuning current range T uning range = f max f min (2.5) The tuning voltage(or current) range refers to the range of acceptable voltages (or currents) that can be applied to the tuning circuitry of an oscillator. Frequency tuning curve The frequency tuning curve is a graphic representation of what happens to the oscillators output frequency as the tuning voltage(or current) is swept through the acceptable range. It is usually desirable that the tuning curve is monotonic. 15

29 Phase noise Phase noise is a measure of the frequency stability of an oscillator. It is defined as the output signal power at a certain offset f m from the carrier frequency f 0 and the power of the carrier, both within a 1-Hz bandwidth. It is usually given in dbc/hz. Pushing figure L(f m ) = 10log( P (f m) P (f 0 ) ) (2.6) The pushing figure of an oscillator gives the dependence of the output frequency on the supply volatge. It is usually given in MHz/V. Pulling Figure P ushing figure = f V SUP max V SUP min (2.7) The pulling figure indicates how dependent the oscillator s output frequency is on the value of load impedance. P ulling figure = f R LOADmax R LOADmin (2.8) 16

30 CHAPTER 3 PREVIOUS WORK 3.1 Maneatis Delay Cell The voltage-controlled oscillator architecture proposed by Maneatis uses a differential buffer stage with symmetric load elements and self-biased replica feedback, to have high supply noise immunity, while operating at low supply voltages. In this architecture, digital calibration is not employed to achieve supply rejection, unlike the architecture proposed in this thesis in chapter 3. The concept is that, high supply rejection can be achieved with high output impedances. This can be done by cascoding the load impedances in the delay stages. However, since cascoding is incompatible with low-voltage circuit design, Maneatis proposes the use of a current source bias circuit, thus enabling the buffer stages to have high supply rejection without cascoding. Symmetric load elements are also used in the buffer stages to enable supply noise cancellation. Differential buffer stage The buffer stage used, is based on an NMOS source-coupled pair with symmetric load elements and a dynamically biased NMOS current source as shown in Figure 17

31 Figure 3.1: Differential buffer stage with MOS symmetric load elements [1], [2], [3] 3-1. The bias voltage of the simple NMOS cell continuously adjusts itself to provide a supply independent bias current. Since, the output swing is referenced to the top supply, the current source helps isolate the buffer from the supply and hence, helps achieve constant buffer delay. The load elements are composed of symmetric loads i.e, a diode connected PMOS device in shunt with an equally sized biased PMOS device. These loads are called symmetric loads because their I-V characteristics is symmetric about the center of the voltage swing as shown in Figure 3-2. The control voltage, V CT RL biases the PMOS device and helps generate the bias voltage for the NMOS current source and hence controls the delay of the buffer stage. Current source bias circuit The current source bias circuit as shown in Figure 3-3, helps set the current through a simple NMOS current source in the buffer delay stage to provide the correct 18

32 Figure 3.2: Symmetric load I-V characteristics, dashed lines show the effective resistance of the loads and highlights the symmetry of the I-V characteristics [1] symmetric load swing limits and also helps adjust the NMOS current source bias so that the current is held constant and independent of supply voltage. The current source bias circuit uses replica of half the buffer stage and a single-stage differential amplifier. The amplifier adjusts the current output of the NMOS current source so that the voltage at the output of the replicated load element is equal to the control voltage. This helps set the correct swing limits for the symmetric load Implementation The maneatis delay cell with symmetric loads and replica-feedback bias generator was implemented in cadence 130-nm. The VCO circuit was modified by shorting the differential pair tail nodes of the delay cells. This enables their tail node voltage to be more or less constant and closer to that generated by the bias generator. Simplified schematic of the voltage-controlled oscillator is shown in this section Figure 3-4, and the full schematics can be seen in Appendix-A. 19

33 Figure 3.3: Self-biased replica-feedback current source bias circuit for the differential buffer stage [1] 3.2 Wilson and Moon Calibration Technique - Sub-banding The self-calibration technique used by Wilson and Moon [4] enables the design of low-noise frequency synthesizers without compromising on the frequency range of operation. Since the output frequency of an oscillator covers a wide range of frequencies for a limited range of input voltage, the gain of the VCO is high. This leads to hight output jitter and phase noise. The digital calibration technique is used to make a programmable VCO, which covers a wide range of frequencies while keeping a low control voltage to output frequency gain (K V CO ). This helps reduce the phase noise and output jitter considerably. The digital word is generated using a self-calibration algorithm. The process variations are also compensated for by the self-calibration technique. This sub-banding 20

34 Figure 3.4: Maneatis VCO 21

35 technique can also be incorporated in the proposed design to reduce th oscillator gain K V CO and further improve the noise sensitivity VCO Design The VCO is made up of a voltage-to-current converter (V-I), current multiplier (IX) and current-controlled oscillator (ICO) as shown in Figure 3-5. The VCOs L- Figure 3.5: Voltage-controlled oscillator - Wilson and Moon [4] bit programmability is attained by the current multiplier, which controls the current flowing into the the ICO. The operating range of the VCO is distributed into 2 L modes. This concept is illustrated in Figure 3-6. One of the operating modes is chosen using the L-bit control word depending on the desired frequency of operation. This results in a small output frequency to control voltage transfer function and thus provides low sensitivity to noise. 22

36 Figure 3.6: 2 L operating modes of VCO [4] Implementation The V-I converter, current multiplier and ICO were implemented in cadence 130- nm, and a five bit control word was used to provide sub-banding. Simplified schematics of these blocks are shown in this section, and the full schematics can be shown in Appendix-A. The complete block diagram of the VCO is shown in Figure 3-7. The building blocks are further discussed in detail in the following subsections. V-I Converter The V-I converter consists of a n-channel and a p-channel differential pair as shown in Figure 3-8. One side of each of the differential pairs is connected V RF which is equal to half the supply voltage. The other transistor s gate is connected to V RF or V LF, based on the output of the comparator. The current from the two pairs depends 23

37 Figure 3.7: Voltage-controlled oscillator - Wilson and Moon 24

38 on the voltages V RF or V LF, and finally the summation of the two currents is applied to the current multiplier. Figure 3.8: Voltage-current converter Current Multiplier The current multiplier is implemented with binary weighted transistors, as shown in Figure 3-9. The control word used is five bits. The maximum current output of the multiplier is 31 times the input current. ICO The ICO is implemented using three delay stages in cascade. The first stage also consists of a half-replica buffer to generate the control voltage V CT RL, applied to the 25

39 Figure 3.9: Current multiplier gates of the PMOS loads of the following delay stages. The circuit diagram for the delay stages are shown in Figure 3-10 and Figure Simulation Results A five bit control word was used to generate 32 operating modes. The multiplied current for each of these modes was generated using the current multiplier and the resulting frequency of operation was measured with varying control voltage V CT RL. V CT RL was varied from 0 to 1.2 volts and the resulting oscillator gain was calculated for each operating mode. Without sub-banding the K V CO of the VCO would have been (5.618 GHz GHz )/1.2 Volts, i.e, GHz/V. However, by using the sub-banding technique the K V CO has been reduced to a few hundred megahertz. This reduction in the oscillation gain helps reduce the output jitter and reduces the phase noise of the VCO. The results with sub-banding are shown in the following excel sheet Figure The effect of supply noise on frequency was also reduced considerably, 26

40 Figure 3.10: ICO - delay stage 1 Figure 3.11: ICO - delay stage 2 27

41 L (Multi plier) Vmin Imin (ua) Fmin (GHz) Fmax (GHz) Imax (ua) Vmax (V) Fmax-Fmin (GHz) Overlap Diff Max Side Percentage Overlap Upper End (%) Overlap diff Min side Percentage Overlap Lower End (%) no overlap no overlap no overlap no overlap no overlap no overlap no overlap no overlap no overlap no overlap no overlap KVCO (MHz/V) Figure 3.12: Reduction in K V CO due to sub-banding 28

42 as shown below in Table 3.1. However, even better supply rejection is acheived using the proposed architecture as discussed in Chapter 4. V SUP (V) Itail K F V SUP Sensitivity (µa) (MHz/V) (percentage/v) F req (GHz) Table 3.1: Effect of supply variation on frequency (K F V SUP ) 29

43 CHAPTER 4 VOLTAGE-CONTROLLED OSCILLATOR DESIGN AND ANALYSIS The VCO, with the overall block diagram as shown in Figure 4-1, is composed of the voltage-controlled oscillator block, the bias voltage generation block and the digital calibration block. The VCO, a ring oscillator, consists of three differential Figure 4.1: Overall VCO block diagram delay stages connected in a loop. The output of each delay stage is followed by a capacitor and a resistor before feeding the output to the input of the next delay stage, as shown in Figure 4-2. The capacitor is used to remove the DC from the output and the resistor is used to fix the DC of the output to 0.6 volts. This ensures that 30

44 Figure 4.2: Delay stages followed by RC variation in the common-mode value of the output, with supply voltage fluctuations, does not effect the DC value of the input of the next stage. The capacitor and resistor values are chosen very carefully, to make sure that they do not attenuate the output signal being fed into the next stage. The concept is that the slope K F V SUP, i.e, the maximum variation in oscillation frequency with respect to the worst case variation in supply volatge needs to be measured and fed into the digital calibration block at VCO start-up. Next the control voltage V CT RL, for example the output voltage of the loop filter in a PLL, is added to the V REF voltage in the V BIAS Generation block. V BIAS is generated in this block, by using the equation 4.1, V BIAS = (V SUP 1.1)K F V SUP + V CT RL (4.1) where, V SUP, is the varying supply voltage. The derivation of this equation is discussed in detail in section 4.2. V BIAS, the tuning voltage, is then used to vary the frequency of oscillation of the VCO. The first section describes the simple VCO core, with V BIAS as the voltage input and F OUT as the output oscillation frequency. Section 4.2 presents the simulation 31

45 curves which lead to the derivation of equation (4.1). Section 4.3 discusses the calibration block in detail. Section 4.4 discusses another possible architecture for the VCO. Finally, the simulation results are presented and discussed in Section 4.5. Some of the ideas for the implementation of the calibration and bias generation blocks are also presented in detail in this chapter. 4.1 VCO Block The VCO is a ring oscillator and consists of three delay stages connected in a loop. In the preliminary design the delay stage was implemented in the form of a source degenerated common-source amplifier with a resistive load R P and source degeneration resistance R N as shown in the figure 4-3. The complete VCO diagram Figure 4.3: Delay Stage with R P and R N is shown in Figure

46 Figure 4.4: Three Stage Ring Oscillator 33

47 However, the frequency of oscillation varies with change in supply voltage. This happens due to the change in current through the delay stage with supply variation. Therefore, an additional input is required to tune the circuit to negate the effect of supply voltage variation. To this effect, we vary the resistance R P to make sure that the current flowing through the delay stage in independent of supply fluctuation. Thus, the load resistance R N is modeled as a PMOS with a voltage control V BIAS applied at its gate, as shown in Figure 4-5. The proposed voltage-controlled oscillator diagram is presented Figure 4.5: Delay stage with PMOS load in Figure

48 Figure 4.6: Three Stage Ring Oscillator 35

49 Since the current through a MOSFET in saturation is: I D = 1 2 µc W ox L (V GS V th ) 2 (4.2) Thus, if V BIAS biases the gate voltage of the PMOS such that V GS remains constant, the current through the delay stage would remain constant, making the oscillation frequency, F OUT supply insensitive. The bias voltage follows a linear pattern with supply variation as shown in Section 4.2. This helps formulate the effect of supply fluctuation on the VCO output frequency in the form of the linear equation (4.1). The following figure and table show the effect of variation in frequency when the supply is varied from 1.1 volts to 1.3 volts in linear steps of 0.02 volts, while V BIAS is fixed at 0 volts. To negate this effect the bias generation and digital calibration Figure 4.7: Effect of variation in supply fixed V BIAS - Frequency spectrum (DFT using hamming V BIAS = 0 V, 36

50 V SUP (V) F req (MHz) V SUP (V) F req (MHz) Table 4.1: Variation of frequency with change in V BIAS = 0 volts blocks are introduced. These blocks help vary the V BIAS with variation in supply and hence maintain fixed oscillation frequency, thus enabling the design of the novel power supply insensitive VCO. These blocks are discussed in detail in the following sections of this Chapter. 4.2 Filtering effect In this voltage-controlled oscillator design, each delay stage if followed by a capacitor and resistor as shown in Figure 4-8. The capacitor and resistor are introduced Figure 4.8: Delay stage followed by resistor and capacitor (Filter effect) 37

51 to remove the DC component of the output signal of the delay stage, and DC bias it to 0.6 volts before it is fed into the input of the following stage. The values of capacitor and resistor are calculated with careful analysis. The two effects that need to be taken into consideration while deciding these values are explained below Path from the output of the first stage to the input of the second stage: When following this path, the capacitor C B and resistor R B act like a high-pass Filter (HPF), as shown below in Figure 4-9. The transfer function of this filter is Figure 4.9: High-pass filter effect given in equation (4.3). V OUT V IN = sc B R B 1 + sr B (C B + C gmos ) (4.3) The V OUT versus V IN characteristics with varying resistor and capacitor values are plotted as shown in Figure From the plot, it can be seen that if R 1 and C 1 are too low then the output signal gets completely attenuated, and the VCO stops oscillating. 38

52 Figure 4.10: HPF - Effect of varying R B and C B 39

53 4.2.2 Path from the supply to the input of the delay stage: When following this path, the resistor R B and capacitor C B act like a low-pass filter (LPF) as shown in Figure The transfer function of this filter is given in Figure 4.11: Low-pass filter effect equation (4.4). A step input was applied at the supply and the transient response at the output was plotted, for varying resistor and capacitor values, as shown in Figure From the plot it can be seen that, if the resistance and capacitance are too high it takes longer for the DC of the output voltage to settle at 0.6 volts, since the settling time is directly proportional to R B and C B. V OUT V SUP = sr B (C B + C gmos ) (4.4) Thus taking the two effects into consideration the resistor value R B was fixed at 10 kilo ohms. Similarly, the capacitor value C B was fixed at 20 femtofarads. 40

54 Figure 4.12: LPF - Effect of varying R B and C B 41

55 4.3 Bias Parameters The complete schematic of the VCO core, with V BIAS as voltage input and F OUT as the output oscillation frequency is presented in Figure 4-6. The bias values of the transistors and resistors and capacitors are enlisted in Table 4-2. R B 10KΩ R N 100Ω C B 100f F C N 20f F C P 20f F W M1,P 2,P 3 10µm W M4,P 5,P 6 10µm W P 1,P 2,P 3 5µm W P 4,P 5,P 6 5µm L M1,P 2,P 3 130ηm L M4,P 5,P 6 130ηm L P 1,P 2,P 3 130ηm 130ηm L P 4,P 5,P 6 Table 4.2: Bias Parameters 4.4 Bias Generation Block The bias generation block is used to generate the voltage V BIAS that controls the gate of the PMOS, and thus varies the load resistance. The resistance is varied such that the current through the delay stage remains fixed, even when the supply voltage fluctuates. The bias voltage V BIAS was varied, along with the supply voltage and the simulated results are enlisted in Table 4-3, as shown below. These values were then plotted with V BIAS as y axis, and V SUP as x-axis, as shown in Figure

56 V SUP 1.1 V 1.15 V 1.2 V 1.25 V 1.3 V V CT RL mv f req (MHz) V BIAS (mv) Table 4.3: Bias voltage variation to maintain constant oscillation frequency Figure 4.13: Bias voltage V BIAS variation with V SUP 43

57 V CT RL, the voltage from the output of the loop filter, enables the VCO to change the frequency of oscillation, i.e, it enables the VCO to jump from one frequency curve to the other as shown in the plot. As V CT RL increases, the frequency of oscillation of the VCO decreases. The supply voltage V SUP was varied from 1.1 volts to 1.2 volts in linear steps of 0.02 volts. It can be seen from the above plot that, the curves are linear. This means that the slope K F V SUP is constant, i.e, for an increment δv SUP there is a linearly proportional increase in δv BIAS. Thus, a linear relationship can be derived between V BIAS, V DD V REF ; the difference in supply voltage from the reference voltage V REF, K F V SUP and V CT RL Derivation A common form of linear equation in the two variables a and y is y = mx + b where m and b are designate constants. The constant m determines the slope or gradient of the line, and the constant term b determines the point at which the line crosses the y-axis. The above linear curves, can be defined by a similar linear equation where, b = V CT RL, (4.5) m = K F V SUP, (4.6) y = V BIAS, (4.7) V BIAS = (V DD V REF )K F V SUP + V CT RL (4.8) 44

58 From the above plotted curves, the slope K F V SUP is calculated to be 0.6 V/V. The reference voltage V REF was fixed at 1.1 volts. Hence, the equation defining the above plot, can be written as Implementation V BIAS = (V DD 1.1)0.6 + V CT RL (4.9) The above equation was implemented using an opamp with closed loop gain 0.6V/V and an open loop gain of 10,000. The circuit is presented in Figure where, Figure 4.14: (V DD 1.1)0.6 + V CT RL Implementation R 1 = R 5 = 600Ω, R 2 = R 3 = 1KΩ, R 4 = R 6 = 1KΩ, 45

59 4.5 Digital Calibration Block The digital calibration block as shown in Figure 4-15 is used to find the value of K F V SUP. After the VCO is powered up, the input V REF is swept from 0.9 volts to Figure 4.15: Digital calibration block 1.1 volts in linear steps of 0.1 volts, the supply voltage V SUP is kept constant at 1.1 volts, and the control voltage input V CT RL is kept fixed at 0 volts. Firstly, V REF is fixed at 1.1 volts, thus generating a bias voltage V BIAS equal to 0 volts. Then the oscillation frequency of the voltage controlled oscillator is measured. Next, V REF is changed to 1.0 volts and the same process is repeated. The frequency of oscillation is measured. However, since this frequency from the one obtained when V REF was 1.1 volts, the resistor in the opamp is varied till the time the oscillation frequencies of the VCO in the two different steps match. The same steps are repeated for V REF equal to 0.9 volts. Finally, the K F V SUP is measured by divided the value of the varied resistor by 1000, as explained in the following eqautions. The above discussed steps are presented in the form of a digital calibration algorithm as shown below in Figure

60 Figure 4.16: Digital Calibration Algorithm 47

61 The opamp with resistor R1, R2, R3, R4, R5 and R6 is shown below, in Figure The transfer function can be written as: Figure 4.17: Resistor tunability V OUT = ( V CT RL R6 + V SUP R4 )( 1 R1 + 1 R5 + 1 R3 )( R6 R4 ) V REF R3 R2 (4.10) if, R1 = R6 = R (4.11) and, R2 = R3 = R4 = R5 = R0 (4.12) V OUT = V CT RL + (V SUP V REF ) R R0 T hus, K F V SUP = R R0 (4.13) (4.14) If, R0 = 1000Ω (4.15) K F V SUP = R 1000 (4.16) Thus, by varying R to maintain the same frequency of oscillation with supply variation, we can calculate the required slope K F V SUP. 48

62 4.6 Simulation Results The proposed voltage-controlled oscillator discussed in this chapter was implemented in cadence 130-µ m CMOS technology. The bias control voltage was varied along with supply variation, according to the proposed bias voltage generation equation 4.1. The supply voltage was varied from 1.1 volts to 1.3 volts in steps of 0.05 volts, and the voltage-controlled oscillator output was plotted V CT RL = 50 mv Figure 4.18: VCO - voltage V CT RL = 50mV 49

63 The frequency of each of the above waveforms in the plot was calculated, and is presented below in Table 4.4. V SUP (V) V BIAS (mv) F req (MHz) Table 4.4: Variation of frequency with change in V CT RL = 50 mv Figure 4.19: Frequency spectrum (DFT using hamming V CT RL = 50mV Inference: The variation in frequency with supply voltage is almost negligible. 50