Design of a Low Power, High Performance BICMOS Current-limiting Circuit for DC-DC Converter Application

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1 PIERS ONLINE, VOL. 3, NO. 4, Design of a Low Power, High Performance BICMOS Current-limiting Circuit for DC-DC Converter Application Hongbo Ma and Quanyuan Feng Institute of Microelectronics, Southwest Jiaotong University, ChengDu 6131, China Abstract A low power, high performance current-limiting circuit implemented in.6 um BICMOS process, which has been successfully applied to the chip of high efficiency, wide input voltage range DC-DC boost switch power management chip, is presented. The circuit as the core sub-block of the chip consists of current-limiting comparator, soft starting and slop compensation. The dynamic bias and slop compensation technology in current-limiting comparator is adopted to improve the performance and to reduce power consume. In this paper, the deign methodology and process of the circuit is analyzed in detail. The simulation and test results based HSPICE show: under the power supply of 3.3 V, the circuit has the gain of 117 db and low quiescent current of 15 UA. DOI: /PIERS With the rapid development of the integrated circuit technology, the requirement of low power consumption, small volume, low cost for portable and powered equipment such as MP3, PDA and digital camera can be satisfied impossibly, meanwhile, the new functions belonging to the energy hunger and thirst type are increasing with day, so it is key issue in this field how to integrate these new functions in smaller volume and to prolong the service time of battery-operated equipments. At present, the switch-mode DC-DC converters have been widely used in power supply systems and are becoming a common building block in modern VLSI systems, which are taking place of LDO and will be the best solution because of its high efficiency. Therefore, it is meaningful and better market prospect to research the power management IC of high efficiency, low power. Figure 1 illustrates a simplified boost dc-dc converter s functional block diagram. Its main function is to convert input dc voltage to higher output dc voltage with minimum power loss. The converter is composed of a power stage and feedback control circuits. V S is a battery voltage, which supplies input dc voltage, and is the boosted output dc voltage. The inductor L, diode D1, and capacitor C are off-chip components. Resistors R1 and R2 sense the output voltage and generate the scaled output voltage to the error amplifier. RLOAD is the load of the dc-dc converter. D 1 Vs M 1 L C R 2 R L O A D R 1 control logical limiting current comparator sense soft-starting compensation _ + error comparator FB_TH Figure 1: Boost dc-dc converter s functional block diagram. From Figure 1, it is found that the performance of current-limiting circuit makes great effect on the total performance of the switch-mode DC-DC converters, such as power consumption, efficiency, temperature characteristics and so on. In this paper, a.6 um low power, high performance

2 PIERS ONLINE, VOL. 3, NO. 4, BICMOS current-limiting Circuit is designed, which is applied to a high efficiency boost type switch mode DC-DC chip as shown as Figure 1. The chip has been widely applied in portable and powered equipment such as MP3, PDA and digital camera and reflection from market is beyond our expectation. Classic Current-limiting Comparator: Usually, it is hoped that the requirement of highspeed, high-gain and high dynamic range to comparator is implemented in condition of lower supply voltage and minimum power consumption, Figure 2 displays various comparators employed in DC- DC converter. In Figure 2(a), the folded cascode configuration is used to input stage, which is characteristic of better frequency response and PSRR, but larger power consumption and low-gain are its deadly shortcoming. The classic two-stage comparator is shown as Figure 2(b), whose gain is higher, but PSRR and speed is lower. Figure 2(c) shows the cascade configuration of one telescopic configuration and many differential structure employing resister load, which is high-gain at cost of the area and power consumption, and difficult to design the matching between many stages. Likewise, there are some other types, but those are cascade of folded cascode, telescopic, differential structure employing resister load or current mirror and single transistor configuration. VDD VDD bais1 M1 M2 M3 M4 M5 M3 M4 IN Q2 Q1 Q3 Q4 VTH bais2 M6 bais3 M8 M7 M9 M11 M1 OUT VM1 N I B M8 M1 M5 M2 V P M6 M7 VO GND (a) Two-stage comparator with Folded input. GND (b) Two-stage comparator. VDD bais1 bais2 V O V p V N GND (c) Many-stages cascaded comparator. Figure 2: The various conventional current comparators. According to our experience, the above circuit s gain does not exceed 1 db, and that out swing of circuit (c) is reduced. Therefore, to improve DC-DC converter s efficiency and reduce the power consumption, some improvements and optimizations are done in this paper. Design of Low Power, High Performance Current-limiting Circuit: Based on current mode PWM controlling method, the current-limiting circuit includes current-limiting comparator, soft-start and slop compensation circuit. Concretely, the current sensing circuit is arranged in high-performance comparator, meanwhile, the comparing threshold is provide by soft-start and slop compensation time-dividedly, i.e., when system is enabled, the soft-start provides the increasing threshold, then taken by slop compensation s out when the starting function is completed, which reduces surge current and improves the system stability, insure the system stability, make the inductor current not vary with the duty ratio, and decrease the error between peak and average value, also contain the inferior harmonic wave oscillation and ring inductor current. Deign of Current-limiting Comparator: As shown as Figure 3, CS is the sampling input port, R4, C1, R6 constitutes the sampling network, and Vbais is the bias voltage, which is provided by OUT1 of the soft-starting circuit. SOFT OUT and SLOP OUT is the comparing threshold, which

3 PIERS ONLINE, VOL. 3, NO. 4, provides the comparing threshold time-dividedly, OUT is the output port, in order to improve the drive ability and compatible to the digital circuit, an inverter composed of M18, M19 is added before OUT signal. Foled cascode Gain prompting Common source Figure 3: The current-comparator schematic in the paper. (1) The high performance design of comparator Comparing the valuable frameworks, the three stages is chosen in the circuit configuration: in the first stage, the folded-cascode is adopted employing resistor load and Darlington difference transistors, which is characteristics of wide common-mode input rang to enlarge the coverage of the comparator. The difference with the load of current mirror constitute the second stage to raise the gain of comparator, respectively, the output stage is implemented in the common source with current source load. The M16 and M17 is cascaded as a transistor (owing to the L max, and W max of.6 um technology). All the MOS transistors is operated in the saturation region, respectively, all the BJT transistors are operated in the linear region. Obviously, the CMR of the circuit is decided by the first stage, i. e., V CM(min) = V OV M6 (sat) + V BCQ3 (linear) V BEQ2 (linear) (1) V CM(max) = V DD V OV M2 (sat) + V BEQ2 (linear) V BEQ3 (linear) (2) The total gain about 12 db is gotten by multiplying the three gains. R o represents the load A V 1 = G m1 R out1 = g c m {R o //[(g mm8 + g mbm8 )r om8 r M6 ]} (3) g c m = ( 1 + g m r π1 ) (4) (β + 1)r π2 g m = I c = I c V be V T (5) A v2 = g m7 R o A V 3 = G m R out3 = G m r M15 (6) where G m represents the equivalent transconductance of M16 and M17 in series. Specially, the branch the M1, M11 provides the gate voltage for M7, M12 to decrease the real voltage of high level, which improves the propagation delay time, but the power consumption is added. (2) Condensations on power consumption When the system works normally: I total = I M1 + I M2 + I M3 + I M4 + I M6 + I M14 + I M9 + I M15 (7) Assume the current of M1 in the saturation region I = 1 ( ) 15u 2 U P C ox (V DD V bais V th ) 2, 7.2u according to the parameters, we know I total = 65I.

4 PIERS ONLINE, VOL. 3, NO. 4, It can be known from above formula that the quiescent current is too large. To decrease the current, the dynamic bias is adopted. Provided that a square wave voltage (V1 is the best bias voltage and V2 is more than V1, T is the period) is used to provide the bias voltage, In a period, the total power consumption of comparator: P total = V DD 1 2 U P C ox ( 15u 7.2u ) [ (V DD V 1 V th ) 2 T 2 + (V DD V 2 V th ) 2 T 2 However, on the condition of the fixed offset voltage: P total = V DD 1 ( ) 15u 2 U P C ox [(V DD V 1 V th ) 2 T (9) 7.2u V 2 > V 1, P dynamic < P fixed. Design of this dynamic VBIAS circuit is arranged in soft-starting circuits. Soft-stating and slop compensation circuit This soft-starting circuit has the two functions as shown as Figure 4: (1) it is employed to provide the increasing threshold gradually for the comparator when system is enabled, which improve the reliability and efficiency of system due to suppressing the surge current and solve the re-starting problem, (2) it is used to provide the dynamic bias for the comparator at normal operation to reduce the quiescent power. Figure 5 shows the simplified slop compensation schematic, which is designed for providing the threshold after the soft-start function, is completed. At present, the current mode has more advantages than the voltage mode, but it also exists some disadvantages, for example, the system s instability when the duty exceeds the 5%, the inferior harmonic vibration, poor interference rejection capability and so on. To improve these shortages, the slop compensation is employed in paper. Slop compensation voltage usually is designed in PWM comparator threshold or current feed-back voltage. In this paper, the slop compensation is implemented in PWM comparator threshold port. The slop amplitude and slope can be adjusted by C3, R4 and current value for charging and discharging to improve the compensation performance. The current-limiting comparator and other sub-blocks of the current-limiting circuit are simulated by HSPICE. The result is shown as Figure 6. The simulation results are gotten by coopering from all the sub-blocks. From the (a) and (b), the gain can attain 1 db, the highest of 121 db and the worst of 9 db, the propagation delay time, CMRR and CMR is also higher than the same application comparator, even though the propagation delay time includes the delay time of relevant signals. In the Figure (c), the quiescent current of comparator varies periodically with bias voltage as our analysis, respectively Figure (d) ] (8) Figure 4: The soft-starting schematic in the paper.

5 PIERS ONLINE, VOL. 3, NO. 4, Figure 5: The simplified slop compensation schematic. illustrates the time sequence of relevant signals with the comparator, whose real work behavior, real value and their relationship is shown as Figure 6(d). To reduce the simulation timethe absolution time of every signals is reduced in rata. The instability of SOFT OUT and VBAIS is resulted in by the reference voltage not established at this moment. A.6 um BICMOS current-limiting circuit is successfully designed with the dynamic offset and slop compensation for DC-DC converter application. The simulation and test results show that this circuit is characteristic of low power consumption, high performance, which satisfies fully the requirements of the new generation DC-DC products. Moreover, it has been applied to a DC- DC switch mode power management IC, which provides a solution to design portable and powered equipments such as MP3, PDA and digital camera for low power, small volume, and multi-function. Among the many people who have been greatly helpful during my work, my advisor, Professor Feng quayuan is first one to whom I would like to express my most sincere appreciation, for the most source of support on my research. I would also like to thank my colleagues, for their help in my design. This work was supported by Postgraduate Foundation for Creation on traffic & transport engineering of Southwest Jiaotong University, and by National Science Foundation of P. R. China, Grant No and the Leader of Academic & Technology of Sichuan province cm.5 2m 4m 6m 8m Viltage X (lin) (VOLTS) Volts db (lin) k 1k 1k 1x 1x 1x Frequency (log) (HERTZ) (a) (b) Parars (lin) Parars (lin) -13u -14u -15u -16u -17u -18u -19u -5u -1u 15u 2u 234u 236u 238u 24u 242u 244u 246u 248u 25u 5u 1u 15u 2u 25u 3u 35u 4u m u 1u 15u 2u 25u 3u 35u 4u 45u 5u 55u 6u 2u 4u 6u 8u 1u 12u 14u 16u 18u 2u 22u 24u (c) (d) Figure 6: (a) the CMR and gain of comparator, (b) the data table of comparator, (c) Quiescent Current of comparator, (d) the sketch map of all the signals.

6 PIERS ONLINE, VOL. 3, NO. 4, REFERENCES 1. Ridley, R. B., A new continuous-time mode for current-mode control, IEEE Transaction on Power Electronics, April Kazimierczuk, M. K. and LaVern A. Starman, Dynamic performance of PWM DC-DC boost converter with input voltage feedforward control, IEEE Transactions on Circuits and Syestems-I: Fundamental Theory and Applications, Vol. 46, No. 12, , December Lee, C. F. and P. K. T. Mok, A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique, IEEE J. Solid-state Circuits, Vol. 39, No. 1, 3 14, Jan Roh, J. High-performance error amplifier for fast transient DC-DC converters, IEEE Transactions On Circruits and System-II: Express Briefs, Vol. 52, No. 9, September Vorperian, V., Simplified analysis of PWM converters using model of PWM switch, IEEE Transactions on Aerospace and Electronic Systems, Vol. 26, No. 3, , May 199.

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