Low Voltage PLL Design Tolerant to Noise and Process Variations

Transcription

1 Low Voltage PLL Design Tolerant to Noise and Process Variations SRC ICSS Program Review September 9, 2003 Un-Ku Moon and Karti Mayaram School of EECS Oregon State University, Corvallis OR

2 Task ID: Technical Thrust: Circuit Design Task Leaders: Un-Ku Moon and Karti Mayaram Students: Merrick Brownlee (PhD, July 2006) Volodymyr Kratyuk (PhD, July 2006) Industrial Liaisons: David R. Johnson, Intel Corporation Woogeun Rhee, IBM Corporation Mark Steeds, National Semiconductor Corp. Anticipated Result: Development of low voltage design techniques that can be used for the design of noise tolerant PLLs and frequency synthesizers. Self-calibration methods will be developed to tune out process/temperature and voltage variations yielding a robust design. Page 2

3 Task Deliverables New noise tolerant design techniques for low voltage PLLs in digital processes (Jun ) Verification of low voltage noise tolerant design techniques using fabricated test structures (Mar ) Digital control techniques for blocks within the PLL (Mar ) Verification of self-calibration and digital control techniques using fabricated test structures (Dec ) Design of a 1.2 volt PLL for a 5GHz wireless LAN application in a 0.1-um CMOS process (Mar ) Page 3

4 Executive Summary Accomplishments during the past year Project start date Apr Initial study of power supply noise sensitivity on ring oscillators Page 4

5 Executive Summary Future direction Develop noise tolerant low voltage design techniques for PLLs utilizing ring and LC based oscillators Develop effective digital programmability for selfcalibration Page 5

6 Executive Summary Technology transfer & industrial interactions Interactions with National Semiconductor Publications None Patentable inventions, patent applications None Page 6

7 Outline PLL Design Issues Ring-oscillator based VCOs Supply noise analysis Future work Page 7

8 Phase-Locked Loop Design Issues Phase Detector Loop Filter VCO Frequency Divider Page 8

9 PLL Building Blocks Voltage controlled oscillator Wide tuning range and low jitter/phase noise Charge-pump based loop filter Frequency divider Phase detector Page 9

10 Phase Noise/Jitter vs. Tuning Range Tuning Range Ring Oscillators Maneatis LC Oscillators Lee/Kim Phase Noise LC oscillators tend to be low noise, narrow tuning range Ring oscillators tend to be high noise, wide tuning range Page 10

11 Source of Ring Oscillator Phase Noise Intrinsic Noise Thermal Flicker Environmental Noise Power Supply Substrate Page 11

12 Ring Oscillator Topologies Maneatis Delay Cell Lee/Kim Delay Cell Vctrl Vctrl Intrinsic Noise Power Supply Noise Tuning Range Maneatis Poor Good Wide Lee/Kim Good Poor Narrow Which has better overall phase noise performance? Page 12

13 Lee/Kim Cell Operation Vctrl No tail current source rail-to-rail swing Positive feedback through cross coupling fast switching No mechanism to reduce power supply noise coupling to output Page 13

14 Conversion of CM Noise to DM Noise Power supply noise causes CM noise at the output Resistor mismatch converts CM noise to DM noise Non-linear loads cause resistor mismatch Need a practical, linear load Page 14

15 Maneatis Symmetric Load 8 x V CTRL Vctrl + V RES Vres 6 I RES Ires I RES Ires 4 V CTRL =2.5 2 V CTRL = V RES First order approximation to linear resistor I-V curve Only symmetric up to V CTRL limited output swing Page 15

16 Resistor Matching Symmetric Load 3.5 x I RES Ires Slope=R Slope=R V RES Differential output swings equal and opposite amounts and sees the same slope matched resistance Assumes the output swings around V CTRL /2 Page 16

17 Improving Noise of Maneatis Linear rather than symmetric is most important for resistance matching 3.5 x Ires Slope=R 1 Slope=R Vres If output CM level is not V CTRL /2, resistance matching is poor Page 17

18 More Linear Load + VVctrl CTRL Vth Vth I RES Ires M1 M2 + V RES Vres -V RES2 term of M 2 cancelled by +V RES2 term of M 1 Approximate current equation: I RES =k W/LV RES Valid for 0 V RES V CTRL Page 18

19 More Linear Load I-V Curves I RES vs. V RES Resistance vs. V RES Ires (ma) Linear Symmetric R (kohms) Symmetric Linear Vres (V) Vres (V) Fairly linear even above V CTRL No need to limit swing Page 19

20 Implementation of Linear Load + Vctrl Ires M1 M2 Vth + Vres + Vctrl A source follower is used to implement the voltage drop Page 20

21 Power Supply Noise Generation R0 1 R1 1 Vdd V DD or ground C Works for either V DD or ground noise kt R0 Noise variance = C R1 Able to sweep noise variance by sweeping R 0 Page 21

22 Initial Simulation Environment 1.8-V 0.18µm CMOS, f osc =3.3GHz, f=1mhz (1/f noise not included in the model) Figure of Merit (FOM) defined: FOM ( ω) = 20log( f0) L( ω) 10log( P) T. I. Ahrens and T. H. Lee, ISLPED, 1998 Page 22

23 320 V DD Noise Sensitivity Intrinsic noise Figure of Merit Lee/Kim Maneatis Mean Squared V DD Noise (V 2 on Log Scale) Lee/Kim has better intrinsic noise rejection since the FOM is higher for small amounts of V DD noise Maneatis has better V DD rejection since the corner where V DD noise starts degrading FOM is higher Page 23

24 Ground Noise Sensitivity Figure of Merit Lee/Kim Maneatis Mean Squared Power Supply Noise (V 2 on Log Scale) Both oscillators are less sensitive to ground noise Unlike V DD case, there is a point at which the superior ground rejection of Maneatis outweighs the superior intrinsic noise rejection of Lee/Kim Page 24

25 Noise on Both V DD and Ground-Fixed Figure of Merit V DD Ground Both Mean Squared Power Supply Noise (V 2 on Log Scale) Gnd noise Set ground variance at a fixed level (10-2 ) and sweep V DD Overall FOM follows ground only FOM when V DD noise is small and V DD FOM when V DD noise is large Page 25

26 Linear Load Power Supply Sensitivity Figure of Merit V DD Ground Mean Squared Power Supply Noise (V 2 on Log Scale) Better intrinsic noise rejection than Maneatis Similar V DD noise rejection Worse ground noise rejection Page 26

27 Dual Tail Current Latch Delay Cell in+ out+ out in The best power supply rejection achieved due to the tail current source (like the Maneatis oscillator) The best intrinsic noise rejection due to the positive feedback (like the Lee/Kim oscillator) This cell combines the two positive features Page 27

28 Latch Power Supply Sensitivity Figure of Merit V DD Ground Mean Squared Power Supply Noise (V 2 on Log Scale) Best intrinsic noise rejection Similar V DD noise rejection compared to Maneatis Worse ground noise rejection Page 28

29 Which Oscillator is Best? Depends on the amount of V DD and ground noise! A series of plots show trends 1. Fixed amount of ground noise 2. Plot V DD noise variance vs. FOM as before 3. Increase ground noise and repeat Page 29

30 Ground noise variance = 10-8 V Figure of Merit Lee/Kim Maneatis Latch Linear Mean Squared Power Supply Noise (V 2 on Log Scale) Gnd noise Lee/Kim Latch Page 30

31 Ground noise variance = 10-6 V Figure of Merit Lee/Kim Maneatis Latch Linear Mean Squared Power Supply Noise (V 2 on Log Scale) Gnd noise Lee/Kim Latch Page 31

32 Ground noise variance = 10-4 V Figure of Merit Lee/Kim Maneatis Latch Linear Mean Squared Power Supply Noise (V 2 on Log Scale) Maneatis Lee/Kim Gnd noise Latch Page 32

33 Ground noise variance = 10-2 V Figure of Merit Lee/Kim Maneatis Latch Linear Mean Squared Power Supply Noise (V 2 on Log Scale) Gnd noise Maneatis Lee/Kim Latch Page 33

34 Conclusions From Plots Ground Noise Small Medium Large Small Latch Lee/Kim Maneatis V DD Noise Medium Latch Lee/Kim Maneatis Large Latch Latch Latch Latch type (Latch, Lee/Kim) are usually better than source coupled pair (Maneatis, Linear) Linear load oscillator never has the highest FOM overall, but it does often outperform the Maneatis Viable alternative to Maneatis as proposed Page 34

35 Next Steps Explore 0.1µm predictive models from Berkeley Power supply noise sensitivity analysis of various ring and LC based oscillators Develop noise tolerant low voltage design techniques for oscillators and PLLs using ring and LC based oscillators Develop effective digital programmability for self-calibration Start interaction with Industry Liaisons to align practical future direction Page 35