Low Voltage CMOS VCOs
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1 Competence Center for Circuit Design Low Voltage CMOS VCOs Niklas Troedsson Department of Electroscience Lund Institute of Technology Lund University Sweden Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 1/16
2 Outline Introduction - Project: Bluetooth Receiver Front-End Low Voltage Oscillator Topologies: 2 Chips VCO: AP ASIC 02 [1] & RAWCON 02 [2] Source Node Tuning (Filtering Technique) Amplitude Control Varactor Study of Low Voltage Operation QVCO: NORCHIP 03 Summary Tuned Buffer Stage Distributed Capacitance Analysis of Monolithic Inductors References Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 2/16
3 Introduction - Project Low Voltage Bluetooth Receiver in CMOS: Receiver architecture for complete integration Low-IF Investigate limits for oscillators Supply voltage Phase noise Tuning range Power consumption Investigate quadrature oscillator topologies Same as above Flicker noise Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 3/16
4 Introduction - Project - cont Low Voltage Studies Justification: Diminishing voltage headroom, ITRS [3] Voltage (V) New compounds will change the parameters such as V T V T prediction 07 V dd V T Minimum transistor channel length (nm) Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 4/16
5 (.! -! / & ' % $ #! " ' *! ),' Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 5/16 " VCO AP ASIC 02: Inductor as current source Little noise of itself No DC-drop Node A swings below ground potential Filtering technique: tuned to 2f0 [5] Ls = 1 (2ωo) 2 (2Cbs + Cls + 2Cgs + Cspar) (1)
6 * 1 *, 2/ 31.?- & # % & # % : / *+,- ' (), " # $! < /3 / >9 =,. / 1 2/ = 1-3? A 2 Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 6/16 4 VCO AP ASIC 02: Amplitude control Bias the diff. stage Prevents source-bulk diodes to turn on
7 VCO RAWCON 02: Low voltage operation varactor study nmos transistors in strong inversion Available for all CMOS processes Bad Q at low voltages Q MOS Vdd=1.0V /w Vth0 Vdd=1.0V /w Vth Vdd=2.0V /w Vth0 Vdd=2.0V /w Vth Vdd=0.7V /w Vth0 Vdd=0.7V /w Vth Q MOS = 1 f 6µ n (V GS V T ) πl 2 (2) Vctrl [V] Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 7/16
8 VCO Summary: 0.25µm CMOS process Agree Systems. AP ASIC 02 1V, 5.5mA, 2.4GHz 15% tuning range -136dBc/Hz 3MHz offset Q of 13.4 (spiral) RAWCON V, 2.8mA, 2.4GHz 13% tuning range -130dBc/Hz 3MHz offset Q of 13.4 (spiral) 920µm 950µm Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 8/16
9 QVCO NORCHIP 03: Quadrature oscillator Topology [6] Low phase error Good phase noise performance Low current consumption Source node filtering technique I- Vctrl I+ Q- Vctrl Q+ OI+ OI+ OQ+ OQ- I- Vctrl I+ Q- Vctrl Q+ Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 9/16
10 QVCO NORCHIP 03: Tuned buffer stage High Q inductor narrow band. Tuning extends band of operation Minimum current Maximum voltage Current (ma) V buf peak (V) V ctrl (V) ibuf fix ibuf var itot fix itot var iqvco fix iqvco var vbuf fix vbuf var V ctrl (V) Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 10/16
11 QVCO NORCHIP 03 Distributed Capacitance Analysis: ɛ 0 ɛ r w s w 6 C ga t 5.5 C 1:tg C 2:tg C gt 5 C 3:tg ɛ r C f C p C f 4.5 C f C gd C f C p C 1:tg = C p + 2C f C p (3) h Capacitance Ratios C 2:tg = C p + C f + C f C p (4) C 3:tg = C p + 2C f C p (5) Width of Trace in µ m Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 11/16
12 QVCO NORCHIP 03 Distributed Capacitance Analysis: ɛ 0 ɛ r w s w C ga C gt t Thick Top Metal t = 3µ m Thin Top Metal t = 0.7µ m ɛ r C f C p C gd C p C f C f C f h Capacitance Ratios C gt = C gt + C gd + C ga C gt (6) C gt Spacing Between Turns in µ m Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 12/16
13 QVCO NORCHIP 03 Distributed Capacitance Analysis: g replacements C sym:tt = C ox:ttl K sym:tt C spi:tt = C ox:ttl K spi:tt ˆk R s1 L s1 PSfrag L s2 replacements R s2 R s1 L s1 C sym:tg = C ox:tg L K sym:tg R sh1 C sym:tg = C ox:tg L K sym:tg R sh2 C spi:tg = C ox:tg L K spi:tg R sh1 K sym:tg = 6 (7) K sym:tt 2 (8) K spi:tg = 3 (9) K spi:tt n 2 (10) Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 13/16
14 QVCO Summary: 0.25µm CMOS process Agree Systems NORCHIP V, 5.4mA 1.8GHz Simulated: 2.0 ma QVCO, and 2.7mA buffer 8.9% tuning range dBc/Hz 3MHz offset Q of 18 (symmetrical) Power Buffer QVCO Source node Amplifier Inductors 1030µm 770µm Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 14/16
15 Summary Project: Oscillator studies for low voltage receiver front-end Two topologies fabricated and measured, a VCO and a QVCO Filtering technique: source node inductor lowers phase noise Amplitude control: preventing source-bulk diodes to turn on MOS varactors: bad Q at low voltages Tuned buffer extends the band of operation Distributed capacitance analysis of on-chip inductors Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 15/16
16 References [1] N. Troedsson and H. Sjöland, High Performance 1V 2.4GHz CMOS VCO, In Proceedings 3d Asian-Pacific Conferance on ASICs 2002, pp , Taipei, Taiwan, August [2], An Ultra Low Voltage 2.4GHz CMOS VCO, In Proceedings 2002 IEEE Radio and Wireless Conference, pp , Boston, Massachusetts, USA, August [3] International Technology Roadmap for Semiconductors - ITRS, [4] J. Rael and A. Abidi, Physical Processes of Phase Noise in Differential LC Oscillators, IEEE Custom Integrated Circuits Conference, pp , [5] E. Hegazi, H. Sjöland, and A. Abidi, Filtering Technique to Lower LC Oscillator Phase Noise, IEEE J. Solid-State Circuits, vol. 36, pp , December [6] P. Andreani, A Low-Phase-Noise, Low-Phase-Error 1.8GHz Quadrature CMOS VCO, In Proceedings of ISSCC 02, pp , February Niklas Troedsson. Competence Center for Circuit Design (CCCD), p. 16/16
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