A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling

Transcription

1 A Fully Integrated CMOS RF Power Amplifier with Internal Frequency Doubling Ellie Cijvat and Henrik Sjöland Department of Electroscience Lund University

2 Presentation outline Introduction PA Analysis Implementation Results Conclusion

3 Introduction Motivation High level of integration on-chip impedance transformation network no discrete RF choke inductor Constant-envelope modulation non-linear PA VCO - PA disturbance frequency multiplication Medium output power class C

4 PA Analysis Frequency Doubling PA A narrowband FM input signal: xt () = Acosω c t Amsin( ω c t) x BB ()t t d where m x BB ()t t d «1 f c 2nd order harmonic: 2f c x 2 () t A 2 DC cos( 2ω c t) msin( 2ω c t) x BB ()t t d same signal information as in fundamental double phase shift

5 PA Analysis Frequency Doubling, Cont d PA stage with cancelled odd harmonics: Differential version: V out V in+ V in- V out+ V out- V in V in 18 V in 9 V in 27

6 PA Analysis Ideal PA response V DD T out DC current: I DC = I max π 2sinα 2 αcosα cosα 2 I max = maximum output current α = conducion angle Vin Vth α [rad] R opt t R L

7 PA Analysis Ideal PA response V DD T out DC current: I DC I max π I max = maximum output current α = conducion angle 2nd order harmonic: = 2sinα 2 αcosα cosα 2 Vin Vth α [rad] R opt t R L α 2 I max 1 I 2 = -- π [ cos 1 cosα 2 θ cosα 2] cos2θdθ = α 2 I max π Drain efficiency for 2nd harmonic: P 2 η 2 = = P DC V DD I V DD I DC = α 1 3α sin-- -- sin ( 2sinα 2 αcosα 2) α -- sin cosα α sin-- 2

8 PA Analysis Ideal PA Response, Cont d Output signals and efficiency vs. conduction angle: I 1 8 Io/Imax I dc efficiency [%] η I 2 2 η alfa (I i = normalized) alfa Assumptions: no knee voltage, optimized load impedance, ideal transformation network, termination of irrelevant harmonics.

9 PA Analysis Non-ideal efficiency Knee voltage V DD V knee η knee = V DD I D V knee V DD Transformation network with L 1 Q factor of 12: η Q = 75%, or -1.2dB. L1 C1 C2 Lbw C3 Combined efficiency example: With: α=2.1, V knee /V DD =.1, Q L1 =12: η tot = η 2 η knee η Q = =.43 = 43%

10 Implementation Stand-alone power amplifier Vi+ Vo+ V out+ V out- Vi- Vo- Vi+ Vo+ Vi- Vo- V o+ V o- V i+ V i- Polyphase network to generate I/Q signals

11 Implementation PA with VCO V out+ f out =2f VCO V ctrl v ctrl + M1 M2 - V out- Vi+ Varactor Vi- Vq- Varactor Vq+ Varactor with continuous and discrete tuning

12 Implementation Chip micrograph PA + VCO VCO PA stand-alone PA active area 1.44 mm 2 PA + VCO 2.25 mm 2

13 Results Stand-alone PA Output power Drain efficiency 15 Stand alone PA; VddDR= Stand alone PA; VddDR= Vdd,PA=3 5 8 Vdd,PA=3.3 Pout [dbm] 5 1 = = Vdd,PA=3 Vdd,PA=3.3 efficiency [%] Pin [dbm] Pin [dbm]

14 Results PA + VCO Varying V DD,VCO : Output power Drain efficiency 1 PA + VCO; VddPA=3.3 (1111) 5 PA + VCO; VddPA= (111) (1111) (111) 3 Pout [dbm] 1 15 efficiency [%] VDD,vco [V] VDD,vco [V]

15 Results PA + VCO, Cont d Varying V DD, PA : Output power Drain efficiency 1 PA + VCO; Vdd,vco=3.3 1 PA + VCO; Vdd,vco= Pout [dbm] 5 1 efficiency [%] Vdd,PA [V] Vdd,PA [V]

16 Results PA + VCO, Cont d Varying Vctrl: Output frequency Output power, drain efficiency 3.3 PA + VCO; Vdd,vco=3.3, Vdd,PA=3.3 1 PA + VCO; Vdd,vco=3.3, Vdd,PA= fout=2*fosc [GHz] Pout [dbm] efficiency [%] Vctrl [V] Vctrl [V]

17 Results PA + VCO, Cont d Frequency response of PA stage: 8 PA + VCO; Vdd,PA= Pout [dbm] fout [GHz]

18 Results Summary maximum PA output power 15 dbm maximum PA drain efficiency 1.7% VCO frequency range active area: stand-alone PA VCO + PA GHz 1.44 mm mm 2

19 Results Comparison to other work Fully integrated CMOS power amplifiers: Pout (dbm) freq. (GHz) efficiency (max) technology output matching other class [2] 33.4 PAE) % (PAE).35um (Bi)CMOS on-chip - E/F3 [3] 2 (max) % (η).8um CMOS on-chip - F? [4] 17.5 (max) % (PAE).35um CMOS partly on-chip - A [5] 9 (@P -5dB ) % (P -5dB ).18um CMOS partly on-chip - AB? [6] 18.6 (@max PAE).9 3% (PAE max).6um CMOS on-chip - C this work 15 (max) % (η).18um CMOS on-chip freq. doubl. C Both the efficiency and the output power are degraded since the 2nd harmonic is taken instead of the fundamental!

20 Conclusions Design and measurement of a CMOS class C PA: with internal frequency doubling fully integrated, including impedance transformation network with drain efficiency analysis 2 test chips: a stand-alone PA and PA with VCO max. drain efficiency = 1.7% max. output power = 15 dbm