Digital Transmitter Revolution: From Polar to Multiphase SCPAs Jeff Walling. Power Efficient RFIC Lab

Transcription

1 Digital Transmitter Revolution: From Polar to Multiphase SCPAs Jeff Walling Power Efficient RFIC Lab

2 Utah PERFIC Lab Wen Yuan Zhidong Bai Dallas Johnson Kyle Holzer Ali Azam Mike Burbidge Darren Korth Sarvani Kunapareddy Jeff Walling DTX Revolution of 5

3 Outline Motivation SCPA Introduction Quadrature Switched Capacitor PA (SCPA) Multiphase SCPA Conclusions Jeff Walling DTX Revolution 3 of 5

4 Spectral vs. Energy Efficiency 100 FM/PM 80 Ocurrences (%) Ocurrences (%) Normalized Envelope (V) OFDM Normalized Envelope (V) Jeff Walling DTX Revolution 4 of 5

5 Spectral vs. Energy Efficiency RF Power Amplifier: dominant single block consumer Smartphones 3-6 PAs Smartphones increase wireless energy demand Jeff Walling DTX Revolution 5 of 5

6 Kahn EER Technique (195) Original Kahn Polar conversion in analog domain Need envelope detector and limiter Modern Kahn Polar conversion in DSP DAC and supply modulator needed Jeff Walling DTX Revolution 6 of 5

7 Digital Frontends: Flexibilty DPA Leverage CMOS strengths Low on-resistance, fast switch Embed DAC functionality in PA Jeff Walling DTX Revolution 7 of 5

8 Outline Motivation SCPA Introduction Quadrature Switched Capacitor PA Multiphase SCPA Conclusions Jeff Walling DTX Revolution 8 of 5

9 Polar DPA: Switched-Capacitor PA (SCPA) Class-D PA with capacitive voltage divider Bottom plate charge redistribution Very linear precision capacitors and low-loss switches Jeff Walling DTX Revolution 9 of 5

10 SCPA: Output Power V OUT n/n P OUT (n/n) 4/π for 1 st harmonic component Linearity determined by capacitor matching and top-plate parasitic n=# capacitors switching N=Total # capacitors V = 1 4 n π N out V DD P out = π n N V R DD out Jeff Walling DTX Revolution 10 of 5

11 SCPA: Power Dissipation Charge/discharge each cycle CV f Fast t r,t f constant current in L C in varies by code, n Jeff Walling DTX Revolution 11 of 5

12 SCPA: Ideal Power Added Efficiency (PAE) Higher efficiency with Higher Q Loaded : Smaller Capacitance Lower CV f Efficiency tradeoff due to L & switch r on Design: Choose P out Choose Q Loaded C is fixed! Resolution: Limited by minimum Capacitor! POUT η = = P + P OUT SC 4n 4n πn( N + Q Loaded n) Loaded Q Q Loaded = πfl R = 1 π fcr Jeff Walling DTX Revolution 1 of 5

13 SCPA: Practical PAE η Ideal η = P = SC P SC + P P + OUT OUT P OUT α β POUT + P + P SWC DR + P CLOCK Ideal η (%) Ideal η vs. Practical η Practical η (%) Practical implementation: Lossy inductor: α SW parasitic R: β Normalized P OUT (dbm) SW parasitic C: Switch driver: Clock distribution: P P P SWC DR CLOCK = ( n / = ( n / = C N ) C N ) C CLOCK SW DR V V V DD DD DD f f f Benefit from scaling Jeff Walling DTX Revolution 13 of 5

14 SCPA Circuit Implementation Jeff Walling DTX Revolution 14 of 5

15 Polar: Bandwidth Expansion How much bandwidth do we need to include? Jeff Walling DTX Revolution 15 of 5

16 Polar: Timing and Close-in PSD Timing mismatch close in mask violation Switching spurs reduced with faster envelope clock Jeff Walling DTX Revolution 16 of 5

17 Outline Motivation SCPA Introduction Quadrature Switched Capacitor PA Implementation and Measurements Conclusions Jeff Walling DTX Revolution 17 of 5

18 Solution: Quadrature SCPA (QSCPA) Sum weighted I/Q vectors in charge domain on C-array No BW expansion! No delay mismatch! No non-linearity due to I/Q interaction Jeff Walling DTX Revolution 18 of 5

19 System Implementation Pout: P out, QSCPA = π n N V R Efficiency: η QSCPA = P P out, QSCPA out, QSCPA + P DD opt SC, QSCPA = 4n 4n πn(n n) + Q Loaded Class-G Improves Efficiency at Backoff Jeff Walling DTX Revolution 19 of 5

20 Voltage Tolerant Switch MP1 VDD-VDD VDD GND-VDD VDD MP MN1 VDD VDD MN3 MP1 VDD No VDD-VDD leakage MP VDD MN1 GND-VDD MN VDD MN GND-VDD MP3 GND-VDD VDD-VDD 0-VDD VDD VDD MP1 MP MN1 MP1 MP MN1 GND-VDD MN MN VDD VDD MP3 VDD VDD 0-VDD VDD GND-VDD VDD VDD VDD MN3 VDD MP3 No gate stress GND-VDD & No Leakage Device reliability Reduce gate stress Reduce leakage Same switch power consumption Jeff Walling DTX Revolution 0 of 5

21 Chip Photograph 65nm RF CMOS (UTM, MiM) Jeff Walling DTX Revolution 1 of 5

22 Area Constraint - Custom Output Inductor Custom Spiral to minimize area Q L = GHz Jeff Walling DTX Revolution of 5

23 Area Constraint - Custom Output Inductor 4n QInd η Limitation on Peak η: Total = η η SCPA Match πn(n n) Q + Q Jeff Walling DTX Revolution 3 of 5 4n + Q Loaded Ind Loaded

24 QSCPA: Static Measurements - GHz Rolloff below GHz external balun Jeff Walling DTX Revolution 4 of 5

25 QSCPA: LTE (10MHz, 64QAM) EVM = 3.6% After D LUT DPD Due to bondwire inductance Jeff Walling DTX Revolution 5 of 5

26 Q-SCPA OOB Noise Offset (MHz) OOB Noise (dbm/hz) ISM Pretty good But need a few more bits to be competitive Jeff Walling DTX Revolution 6 of 5

27 Outline Motivation SCPA Introduction Quadrature Switched Capacitor PA Multiphase SCPA Conclusions Jeff Walling DTX Revolution 7 of 5

28 Reduce Loss - Multiphase SCPA (MP-SCPA) Generate evenly distributed phases Select two adjacent phases to desired 8C output Weight them by selecting number of capacitors No BW expansion! No delay mismatch! 8C Jeff Walling DTX Revolution 8 of 5

29 M-phase Modulation Power drop at ϕ: P3 P n P1 A ( ) sin ( / ) A φ π π = ( n1( φ) + n( φ) ) ( sin( π / M φ) + sinφ ) M P4 ϕ n 1 P0 Maximum power drop: φ = π / M P5 P6 P7 sin ( π π / M ) ( sin( π / M φ) + sinφ ) = cos ( π / M ) P0 P1 Average power drop: P P3 π 1 sin ( π π / M) M sin ( π π / M) dφ = tan( π / M ) M ( sin( π / M φ) + sinφ ) π π[1 cos( π / )] 0 Jeff Walling DTX Revolution 9 of 5

30 Multiphase Comparison All-digital Architecture Power Drop (Max) Power Drop (Average) Phase Modulat or Bandwidt h Expansio n Delay Mismatc h Quadrature 8-phase 16-phase 3-phase -3 db db db db db (36%) db (10%) db (.5%) db (0.6%) Digital Polar 0 db 0 db Why 16-phase? Significant Power Increase No phase modulator Jeff Walling DTX Revolution 30 of 5

31 Multiphase to Quadrature conversion Q n ϕ m θ n 1 m φm = π φm+ 1 = M I = Acosθ Q= Asinθ m m+ 1 π θ < π M M ϕ m+1 I m I m+1 A Q m+1 Q m I m + 1 π M Q MP m m+ 1 I = Im + Im+ 1 = n1cos π + ncos π M M m m+ 1 Q= Qm + Qm+ 1 = n1sin π + nsin π M M MP Q 1 n 1 n m+ 1 m+ 1 Isin π Qcos π M M = π sin M θ θ M m< M π π m m Isin π Qcos π M M = π sin M Jeff Walling DTX Revolution 31 of 5

32 Output Power of Multiphase Q A m m+ 1 I = Im + Im+ 1 = n1cos π + ncos π M M n ϕ m+1 Q m+1 m m+ 1 Q= Qm + Qm+ 1 = n1sin π + nsin π M M ϕ m θ n 1 I m I m+1 Q m I π I + Q = n1 + n + nn 1 cos M P out, n, n P 1 out,max = n + n + nn cos 1 1 N π M P out = π n N V R DD out Jeff Walling DTX Revolution 3 of 5

33 Input Power and PAE Q n A Q m+1 P π n + n + nn cos 1 1 VDD out, n1, n = M N π Ropt ϕ m θ n 1 ϕ m+1 Q m ( n1+ n)( N n1 n) Pin, n1, n = CV DD f N Q Load = 1 πcfr opt I m I m+1 I PAE n, n 1 P out, n, n 1 = = P + P out, n, n in, n, n 1 1 π n1 + n + nn 1 cos M π π 1 n1 + n + nn 1 cos + ( n1+ n)( N n1 n) M 4 Q Load Jeff Walling DTX Revolution 33 of 5

34 Ideal Output Power and PAE Jeff Walling DTX Revolution 34 of 5

35 Multiphase SCPA System Architecture 16 evenly distributed phases adjacent phases to every unit cell Logic selects phase and state for every cell Cell Reuse! Jeff Walling DTX Revolution 35 of 5

36 Chip Photograph 130nm RF CMOS (UTM, MiM) Jeff Walling DTX Revolution 36 of 5

37 MP-SCPA Static Measurements - I P out /PAE vs. Frequency P out vs. Code Center Frequency = 1.8 GHz Efficiency > 0% for 600MHz BW Jeff Walling DTX Revolution 37 of 5

38 MP-SCPA: Static Output vs. Code Two Phases 16 Phases Q 0 Q I I Jeff Walling DTX Revolution 38 of 5

39 MP-SCPA: Measured P out and PAE After DPD Peak Pout = 5 dbm, PAE = 5% Jeff Walling DTX Revolution 39 of 5

40 GHz (10 MHz, 64 QAM) no DPD EVM > 9%-rms Jeff Walling DTX Revolution 40 of 5

41 Digital Predistortion (DPD): Surface Fit I DPD - LUT I DPD - Surface Fit I DPD J k= j k j k IDPD = ak, j k IQ j= 0 k= 0 J k= j k j k QDPD = bk, j k IQ j= 0 k= 0 I Q Surface fit improves DPD accuracy without requiring significant memory Can add memory effects to polynomial Jeff Walling DTX Revolution 41 of 5

42 DPD: Surface Fit vs. LUT Surface Fit vs. LUT I DPD - Surface Fit Q DPD - Surface Fit I DPD - LUT Q DPD - LUT Jeff Walling DTX Revolution 4 of 5

43 MP-SCPA: Digital Predistortion (DPD) - I Jeff Walling DTX Revolution 43 of 5

44 Time Domain LTE Signal with DPD Jeff Walling DTX Revolution 44 of 5

45 MP-SCPA Linearity with DPD AM-AM AM-PM Jeff Walling DTX Revolution 45 of 5

46 GHz (10 MHz, 64 QAM) no DPD D-LUT DPD EVM = 3.5%-rms Jeff Walling DTX Revolution 46 of 5

47 OOB Noise Offset (MHz) OOB Noise (dbm/hz) ISM Pretty good But need a few more bits to be competitive Jeff Walling DTX Revolution 47 of 5

48 Comparison to Prior Art This Work This Work Jin, ISSCC (QSCPA) (MP-SCPA) 15 Alavi, TMTT 14 Lu, JSSC 14 Process (nm) Supply (V) 1./.4 1.5/ Resolution (bit) 8-IQ 7-MP 6-IQ 13-IQ 9-Polar f 0 (GHz) Peak P out (dbm) PAE at peak P out 0% 4.9% 40.4% 4% 38% LTE LTE LTE Single carrier 80.11g Modulation signal 10 MHz, MHz, MHz, 16- MHz, 64-0 MHz, 64- QAM QAM QAM QAM QAM Avg. P out (dbm) Average PAE (%) NA 1.8 EVM (%-rms) NA ACLR (dbc) -30.7/ / /-3.7 <-43 NA Jeff Walling DTX Revolution 48 of 5 Matching On-chip On-Chip No Transformer Transformer

49 Graduate Application Financial support readily available No cost for domestic Ph.D. applicants Foreign applicants pay $15 Fellowships, teaching assistantships Jeff Walling DTX Revolution 49 of 5

50 Summary SCPA utilizes fast, low-loss switches and native precision capacitance ratios Systematic mismatches in polar variants dominate non-linearity! Revisit Q/MP Domain with Digital PAs Sum Multiple Phases in Charge Domain on Capacitor Array No delay mismatch! No bandwidth expansion! Loss can be further reduced by increasing basis phases Still must increase amplitude resolution Jeff Walling DTX Revolution 50 of 5

51 Acknowledgments MP-SCPAs: Wen Yuan Past Collaborators (Original SCPA): Profs. Sangmin Yoo and David Allstot Measurement Support: National Instruments Funding: Qualcomm Research and NSF CCSS: Jeff Walling DTX Revolution 51 of 5

52 References J. S. Walling, S. S. Taylor, and D. J. Allstot, A Class-G Supply Modulator and Class-E PA in 130 nm CMOS, in IEEE J. Solid-State Circuits, 009, vol. 44, no. 9, pp S.-M. Yoo, J. Walling, E. Woo, and D. J. Allstot, A switched-capacitor RF power amplifier, IEEE J. Solid-State Circuits, vol. 46, no. 1, pp , 011. S.-M. Yoo, J. S. Walling, O. Degani, B. Jann, R. Sadhwani, J. C. Rudell, and D. J. Allstot, A class-g switched-capacitor RF power amplifier, IEEE J. Solid State Circuits, vol. 48, no. 5, pp , 013. L. Ye, J. Chen, L. Kong, E. Alon, and A. M. Niknejad, Design Considerations for a Direct Digitally Modulated WLAN Transmitter With Integrated Phase Path and Dynamic Impedance Modulation, IEEE J. Solid-State Circuits, vol. 48, no. 1, pp , Dec C. Lu, H. Wang, A. Goel, S. Son, P. Liang, A. Niknejad, and G. Chien, A 4.7dBm alldigital RF transmitter for multimode broadband applications in 40nm CMOS, in IEEE ISSCC Dig. Tech. Papers, 013, pp M. S. Alavi, R. B. Staszewski, L. C. N. De Vreede, and J. R. Long, A Wideband X13-bit All-Digital I/Q RF-DAC, IEEE Trans. Microw. Theory Tech., vol. 6, no. 4, pp , 014. H. Jin, D. Kim, S. Jin, H. Lee, K. Moon, H. Kim, and B. Kim, Efficient digital quadrature transmitter based on IQ cell sharing, in IEEE ISSCC Dig. Tech. Papers, 015, pp W. Yuan, V. Aparin, J. Dunworth, L. Seward, and J. S. Walling, A Quadrature Switched Capacitor Power Amplifier in 65nm CMOS, in Proc. of the IEEE RFIC Symposium, 015, pp W. Yuan, V. Aparin, J. Dunworth, L. Seward, and J. S. Walling, A Quadrature Switched Capacitor Power Amplifier, IEEE J. Solid-State Circuits, Accepted to appear. Jeff Walling DTX Revolution 5 of 5

53 Backups Jeff Walling DTX Revolution 53 of 5

54 Class-G SCPA: Efficiency Zero SC Power consumption at 0.5V Normalized Higher efficiency at output power lower than 0.5V Normalized Jeff Walling DTX Revolution 54 of 5

55 Class-G SCPA: Improved Code Classic Class-G Improved Class-G V gnd V DD V DD Jeff Walling DTX Revolution 55 of 5

56 Class-G SCPA: Improved Efficiency Zero SC Power consumption at 0.5V Normalized Higher efficiency at output power lower than 0.5V Normalized Higher efficiency at output power higher than 0.5V Normalized Cont. efficiency curve Jeff Walling DTX Revolution 56 of 5