Ten years ago, it was widely accepted conventional wisdom that wattlevel. Next-Generation CMOS RF Power Amplifiers FOCUSED ISSUE FEATURE.

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1 FOCUSED ISSUE FEATURE Next-Generation CMOS RF Power Amplifiers Ali Hajimiri Ten years ago, it was widely accepted conventional wisdom that wattlevel fully integrated power amplifiers (PAs) were not feasible in standard complimentary metal-oxide-semiconductor (CMOS) technology. Today, millions of such devices are commercially produced and shipped every month and are used in hundreds of millions of cellular phones across the world. Such dramatic transition from being considered an impossibility even by most optimistic academics to the obvious future direction to be followed by everyone happened through a series of demonstrations based on new architectures radically different from the known PA topologies applied over more than half a century. PHOTODISC Ali Hajimiri (hajimiri@caltech.edu) is the Thomas G. Myers professor of electrical engineering at the California Institute of Technology (Caltech) and director of the Microelectronics Laboratory. Digital Object Identifier /MMM Date of publication: 14 January /11/$ IEEE February 2011

2 Drain Voltage, Drain Voltage, Drain Voltage, Current Voltage Current Voltage Current Voltage Time Time Time More Current More Voltage Drain Voltage, Current Voltage V bk Time Drain Voltage, Current Voltage V bk Time Figure 1. Constant power scaling: how the same output RF power can be achieved with different levels of voltage and current. CMOS technology presents several challenges to the implementation of a fully integrated high-power radio-frequency (RF) PA, in particular, low transistor breakdown voltage and lossy on-chip passive elements [1]. However, these challenges could be completely trumped by CMOS s most potent weapon of all: a practically unlimited number of transistors to design with. This unlimited number of transistors integrated on a single silicon chip is similar to an army of ants that, when harnessed in unison, can overwhelm the elephant of compound semiconductors and module technology. In fact, the main reason so many inaccurate predictions about the impossibility of fully integrated watt-level CMOS PAs were made in the past was that they were based on the assumption of using the same or similar topologies as those used in the compound semiconductor PAs. This assumption, however, completely discounts the power of parallelism offered by the practically infinite number of transistors available in today s CMOS process technologies. The (practically) unlimited number of transistors available in CMOS not only can be used to generate a large amount of RF power when used in conjunction with innovative combining techniques but also can be further exploited to make highefficiency transmitter architectures for nonconstant envelope modulation schemes. In this article, we will discuss the thought process behind the development of some of the techniques that resulted in the emergence of CMOS as a viable technology for fully integrated watt-level PAs and fully integrated radios. Metal-oxide-semiconductor (MOS) transistors were not considered true RF transistors until the early 1990s, and, even then, the notion of CMOS RF was perceived by many as an academic exercise with no commercial value. However, the continued scaling of the CMOS minimum feature sizes led to faster MOS transistors to the point that it became possible to use them in lower-frequency commercial RF applications at the turn of the century. Unfortunately, this increase in speed (higher f T and f max ) came at the price of lowered breakdown voltages due to the smaller dimensions of the transistors. This was not a major challenge for the small-signal blocks except for some loss of dynamic range, which is often easily justified considering the benefits of integration. Even for most large-signal blocks, such as oscillators and mixer, the loss of voltage swing can be countered with topological modifications and device-size adjustments. However, the limitations imposed by the low-voltage handling capability of the modern MOS transistors is much more severe in PAs and cannot be dealt with as easily, as shown in the following simple example. The ac power P L, delivered to the load R L, is related to the peak voltage amplitude V amp of a sinusoidal source through P L 5 V 2 amp. 2R L Assume that we would like to deliver 1 W of RF power into a 50 V load at 2 GHz. This is a representative February

3 Ten years ago, it was widely accepted conventional wisdom that watt-level fully integrated PAs were not feasible in standard CMOS technology. example of the power levels needed in cellular communication standards Global System for Mobile Communications (GSM) and General Packet Radio Service (GPRS). Using the above expression, we can easily determine the peak-to-peak voltage swing across the load to be 20 V. This is too high a voltage to directly appear across the drain-source of a transistor with small enough feature size to provide the necessary power gain at the frequency of interest. The maximum R load /r 1 r 2 r 3 R load /r 2 r 3 R load /r 3 First Stage Second Stage Third Stage Resonant LC Match (a) 50/N 2 Ω 1:N Impedance Transformer Magnetic Transformer (b) Figure 2. (a) An LC resonant match. (b) A magnetic transformer match. Efficiency, η (%) n = 2 n = 3 Q L = 50 Q L = 15 Q L = 10 Q L = 8 Q L = 5 R load 50 Ω Load Power Enhancement Ratio (E ) n = 4 Figure 3. Passive efficiency versus power enhancement ratio for the optimum number of LC matching sections as a function of Q [1]. voltage handling capability of a single 130 nm CMOS transistor is in the range of a few volts, not tens of volts. For example, if reliability issues in the transistor dictated a maximum voltage swing of 2 V, only a power of 10 mw could be deliver to a 50 V load if it were driven directly by the transistor. Something must be placed between the transistor and the load if higher power levels are needed. The classical solution to this problem is trading current for voltage, as shown in Figure 1. This is achieved through impedance transformation. The concept is quite simple, the instantaneous power is the product of the voltage and current, so the large voltage swing necessary at the load can be obtained using a network of passive elements that transfer it to a lower impedance at the driving transistor. This allows the transistor to have a larger current and a smaller voltage swing. This is advantageous as the voltage handling capability of a single transistor is essentially determined by its physics while its current handling can be adjusted by changing its effective width or the number of parallel transistors. Although this solution can work in theory, the classical impedance transformation approaches are not very effective when the ratio of the power needed at the load 1P L 2 and the power the transistor can directly generate 1P dir 2 is large. This ratio is called power enhancement ratio (PER) [2] and is easily determined to be given by E ; P L P dir 5 r.h p, where r is the impedance transformation ratio and h p is the power efficiency of the passive matching network. (In the earlier numerical example, the power enhancement ratio is 100.) For a multistage inductance-capacitance (LC) matching network [Figure 2(a)] with a fixed inductor quality factor (Q) it is possible to calculate the highest possible passive efficiency as a function of PER for the optimum number of LC matching sections [2]. The result of this calculation is plotted in Figure 3, where the maximum achievable passive efficiency is plotted versus PER for the optimum number of stages designated as n. It is easy to see from Figure 3 that, for a PER of 100, even with an inductor quality factor of 10, the passive efficiency of the output matching network alone is around 50% (achieved with three LC stages). This efficiency will be multiplied by those of the active device and the previous stages, leading to unacceptably low power efficiency for the completed PA. Therefore, it is clear that an integrated LC matching network cannot be used effectively to implement a watt-level CMOS PA due to the strong dependence of the efficiency on the power enhancement ratio. Unlike an LC matching network, a transformerbased matching network s efficiency does not have a strong dependence on the PER, assuming a given Q and 40 February 2011

4 a high coupling factor k [2]. Therefore, a transformerbased matching architecture [Figure 2(b)], where a high k can be maintained, offers a more realistic way of achieving the impedance transformation necessary from a large number of transistors (necessary to carry a lot of current) to a large resistor (needed to deliver a large voltage swing). Several CMOS PAs using transformers with multiple primaries and single secondary performing power combining and impedance matching at the same time have been reported [1] [7]. An intuitive way to see why transformers are superior to LC-matching networks when a large transformation ratio is needed is to note that there is more energy stored in an LC-matching network than a transformer. Consider the example illustrated in Figure 4, where a single stage LC match and a transformer perform an impedance transformation to convert a 1 V, 7 A swing at the drain of the transistor to a 7 V, 1 A one at the load. The reactive energy stored in the LC match [Figure 4(a)] is 49 J, while the reactive energy stored in the transformer [Figure 4(b)] is roughly 7 J. Considering that quality factor is the ratio of the energy stored to the energy dissipated per cycle, we can see that, for a given Q, there is more power loss in the LC match than the transformer simply because there is more energy stored in the LC match. There are some practical limitations to the basic transformer matching. Large transformation ratios result in impractically small inductance on the primary. This, in turn, leads to a larger fractional ohmic loss in the transformer, diminishing some of the intended benefits of such matching scheme. This problem can be dealt with by taking advantage of the isolation between the primary (or primaries) and the secondary windings of transformers to use multiple primary windings to couple to a single secondary. This is highly conducive to the parallelism necessary for providing a large current by the transistor and leads to a very natural way of performing an impedance transformation and power combining, at the same time noting that multiple primaries can be used to couple to the same secondary. The most straightforward approach is to have multiple primaries each driven by an independent amplifier couple to the secondary. This way, multiple amplifiers can be power combined to produce the large voltage swing on the secondary, where no active element exists. While this is a major step forward, it still poses other practical limitations due to the layout geometrical constraints of on-chip inductors. To obtain a reasonable operation at higher power levels, different primary windings of the transformer should be well isolated. This limits the practical layout options, as most classical approaches to such layout result in significant overlap and/or proximity of different primaries and is, hence, suboptimal. One approach that does not suffer from such limitation is using slab inductors (Figure 5) on the primary and The instantaneous power is the product of the voltage and current, so the large voltage swing necessary at the load can be obtained using a network of passive elements. the secondary, where the secondary slab inductors are placed in series in the form of a polygon, as shown in Figure 6. This arrangement minimizes the coupling between the various primaries while allowing the use of slab inductors, which offer a higher Q for a given inductance. Note that the individual differential amplifiers cannot be directly connected across the two terminals of the slab primary. This is because the two terminals of a slab inductor are not in the same physical location, making it impossible to attach a small circuit element 1 V Input Input Resonant Match R in C s 7 A 7 A 7 V L p 1 A 7 V Inductor Stored Energy = 49 J (a) Transformer Match 7 A 1:7 1 V 7 V 1 A 7 A M 1 A Inductor Stored Energy 7 J (b) R load 7 V R load Figure 4. The energy stored in (a) LC match and (b) transformer.???? Figure 5. The connection challenge of a slab inductor. February

5 Output Figure 6. The basic distributed active transformer [1] [3]. Input Secondary Winding Primary Winding Transistors Output Figure 7. The die micrograph of the first distributed active transformer [1]. to both terminals without long interconnecting wires, which produce additional loss and inductance, as illustrated in Figure 5. This is not a problem in the secondary, as the secondary slabs are all in series and form one closed loop in the secondary. However, connecting a capacitor or differential drive transistors across the primary inductors poses a practical problem. Fortunately, this problem can be solved by noting that, when each primary operates in a differential mode, the voltage on the opposite side of a primary would Output Figure 8. A double concentric distributed active transformer with cascode cores [4]. be essentially the same as the voltage on the near end of the adjacent primary inductor. This key observation allows the differential driver and the resonant capacitor to be connected between the neighboring ends of adjacent slab inductors, as shown in Figure 6, resulting in the same circuit behavior as if they were connected across the primary inductors. This structure is known as distributed active transformer (DAT). The first watt-level fully integrated CMOS PA was implemented using the DAT architecture in 2000 and reported in 2001 [1]. It was a 1.9 W, 2.4 GHz CMOS PA implemented using 350 nm CMOS transistors. It achieved a peak power-added efficiency (PAE) of 41%, running off of a 2-V power supply with a die area of 2.6 mm 2. Although it was implemented at the 2.4-GHz industrial, scientific, and medical (ISM), the power levels were clearly suitable for cellular applications such as GSM/GPRS, which were solely addressed by compound semiconductors and exotic module technologies at the time. Its die micrograph is shown in Figure 7. Many different DATs have been successfully demonstrated by several teams [1] [5] over the last decade. While demonstration of a fully integrated watt-level CMOS PA was a major achievement at the time, there still existed several challenges before DAT-based PAs could be deployed as commercial products. Perhaps the most pressing was the need for the PA to run off of a Li-ion battery with a cell voltage of 3.6 V, which would be even higher when the battery is being charged. This posed another breakdown voltage challenge to the PA, which is more of a dc nature as opposed to the ac excess voltage swing problem the original DAT was designed to solve. In the standard DAT (or other classical PA topologies), this intrinsically larger supply voltage directly appears on the drain of the transistors serving as the average value of the ac signal swing on the drain, resulting in larger peak voltages. While it is conceivable to solve this problem with a step-down dc-to-dc converter, it is neither cost-effective nor practical to do so due to the required extra elements (at least one external inductor), the added efficiency hit, and switching noise issues. Therefore, the ideal solution should allow application of the large supply voltage to the PA directly, where it is used in the PA to generate the necessary voltage swing at the output. In a standard single-concentric DAT like the one shown in Figure 6, the dc supply voltage is directly seen by the transistors in the amplifier cores. A first step in solving this problem is using cascode architecture in the cores to divide the voltage swing between the two transistors, where each transistor experiences roughly half of the voltage swing. While this alleviates the problem to some extent, it is not enough to implement a reliable watt-level CMOS PA in a 130-nm CMOS process that may have to withstand supply voltages as high as 6 V while experiencing a load mismatch condition in a worst-case scenario. 42 February 2011

6 This challenge can be overcome by noting that the standard single-concentric DAT of Figure 6 consists of slab inductors that are driven by the differential cores in the corner, effectively creating a virtual ground in the middle of the slab. This is where the supply voltage is applied to the PA. The key insight is that the same virtual ground point can, in principle, serve as the ground connection of the core of another PA. The two PAs can be combined in a concentric fashion where they both couple magnetically to the same secondary loop, as shown in the double-concentric quad-core DAT of Figure 8 [4]. This way, the two sets of DAT primaries are stacked from the dc perspective, while they operate in parallel from an ac point of view. The inner and the outer cores share the same dc current, while they divide the supply voltage almost equally between them. This reduces the voltage experienced by each PA by a factor of two, while they each contribute half of the RF power at the output by magnetically coupling to the secondary. This concentric stacking can be repeated multiple times if necessary. These techniques were used to implement a fully integrated quad-band CMOS PA in a standard 130-nm CMOS process, operating off of a 3.6-V battery to support GSM/GPRS at 850 MHz, 900 MHz, 1.8 GHz, and 1.9 GHz [4]. The PA has an overall PAE of 51% while producing 135 dbm (3.2 W) of output power in the extended-gsm (E-GSM) band. The PAE includes the losses of the PA, on-chip closed loop power control, and the packaging. The high-band PA in the PCS band For a given Q, there is more power loss in the LC match than the transformer simply because there is more energy stored in the LC match. achieves a PAE of 45% while generating up to 33 dbm (2 W) of power at 1.85 GHz. The PA works with power supplies in the range of V and can withstand a 6-V power supply under voltage standing wave ratio (VSWR) of greater than 15:1 under all phase angles, showing no oscillation, breakdown, or long-term degradation over extended periods of testing. The die micrograph of this chip is shown in Figure 9. Figure 9. Die micrograph of the quad-band GSM/GPRS power amplifier of [4]. LBB+ CM LBB PM 0 On-Chip I out + I out Analog BB Replica Linearizer Array LBB+ 6 CM 6 LBB 6 Analog BB Distributor PM 13 C 1 V DD 1:2 PM 14 PM 15 C 2 LO+ LO Digital Controller Digital LO Distributor PAD BB in +BB in Envelope (BB) Bypass Digital Control + Phase (LO) RF Output R Load t t t Figure 10. The block diagram of an RF transmitter based on a power mixer array [11]. February

7 The spectral efficiency of nonconstant envelope modulation schemes has turned them into an attractive option for wireless communications. These demonstrations show the path the fully integrated CMOS PA took from being an oxymoron to a reality, where hundreds of millions of units have been shipped and the prospects for the future shipments are growing. While integration of a PA in CMOS has produced significant cost and area reductions, its real power lies in the ability to integrate the PA and the transceiver on the same die. In addition to the classical benefits of such integration, namely interface elimination and cost/size reduction, such integration provides an opportunity to utilize new architectures not practical with the PA and the transceiver on two separate chips. Such architectures are of particular interest in the case of nonconstant modulation schemes. As an example, the following briefly discusses the power mixer array concept that makes BB+ RF out + RF out LO+ M 7 M 3 M 4 BB M 5 M 8 M 1 LO M 2 M 6 BB Figure 11. The power mixer core used in the power mixer array [11]. (dbm/10 khz) Analog BB Replica Linearizer Array Digital Controller BA Mode, Frequency = 1.75 GHz, BW = 5 MHz, 99.9% PAPR = 8.5 db P Out = dbm Frequency Offset (MHz) EVM = 4.9% Analog BB Distributor Figure 12. The measured spectrum and constellation of WiMax signal [11] operating in baseline analog (BA) mode. 1.6 mm Output Network Power Mixer Array Digital LO Distributor 1.6 mm Figure 13. The die micrograph of the power mixer array of [11]. it possible to implement a CMOS full transmitter for nonconstant envelope modulation schemes. The spectral efficiency of nonconstant envelope modulation schemes has turned them into an attractive option for wireless communications where there is constantly growing demand for scarce spectral resources. Traditionally, in these modulation schemes, the data is modulated at the baseband, upconverted by transmitter to the desired frequency, and, finally, amplified using a linear PA. The DAT-based PAs of [1] [4] were designed for quasi-constant-envelope modulation schemes such as GSM/GPRS and must be modified for use in nonconstant modulation schemes. Although several linearization techniques have been devised over the last half-century (e.g., [8] [10]), many of them are not conducive to a fully integrated implementation because they either require long, low-loss transmission lines, or dc-to-dc converters that need an external inductor and large switching currents. A linear PA is used to maintain the integrity of the modulated signal and avoid detrimental out-of-band emission due to spectral regrowth. Although it has been possible to make linear PAs capable of faithful amplification of such signal, they are usually less efficient than their nonlinear, switching counterparts. The ability to fully integrate a PA in a CMOS process enables attractive alternatives to generate nonconstant envelop modulations without resorting to strictly linear PAs. Many solutions 44 February 2011

8 have been proposed to deal with this problem, such as amplitude elimination and restoration techniques, which could operate based on polar modulation. One such solution is the power mixer array (Figure 10), which selectively applies the local oscillator (LO) signal to a sufficient number of individually linearized power up-conversion mixers, to generate the necessary output power while maintaining linearity and high back-off efficiency [11]. The outputs of the mixers are current combined at their drains, where the nonconstant envelope modulated signal is restored. The modulated signal is impedance transformed into the external load impedance by an on-chip transformer, which does not degrade the spectral purity of the transmitted signal due to its linear nature. Highpower efficiency can be expected from a current-commuting mixer since its lower-tree common-source transistors operate in the switching mode between the triode and the cut-off regions [11]. To obtain highervoltage-handling capability and improved reliability, a double cascade is used, where the top transistor is a thick gate oxide for better voltage handling capability, as shown in Figure 11. The phase information is carried through the phase-modulated LO, which is selectively applied to the desired number of power mixer cores by the digital LO distributor. The choice of how many and which power mixers receive the digital LO is controlled by an on-chip digital controller. The baseband amplitude signal is applied to the middle-tree differential pair, thereby eliminating the need for a supply voltage modulator commonly used in standard envelope elimination and restoration techniques. Analog baseband replica linearizers are used to linearize the differential baseband envelope signal, which is applied to the power mixer cores via an analog distributor. A prototype was fabricated in a standard 130-nm CMOS process [11] with PAE greater than 40% between 1.6 GHz and 2 GHz with a peak of 42% and the output power greater than 1 W over an octave from 1.2 GHz to 2.4 GHz with a maximum output power of dbm. The linearized analog (LA) mode [11] operation achieves an output 1 db compression point of dbm, providing a very large linear range. In the LAmode, a 16 quadrature amplitude modulation (QAM) modulated signal with a symbol rate of 50 ksym/s at 1.8 GHz, an error vector magnitude (EVM) of 5% is measured with an average output power of dbm and an overall PAE of 18%. In the efficient segmented (ES) mode, cores are dynamically activated in units of 4, and the measured PAE improves to 26% with an average output power of dbm and an EVM of 4.5% despite the 16-QAM s nonconstant envelope with a peak-to-average power ratio of 6.7 db. Additionally, wideband code-division multiple access (WCDMA) and worldwide interoperability for microwave access (WiMax) modulated output signals are successfully measured with a linear output power of 128 dbm, a PAE of 30%, and an EVM of 2.9% for WCDMA and maximum linear output power of 125 db, a PAE of 20%, and an EVM of 4.9% for WiMax. The measured spectrum and constellation of a WiMax signal with 5 Msymb/s in the baseline analog (BA) mode is shown in Figure 12. The die micrograph of the power mixer array is shown in Figure 13. It can be seen through these demonstrations that it is indeed possible and beneficial to implement a fully integrated watt-level CMOS PA by using novel architectures that leverage the large number of transistors available in CMOS process technologies. Such integration enables innovative transmitter architectures, leading to power and area efficient radio transmitters in CMOS, enabling the next generation of radio transceivers. References [1] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, A 2.4-GHz, 2.2-W, 2-V fully integrated CMOS circular-geometry active-transformer power amplifier, in Proc. IEEE Custom Integrated Circuits Conf., May 2001, pp [2] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, Distributed active transformer: A new power combining and impedance transformation techniques, IEEE Trans. Microwave Theory Tech., vol. 50, no. 1, pp , Jan [3] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, Fully-integrated CMOS power amplifier design using the distributed active transformer architecture, IEEE J. Solid-State Circuits, vol. 37, no. 3, pp , Mar [4] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G. Hatcher, D. McClymont, and A. Hajimiri, A fully-integrated quad-band GSM/GPRS CMOS power amplifier, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp , Dec [5] D. H. Lee, C. Park, J. Han, Y. Kim, S. Hong, C. Lee, and J. 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Raab, High-efficiency linear amplification by dynamic load modulation, in IEEE MTT-S Int. Microwave Symp. Dig., June 2003, vol. 3, pp [11] S. Kousai and A. Hajimiri, An octave-range, watt-level, fullyintegrated CMOS switching power mixer array for linearization and back-off-efficiency improvement, IEEE J. Solid-State Circuits, vol. 44, no. 12, pp , Dec February