Analysis and Design of a Low phase noise, low power, Wideband CMOS Voltage Controlled Ring Oscillator in 90 nm process

Transcription

1 Analysis and Design of a Low phase noise, low power, Wideband CMOS Voltage Controlled Ring Oscillator in 90 nm process Sweta Padma Dash, Adyasha Rath, Geeta Pattnaik, Subhrajyoti Das, Anindita Dash Abstract Based on differential delay cells a low phase noise, a low power,wide band three stage CMOS voltage controlled ring oscillator (VCRO) has been analyzed which was proposed by Yan and Luong. Using GPDK 90 nm CMOS technology the three stage VCO circuit are realized. In this work the design parameters are varied widely and performance of the circuit are analyzed. This VCO has a very wide operating frequency range from 3.6 GHz to 7.5 GHz, with a tuning range of 52%. Tthe phase noise obtained is about -99 dbc/hz at 1MHz offset from 5.86 GHz and the power consumed by the circuit is 1.7mW. The phase noise of the differential VCO can be improved by cascading more number of stages at the cost of more power consumption. Index Terms Voltage Controlled Ring Oscillator, Radio Frequency Integrated Circuit, Phase Locked Loop, Phase Noise, Tuning Range. I. INTRODUCTION In recent years radio frequency integrated circuits (RFICs) have drawn significant attention due to their wide use in the wireless communication. One of the key block in RFIC is Phase Locked Loop, which contains Voltage Controlled Oscillator. VCO has numerous applications ranging from frequency synthesizers to transceivers. In recent years the design of high performance monolithic VCO has been one of the active area of research and development. In order to fulfill the specifications of the RFIC applications, the VCO should be designed to have high tuning range, low phase noise, low power consumption with Small chip area. A CMOS VCO can be built using LC tuned circuit. LC resonant or ring topology, relaxation circuits VCOs exhibit much better phase noise with having high quality factor (Q) resonant networks. Complexity of the design and its cost increases by using high quality inductors in a CMOS technology. Eddy current problems were introduced in it. Ring Oscillators, do not require on chip inductors and occupy less area than their LC VCO. Generally the tuning range of the LqC oscillator is low i.e. (10 ~ 20) %. The tuning range of ring oscillator is much better (>50%) than LC. Both in phase and quadrature phase outputs are also obtained from ring oscillators. This work analyses the scaled version of VCO architecture which was proposed by Yan and Luong [1] and it is redesigned by the help of CADENCE Virtuso Analog Design Environment by using GPDK 90 nm process.. It is observed to achieve wide operation frequencies with low power consumption to be suitable for RFIC application. The remaining part of the paper is organized as follows. In section II the analysis of the architecture of delay cell used in VCRO and the tuning range and phase noise is discussed. Section III presents the simulation studies of phase noise, tuning range and power consumption of this design. In section IV the results are analyzed and section V provides the conclusions. II. VCRO ARCHITECTURE Higher frequency range can be achieved by using single ended VCRO than its differential counterpart. As the output voltage swing depends on supply voltage it is prone to noises and irregularities in the supply voltage. To achieve wide tuning range, higher operating frequency range, with maintaining a better phase noise performance and low power consumption most challenging task is to reduce the delay of each cell. The block diagram of a differential VCO structure is shown in figure 1. Fig. 1. Three stage Ring VCO For a ring oscillator, there is always a demand for low phase noise, low power consumption and quadrature output for different applications. Many different architectures have been proposed by several authors and analysis are done on them.due to lack of PMOS diode pair to perfectly cancel out the resistive load he delay cell proposed in [2] have less power efficient. The delay cell reported in [3] results in limited frequency tuning range as their frequency is tuned by Vgs of PMOS cross coupled load. Another delay cell proposed in [4] provides better tuning range but not having a better phase noise performance. The delay cell proposed by Yan and Luong [1] provides better phase noise performance, consumes less power and wide frequency tuning range. Hence in this work a fully differential ring oscillator with three stage delay cells, proposed by Yan and Luong [1] is considered for analysis. ISSN: All Rights Reserved 2014 IJSETR 1264

2 The work done in [1] uses 0.5 µm technology and here using 90 nm CMOS technology performance evaluation is done. f osc = 1 g nm 0 2 ( g pm 2 + g pm 0+ c L 2 ) c L 2 (1) The schematic of the delay cell used in this three stage VCRO which is designed in Cadence Virtuso Analog Design Environment is shown in figure 1 and 2. Where gm is the trans conductance of the devices, GL and CL are the load conductance and load capacitance respectively. The frequency of oscillation is tuned by adjusting the trans conductance of the diode connected transistor MP0 and MP3.The maximum and minimum frequency can be calculated as f max = 1 g nm 0 c L (2) f min = 1 g nm 0 2 g pm 0 2 c 2 L (3) By setting the operating frequency as 5.86GHz The design parameters of the transistors in the delay cell are determined by using (1), (2) and (3). For a three stage ring oscillator the single sideband phase noise ( L{f off } ) is calculated in [5]. L{f off } = N. τ 2 rms 8 π 2 f 2 off. i 2 n f v 2 pp c 2 L [4] i 2 n f = 4KTγ(g mn 0 + g mp 0 + g mp 1 ) [5] Fig.2. Delay cell of VCRO Figure 2.shows the schematic of delay cell proposed in [1]. The delay cell consists of two NMOS transistors (NM0 and NM1), two PMOS transistors (PM2 and PM1) to provide positive feedback for oscillation, two diode - connected PMOS (PM0 and PM3) and one PMOS transistor PM4 for frequency tuning of the VCRO. The topology consists of three delay cells for minimization of power consumption and phase noise. The present work as compared to proposed work in [1], extends the VCRO to a three stage structure which expects a tradeoff between phase noise and power consumption. NMOS transistors are used as the input pair to increase the trans conductance to capacitance (gm/c) ratio to achieve higher frequency of operation. Only parasitic capacitors are used to reduce the power consumption and bulk area. By adjusting the trans conductance of the diode connected PMOS, PM0 and PM3 wider tuning range can be achieved. The trans conductance of PM1 and PM2 can be adjusted from zero to a value close to gm of PM0 and PM3 by controlling the current through transistor PM5. The source nodes of transistors PM0 and PM3 is directly connected to supply voltage to maximize the output swing, thereby increasing the carrier power and reducing the noise power and hence the phase noise performance becomes better. The frequency of oscillation of the ring oscillator found in [1] is Where гms is the root mean square of impulse response function (ISF). N is the number of noise sources, f off is the offset frequency for phase noise analysis, VPP is the peak to peak output amplitude, CL is the total output load capacitance, γ is the noise multiplication factor for short channel device, g nm and g pm are the transconductances of the NMOS and PMOS devices, K is the Boltzman constant, T is the temperature in degree kelvin. i 2 n f = Device noise power spectral density. III. SIMULATION ANALYSIS The ring oscillator is simulated in GPDK 90 nm CMOS technology in CADENCE environment. The tuning range, the phase noise and the power dissipation are measured using Virtuso ADE environment. A. Tuning Range The supply voltage is varied and the tuning range is measured at a supply voltage of 1 V, the oscillating frequency is between 3.6 GHz to 7.52GHz, corresponding to tuning range of 52 %. Fig. 3. shows the transient analysis of the three stage ring VCO at a supply voltage of 1V. Figure 4. shows the output frequency spectrum at f o = 5.86GHz.Figure. 5 is a plot of the channel length and the tuning range. This shows that the tuning range of this VCO increases almost linearly with the increase in length of the devices. ISSN: All Rights Reserved 2014 IJSETR 1265

3 Tunning range (%) Frequency(in GHz) International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5, May 2014 Figure.6 shows the measurment results of the operating frequency at different control voltages at supply voltage of 1va obtained is -99 dbc/hz at 1MHz offset frequency, where the operating frequency is 5.8 GHz Vctrl(in V) freq Fig. 6. Control voltage VS frequency Fig. 3. Transient analysis of VCRO C. Power Dissipation In order to maximize the output swing the output node of PM2 and PM3 transistors are directly connected to power supply. Hence power consumption by the circuit obtained is 1.787mW. Fig. 4 Frequency spectrum Fig. 7. Phase noise characteristics at 1MHz offset frequency D. Layout Channel length of devices (nm) Fig. 5. Variation of tuning range of VCO with channel length of the device B. Phase Noise The phase noise behavior of this VCO in SPECTRE is measured and shown in figure 6. The phase noise value Fig. 8. layout of delay cell ISSN: All Rights Reserved 2014 IJSETR 1266

4 The ring oscillator is implemented in 90nm N-well single poly triple metal CMOS technology. In the layout of the ring oscillator delay stages are placed closed to minimize the parasitic capacitance of interconnections. Fig.8 and 9 shows the layout of delay stage and the ring oscillator respectively. IV. ANALYSIS OF RESULTS The performance comparison of different VCO topologies with different design parameters and different technology is presented in table I. the delay used in this VCO operates at the operating frequency of 5.86GHz at a supply voltage of 1v. Fig. 9. layout of ring VCO The frequency tuning range improved than other designs as in [1] and [6]. Phase noise also improved to -99 dbc/hz at 1 MHz offset frequency. TABLE I PERFORMANCE COMPARISION Ref. CMOS(nm) Power supply (v) FTR (GHz) Power (mw) Phase noise (dbc/hz) [1] 0.5um [6] 0.18um This work 90nm V. CONCLUSIONS A 5.8 GHz, 1 V, three-stage CMOS ring oscillator with a wide tuning range, low power consumption has been implemented in 90 nm CMOS technology. This VCO has a wide operating frequency range (3.6 GHz 7.5 GHz), which corresponds to a wide tuning range of 52.11%. The power consumption of this VCO is only 1.7 mw from 1 V supply voltage. The phase noise of this VCO is - 99 dbc/hz, which is observed to improve further by using more number of stages. Hence the architecture presented in [1] when implemented in 90 nm process is demonstrated to have better performance with respect to tuning range, supply voltage, power consumption and silicon area. REFERENCES [1] William Shing Tak Yan and Howard Cam Luong, A 900-MHz CMOS Low-Phase-Noise Voltage-Controlled RingOscillator, IEEETransactions Circuits and Systems II: Analog and Digital Signal Processing,VOL. 48, NO. 2, February [2] B. Fahs, W. Y. Ali-Ahmad, and P. Gamand, A twostage ring oscillator in 0.13-µm CMOS for UWB impulse radio, IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp , May 2009 [3] Y. A. Eken and J. P. Uyemura, A 5.9-GHz voltagecontrolled ring oscillator in 0.18-µm CMOS, IEEE J. SolidState Circuits, vol. 39, no. 1, pp , Jan [4] Changzhi Li, and Jenshan Lin, A 1 9 GHz LinearWide-Tuning- Range Quadrature Ring Oscillator in 130 nmcmos for Non-Contact Vital Sign Radar Application, 2009.IEEE Microwave and wireless components Letters, VOL. 20, NO. 1, January 2010 ISSN: All Rights Reserved 2014 IJSETR 1267

5 [5] A.Hajimiri, S. Limotyrakis and T. H.Lee, Jitter and Phase Noise in Ring Oscillators, IEEE J. Solid-State Circuits,,VOL. 34, NO. 6, JUNE [6] Ahmad Akmal Abd Ghani and Azilah Saparon, A 1.4GHz CMOS Low-Phase Noise Voltage - Controlled Ring Oscillator, The 5th Student Conference on Research and Development SCOReD 2007, December 2007, Malaysia. [7] K.W.Chew, K.S.Yeo and S.-F.Chu. Impact of technology scaling on the 1/f noise of thin and thick gate oxide deep submicron NMOS transistors IEE Proceedings - Circuits, Devices and Systems. Vol: 151, No: 5, pp , October [8] B. Razavi, Design of Analog CMOS integrated circuits, McGraw Hill, Ms. Sweta Padma Dash.The author is currently pursuing Master in VLSI and Embedded system at KIIT University, Odisha. she had completed B.Tech from Modern Institute of Technology and Management, affiliated to Biju Pattnaik University and Technology. Her area of interest is analog and mixed signal ICs. Ms. Adyasha Rath. She is presently pursuing her M.Tech with specialization in VLSI & Embedded Systems under KIIT University. She has received her B.Tech degree from Biju Pattnaik University of Technology in Electronics & Communication Engineering in the year Her areas of interest include low power, high speed analog and mixed mode circuit design. Ms. Geeta Pattnaik.. The author is currently pursuing M-TECH in VLSI and Embedded system at KIIT University, Odisha.. She had completed B.Tech from Seemanta Engineering College affliated tobiju pattnaik University and Technology in the year 2011 in the stream of Electronics & Telecommunication. Her area of interest is low power analog circuits design. Ms. Subhrajyoti Das received her B.Tech Degree in Electronics & Telecommunication Engineering from Mahavir Institute of Engineering & Technology(M.I.E.T) College,Bhubaneswar under Biju Patnaik University & Technology, Odisha in 2011.M.Tech student in VLSI design & Embedded System in School of Electronics Engineering at KIIT University, Bhubaneswar, Odisha. Area of research focus on design of low power, high speed, frequency compensated OPAMP Mrs. Anindita Dash received Bachelor in Engineering in Electronics and Telecommunication from Institute of Technical Education and Research, Utkal University.She is currently pursuing MTech in VLSI and Embedded Design Systems in KIIT University. She is currently working as part-time faculty in CET.Her research interests include high speed and low power techniques,digital synthesis. ISSN: All Rights Reserved 2014 IJSETR 1268