A Si/GaN-based Synchronous Boost DC-DC Converter with High Speed and High Accuracy Peak Current Control Unit

Transcription

1 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, 2017 SSN(Prin) hps://doi.org/ /jsts SSN(Online) A Si/GaN-based Synchronous Boos DC-DC Converer wih High Speed and High Accuracy Peak Curren Conrol Uni Shengpeng Tang, Donglie Gu, Xianzhi Meng, Kexu Sun, Jianxiong Xi, and Lenian He Absrac A 3 MHz Si/ 5 MHz GaN-based 48 W boos converer wih high speed and high accuracy Peak Curren Conrol Uni (PCCU) is presened. Compared wih he convenional Peak Curren Mode (PCM) conrollers, he boos conroller C adops a novel PCCU consising of a fully differenial openloop operaional ransconducance amplifier (OTA) and a ransimpedance amplifier (TA), which can minimize he feedforward delay and enable he converer o operae a a higher swiching frequency. As a resul, he dynamic response and peak curren accuracy of he converer are improved. n addiion, he compensaed oupu of error amplifier in PCCU is moved forward o raise he conrol accuracy furher. This C is designed in CSMC 0.8 um 60 BCD process. The pos-layou simulaion shows ha he boos converer wih he proposed PCCU can shoren he feedforward delay o ns and behave much beer han he convenional one in dynamic response as well as peak curren accuracy. The proposed converer can operae a 3/5 MHz well wih wide duy cycle ranging from o The maximum line regulaion and oupu regulaion is less han 9.6 m/ and 6.72 m/, respecively. ndex Terms Peak curren mode (PCM), peak curren conrol uni (PCCU), high speed, high accuracy, boos DC-DC converer, swiching frequency Manuscrip received Apr. 16, 2017; acceped Oc. 26, 2017 nsiue of LS Circuis Design, Zhejiang Universiy helenian@vlsi.zju.edu.cn. NTRODUCTON As fundamenal power managemen unis, boos converers are widely applied in baery-powered sysems, HE/E powerrain and auomoive power sysems [1], [2]. Among mos common boos conrol schemes, Peak Curren Mode (PCM) has advanages of fas response on variaion of N/OUT, simple loop compensaion and inheren cycle-by-cycle curren limi [3]. Fig. 1 shows a boos converer wih he convenional PCM conrol. n his conrol configuraion, he error amplifier EA compensaed oupu COMP says consan in one swiching period and he sensor oupu S wih peak curren informaion riggers he comparaor CMP o urn off he low side MOSFET wih delay in every cycle. is noiceable ha he swich canno be insanly urned off because of he delay. f he converer operaes a a low speed, he delay exers lile effec on is oupu regulaion. However, when demanded wih high swiching frequency for sysem size reducion and fas response, he convenional PCM boos converer as well as oher PCM based DC-DC converers are difficul o be se operaing a high frequency, due o operaion frequency limied by he curren-sensing circuis delay [4, 5]. According o differen power level and signal processing, pracical curren sensing circuis in PCM can be classified ino hree caegories, as depiced in Fig. 2. The firs one is curren scaled down sensing [4, 6-8]. Fig. 2(a) shows he circui implemenaion in buck converer and (b) gives he corresponding configuraion applied in boos converer. This mehod copies housands of he converer curren direcly wih he scaled down ransisor.

2 772 SHENGPENG TANG e al : A Si/GaN-BASED SYNCHRONOUS BOOST DC-DC CONERTER WTH HGH SPEED AND HGH As shown in Fig. 2(a), he copy ransisor curren M C draws C from DD which is proporional o he inducor curren in high side ransisor M H. Then, his curren flows hrough a resisor o produce an inducorproporional volage S. n order o improve curren copy accuracy, an OPA is frequenly used. However, due o ransisor mismach and resriced OPA bandwidh, he high-frequency capabiliy of his curren sensing scheme is limied. Wha s more, he copy ransisor canno duplicae he inducor curren wihou limi and i is only suied o low volage and low curren (up o hundreds of milliamperes) applicaion. The second mehod is based on resisor (or inducor DCR) high-side curren sensing, which is widely implemened by smar C and works well up o hundreds Fig. 1. Boos converer wih convenional PCM conrol. DD OPA ~ (a) / (c) OPA DD ~ (b) DD LEB LPF OPA DD OPA / Fig. 2. (a) Curren scale down sensing for buck, (b) boos Converer, (c) High-side curren sensing configuraion, (d) Low-side curren sensing configuraion. (d) of kiloherz [9]. As presened in Fig. 2(c), his kind of echnology applied in buck, boos or buck-boos converer uilizes a closed-loop circuiry such as an OPA o ransform double-erminal signal across sensing resisor o single-ended signal S, which can reflec he inducor curren proporionally. Since he circui is subjec o he limied bandwidh of closed-loop negaive feedback, his mehod could no significanly increase he PCM converer swiching frequency. Similar o high-side curren sensing, he hird mehod akes a resisor beween power MOSFET and ground o sense he low-side curren [9, 10], as shown in Fig. 2(d). This mehod is mainly applied in high-volage boos, flyback and buck-boos converer because conroller Cs adoping his scheme can omi a pad and save chip area wihou high-volage device. Due o he presence of parasiic capacior of low-side, he converer can suffer from a large curren spike a he beginning of MOSFET conducion. Therefore, he Leading Edge Blanking (LEB) circui is needed o se a shor ime o avoid sensing he curren spike. Apar from curren spike, due o single-ended sensing, his mehod can be inerfered by high-frequency noise and here is usually a Low Pass Filer (LPF) beween he sensing circuiry and he sensing resisor. Boh LEB and LPF severely degrade he bandwidh of his curren sensing scheme. From he above, i is no suied for high-frequency operaion eiher. Alhough he swiching frequency of PCM boos converer is limied by he curren-sensing circuis menioned above, he demand for lower conrol delay is sill increasing. n he auomoive baery sep-up conversion, he baery volage for boos inpu is no consan during warm crack and jump sar which flucuaes over a wide range. More han ha, he increasing demand for power densiy in auomoive elecronics requires increasing operaing frequency [1], [2]. n order o realize wide inpu and high frequency in sep-up operaion, a high speed boos converer conrol wih a sufficienly shor delay is necessary. To address he concerns above, a boos converer wih high speed and high accuracy peak curren conrol uni (PCCU) is proposed and par of he idea has been presened a he 13h nernaional SoC Design Conference las year [12]. The proposed PCCU can minimize he feedforward delay and move he error amplifier oupu forward, which enable a 48 W boos

3 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, converer o operae a 5 MHz wih excellen dynamic performance and reliable peak curren accuracy. This paper is organized as follows. Secion will firs review he convenional PCM conrol and discuss he operaion principle of he proposed PCCU. A deailed comparison beween PCCU and convenional PCM conrol is also included. Nex, Secion would presen circui implemenaions of he proposed boos conroller. A las, he pos-layou simulaion resuls and conclusions are given in Secion and, respecively.. BOOST CONERTER WTH PCCU 1. Operaion and Delay of Convenional PCM Conrol Before discussing he proposed conrol uni, we should undersand he operaing frequency limiaion of he convenional Peak Curren Mode conrol. Fig. 3 shows he convenional PCM conrol in general DC-DC converer configuraion. Jus as used in a boos converer, he PCM circuiry in he general DC-DC converer urns off he main power swich when he inducor curren exceeds he hreshold se by he error amplifier (EA) oupu. should be noed ha he power swich canno be insanly urned off and he delay in one period is exacly equal o he curren feedforward pah delay. Wihin he black dashed wireframe in Fig. 3, he curren feedforward delay feedforward in PCM converer consiss of 4 pars and each par is denoed in Fig. 4 for he conribuion o oal curren feedforward delay. The firs par SEN is caused by curren sensing circuis. As menioned before, his in a PCM converer is limied by he sae-of-he-ar curren-sensing circuis delay [4, 5, 8]. The second par CMP is due o he comparaor delay which can be minimized under a few nanoseconds wih maure comparaor srucure and process. However, under a fixed process for power managemen C, here is lile improvemen space for delay minimizaion. The hird par BUFF resuls from Logic&Driver block, which is designed o achieve opimum fan-ou and sage number according o he power level of MOSFET. The las par POW also comes from MOSFET. denoes he ime from he beginning of MOSFET gae discharging o he end of miller plaeau. Boh of wo pars are relaed o Fig. 3. The general DC-DC converer wih convenional PCM conrol. curren capaciy (or R ds( on) ) and volage raings. n general, a MOSFET wih small on-resisance ( R ds( on) ) and high block volage can have large parasiic capaciance, which resuling in relaively large BUFF +. POW s worh noing ha he gradually maure Gallium Niride (GaN) FETs [13] showing a superior figure of meri ( QG Rds( on) ) in comparison wih silicon FETs can enable boh high frequency and high efficiency [14]. GaN FETs usually possess ~10 smaller gae charge Q_G han Si [15], which means Logic&Driver and swich discharging delay BUFF POW are dramaically reduced. From differen delay pars discussed above, he oal curren feedforward delay namely PCM minimum on ime _ Fig. 4. Curren feedforward delay decomposiion in a general DC-DC converer. ON _ MN can be expressed as = = (1) feedforward ON _ MN SEN CMP BUF POW.

4 774 SHENGPENG TANG e al : A Si/GaN-BASED SYNCHRONOUS BOOST DC-DC CONERTER WTH HGH SPEED AND HGH As for converer minimum off ime OFF _ MN, i depends on he recificaion device performance and corresponding conrol circuiry. can be sure ha he ON _ MN is normally larger han _ OFF MN, because he laer is achieved wihou curren sensing and comparison process. Therefore, he minimum on ime ON _ MN heoreically deermines he PCM converer maximum swiching frequency, which is given by where f SW _ MAX D MN = (2) ON _ MN D MN denoes he minimum duy cycle of converer. From (1) o (2), if we inend o ge a high-frequency and wide-inpu PCM converer, we shall decrease each par of delay BUF ON _ MN. As discussed above, he curren sensing SEN and buffer & MOSFET discharging delay + can be aken ino accoun o improve conrol POW speed. The BUF + POW delay is dependen on power MOSFET and has lile relaion wih PCM conrol circuis under predefined process and power consumpion. Thus, i is preferred o make some changes in curren-sensing circuis o reduce operaing frequency. 2. Operaion Principle of PCCU ON _ MN for higher Fig. 5 shows a general DC-DC converer wih improved peak curren conrol, he volage loop of his conrol scheme is same as convenional PCM, excep for he proposed PCCU which has significan impac on he conrol feedforward delay. n he blue dashed wire frame, he proposed PCCU includes a differenial open-loop OTA (Operaional Transconducance Amplifier), a differenial open-loop TA (Transimpedance Amplifier) and a comparaor CMP. The OTA receives wo pairs of differenial volage signal SNS _ P, SNS _ N and COMP, REF. Then, i ransforms hese wo pairs of differenial volages ino one pair of differenial curren signals and ransmis hem o he TA. The TA amplifies he differenial curren signals and oupus he differenial volage signals which are direcly conneced o he comparaor CMP. The circui diagram of he proposed PCCU is presened in Fig. 6(a) and a convenional PCM curren sensing and conversion circui diagram is also shown in Fig. 6(b). Corresponding curren deecing nework is implemened by a sensing resisor R SENSE for easy undersanding. As depiced in deep red dashed wireframe for PCCU, he differenial open-loop OTA includes resisors r, 1 r 2 as well as wo branches whose curren is deermined by respecive clamp circuis. As shown in green dashed wireframe, he differenial open-loop TA mainly includes a differenial common-gae amplifier. The branch of curren M supplies he amplifier wih 5 quiescen curren bias. n order o eliminae he quiescen volage difference of he TA inpu, he branch carrying curren M is inroduced o compensae he N 10 1 poenial drop brough by M. M 5 1, M 3, M 11 and M 6 ~ M 9 are high volage MOSFETs, which can improve he curren source performance and wihsand high volage from converer inpu. When he volage difference Fig. 5. The general DC-DC converer wih he proposed Peak Curren Conrol Uni (PCCU). PN beween por SNS_P and SNS_N equals zero, he quiescen volage difference PN1_ Q of PN1 can be expressed as below r r = ( ) r = PN1_ Q COMP REF COMP REF R1 R2 (3)

5 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, = 2 = _ _ _ DD DD DD 10 6 DD bias _ 3 = 4 = (a) (b) Fig. 6. (a) Circui diagram of proposed PCCU, (b) Circui diagram of convenional PCM curren sensing and conversion. where PN1_ Q is normally se below zero. While he inducor curren i L ramps up wih main swich ON, and 1 also increase. As exceeds 1_, PN PN PN PN Q he volage N1 a node N 1 is lower han P1. A his ime, he TA oupu PN 2 increases over zero and he comparaor sars o flip and oupu high level. Afer some delay of pos-sage circuis, he main swich is urned off unil nex oscillaor clock arrives. Obviously, he quiescen volage PN 1_ Q is exacly he inducor peak curren rigger poin resisor r. Considering he sampling R SENSE, he inducor curren hreshold can be expressed as 1 r r = r = ( COMP REF). R TH _ PCCU COMP REF RSENSE R1 R2 SENSE TH _ PCCU Fig. 7 plos some key waveforms when aking he slope compensaion ino accoun o suppress he subharmonic oscillaion. n his configuraion, he inpu volage COMP is varying in DT as well as (4) TH _ PCCU. n his way, he PCCU ses he dynamic inducor peak curren rigger poin and realizes cycle-by-cycle curren wih procedures illusraed above. 3. Comparison wih Convenional PCM Conrol As we can see from Fig. 6, he convenional PCM Fig. 7. Key waveforms in he proposed PCCU. configuraion incorporaes addiional sages, which are uilized o conver he differenial volages from TA o single-ended signal S for peak curren informaion ransfer. n order o mainain he conversion accuracy of he OPA, a buffer is usually insered beween TA and OPA. Obviously, compared wih he proposed PCCU, hese addiional sages would bring exra feedforward delay buffer OPA + for convenional PCM conrol: = + + (5) feedforward _ con feedforward _ PCCU Buffer OPA. Hence, he converer wih PCCU can operae wih a smaller minimum on ime and achieve a higher swiching frequency han convenional converer, as shown in Fig. 8(a). Due o swiching frequency increase, he converer loop bandwidh can be pushed higher. Given a converer wih single-pole conrol sysem, he open-loop ransfer funcion is below:

6 776 SHENGPENG TANG e al : A Si/GaN-BASED SYNCHRONOUS BOOST DC-DC CONERTER WTH HGH SPEED AND HGH _ _ (a) (b) (c) (d) Fig. 8. (a) nducor curren waveforms under maximum swiching frequency of convenional PCM and PCCU-based converers, (b) Load, (c) line responses of convenional PCM and PCCU-based boos converers, (d) Threshold and peak inducor curren of convenional PCM and PCCU-based converers. S G( S) H( S) = A0 1+ ω0 where A 0 is DC gain and ω / 2 0 π is he conrol loop - (6) 3 db bandwidh. We can derive he load sep recovery expression by uilizing (6) and inverse Laplace ransform. The load ransien recovery expression akes he form: where 1+ A ( 0 ) ( ω0+ ω0a0) ( ) = 1+ Ae 0 (7) is he iniial change of load ransien. The ime consan is ( ω + ω A ) , which deermines how long i will ake for he converer o recover he seady sae. The change can be esimaed by Anoher issue of he proposed PCCU is he peak curren accuracy improvemen. From Fig. 6(b), we can obain he inducor curren hreshold convenional PCM conrol: TH _ con where ( ) _ TA, SENSE _ TA (, ) TH _ con under 1 COMP = (9) R A PT A P T is he gain of TA oupu o Compared wih (4), PN. TH _ con is dependen on he TA gain and TA gain or any open-loop amplifier will dramaically varies wih process and emperaure, as included in (9). From (4) o (9), he peak curren peak _ PCCU for a boos converer wih he PCCU can be expressed as: where = (8) πc f 2 ou GBW is he load sep and f GBW is he cross frequency of he converer. A higher cross frequency means a lower load ransien change. As for line ransien response, he expressions are similar and he ime consan is also ( ω + ω A ) From (5), (7) and (8), we can draw a conclusion ha a converer wih lower feedforward delay can operae a a higher frequency, which would expand he conrol bandwidh o achieve good dynamic response. As shown in Fig. 8(b) and (c), under he same load/line ransien, he converer wih he proposed PCCU shows lower undershoo (or overshoo) and shorer recovery ime han he convenional one r r = N + feedforward _ PCCU L peak _ PCCU COMP REF RSENSE R1 R2 (10) and he counerpar of convenional PCM boos converer is given by: peak _ con 1 COMP = + R A PT SENSE _ TA As shown in Fig. 8(d), he (, ) feedforward _ con N L. (11) TH _ PCCU shows sabiliy under process and emperaure variaion. peak _ PCCU rises wih emperaure and slow process because he feedforward delay is increased. Differen from PCCU

7 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, Fig. 9. The funcional block diagram of proposed PCCU. peak curren, peak _ con increases sharply wih emperaure and slow process. Because no only feedforward _ conv is prolonged bu also he hreshold curren is elevaed. Due o he difficuly of predicing and conrolling he peak curren, his propery of convenional PCM conroller is undesirable. 4. Proposed Boos Converer wih PCCU The funcional block diagram of he proposed boos converer wih PCCU is presened in Fig. 9. This work is primarily concerned wih he design of a high-frequency medium power synchronous boos conroller. To compare he performance of he proposed PCCU and he convenional PCM conrol, his boos conroller C is designed o operae in differen feedforward pahs. As depiced in Fig. 9, he PCM conrol pah reuses he TA and CMP of he PCCU. Hence, by idenifying PCCU value, he boos conroller can flexibly access he PCCU or convenional PCM conrol. n addiion, his conroller also provides he opion o drive Si power MOSFETs or power GaN FETs. On he righ op of his block diagram, he adjusable LDO can oupu hree ypes of volage for power FETs according o GaN value. For EPC GaN FETs driving, he LDO oupus 5.2 for low-side driver and 5.8 for high-side driver. The boosrap diode C BOOT forward volage drop is aken ino accoun. The oher is Si Mode wih GaN pin grounded. Thus, he LDO module would oupu 7.5 for boh low-side and high-side Si power MOSFET driving. Apar from hese conrol blocks menioned above, he conroller C also Logic Conrol, Oscillaor as well as oher auxiliary blocks, such as references and proecion circuiry.. CRCUT MPLEMENTATON 1. Error Amplifier Design The error amplifier (EA) is a crucial sage in boos PCM conrol, as i deermines he converer saic and dynamic characerisics. n order o achieve sufficienly small seady-saed error of oupu, a large DC gain of EA is needed. As wih fas load ransien response, he bandwidh of EA should be high enough o enable he conrol loop o reac wih oupu variaion in ime. The OTA (Operaional Transconducance Amplifier) is usually adoped as EA in Peak Curren Mode conrol for is high oupu impedance and larger curren capabiliy, which signifies large DC gain and high bandwidh. Fig. 10 shows he ransisor-level circui of he EA applied in he proposed boos converer. n his circuiry, a wo-sage cascade OTA is used for error amplificaion. The firs sage is for volage-curren ransform and he second sage wih cascode configuraion offers high gain. n order o achieve relaively large swing, he sacked ransisor M 11 and M 12 is exclusively biased by M b5 and

8 778 SHENGPENG TANG e al : A Si/GaN-BASED SYNCHRONOUS BOOST DC-DC CONERTER WTH HGH SPEED AND HGH Fig. 10. The ransisor-level circui implemenaion of error amplifier. M b3, respecively. should be noed ha he EA has grea influence on inducor curren and oupu volage during boos converer power up. Due o low volage level a converer oupu during sar-up, he feedback volage is also a low. f he EA compares his value wih a fixed relaively high volage REF, his EA would ener he sauraion region and oupu he highes volage, which can lead o overlong swiching on ime wihin converer. A his ime, he boos converer would ac as a LC circui wih sep exciaion and he inducor curren and oupu volage can oscillae wih large ampliude. For he boos converer, despie of he large oupu capaciors, here is an inrush curren when he converer is powering up wihou any measures. Because he oupu volage variaion is lagging behind he inducor curren. To solve he power up problem, a ime-varying reference SS is conneced o he gae of anoher P ype ransisor M3 in EA. Thus, M3 and M4 form a compeiive pair, of which lower gae level would ake over he effecive reference inpu. The by charging an exernal capacior source SS. When SS exceeds reference is changed smoohly from SS is obained C SS wih curren REF, he effecive SS o REF. This process is sof sar, which enables boos converer o avoid harsh oscillaion when powering up. The sof sar ime SS is given by SS REFCSS =. (12) SS Apar from ime-varying reference, wo OTAs wih similar srucure are inroduced as depiced righ in Fig. 10. They clamp he cascode OTA oupu wih an appropriae range, which can preven his amplifier enering sauraion region. 2. Buffer and Operaional Amplifier for PCCU n order o suppress he sub-harmonic oscillaion of PCM conrol, slope compensaion is necessary o EA oupu or inducor curren before hey are ransmied o he comparaor. According o power elecronics PCM heory, he absolue compensaion amoun S e should be greaer han half of he curren decreasing slope [16], [17]. For a boos converer, he minimum absolue compensaion amoun can be given below The scheme is subracing O S e MN =. (13) 2L S e from EA oupu. As shown in Fig. 11, his mehod enables he EA oupu and compensaion signal o share a common operaional amplifier, which mainains he symmery of proposed PCCU. n his configuraion, an improved source follower is inroduced o operae wih slope compensaion circuis. The improved source follower is similar o convenional counerpar excep for a curren pah from oupu node o DD, which is implemened by a p-channel MOSFET M 2. The gae of M 1 is conneced o he drain of inpu ransisor M 2. f oupu O varies wih a small incremen, he volage a node P will follow his

9 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, Fig. 11. Desirable circui implemenaion of slope compensaion and Clamper 1 of proposed PCCU. increase and he curren hrough M1 decreases o resis O variaion in urn. Thus, he ineracion in his loop is negaive feedback. The negaive feedback of his improved source follower would benefi in wo ways. The firs is he lineariy beween oupu O and inpu EA. Wih simple signal derivaion, he oupu DC gain of his improved source follower can be expressed as follows v v O m1 m2 o1 o2 =. (14) + EA 1 g g r r g g r r m1 m2 o1 o2 A convenional source follower DC gain is given below v v g r =. (15) 1 + g r O _ con m1 o EA _ con m1 o Compared wih convenional one, he improved source follower possesses a larger DC gain approximae o uniy. This characerisic is desirable because he oupu is inended o follow he inpu O EA linearly jus wih a level shif. The second meri of he improved source follower is he low oupu resisance compared wih he convenional one. The oupu resisance is given below 1 1 = + g m2 ( gm 1+ gmb 1) ro R R r ou S o2 (16) The oupu resisance of a convenional source follower can be expressed as Obviously, 1 R ou R 1 ou _ con = g + g. (17) m1 mb1 is much larger han 1 R ou _ con. Thus, he oupu resisance of improved source follower is much lower han he convenional one. This feaure enables he improved source follower o behave like an ideal buffer sage, a which he oupu volage O says consan when he slope compensaion is drawing curren. should be noed ha he negaive feedback of source follower can be unsable if he pole a node P is near he pole a oupu node O. To avoid his issue, a capacior is conneced o he gae of M 2 o push his pole o he zero. The capaciance is inversely proporional o he size of M 2. For slope compensaion, a curren source comprised of R 1, R 2 and M 5 draws curren from source follower oupu during swiching on ime. The key waveforms are presened a he righ side. When PWM signal is high, M 6 and M 8 are urned off. The volage on capacior ramps up wih consan charge curren volage C C charge and he G also increases wih he same slope. Since he size of M 5 is large (aspec raio > 15), all mos all of G is applied o he resisor R 2. Thus, he decrease rae is expressed as follows COMP

10 780 SHENGPENG TANG e al : A Si/GaN-BASED SYNCHRONOUS BOOST DC-DC CONERTER WTH HGH SPEED AND HGH d R =. (18) R C COMP 1 charge d 2 From (4) and (18), he compensaion curren slope can be obained: d r d R R COMP 1 charge = SENSE R R C 2. (19) As menioned above in Fig. 6, he PCCU has wo prese curren COMP and corresponding Clamper. The curren REF, which is deermined by REF is consan for fixed reference and here is no addiional performance requiremens excep for high gain wih Clamp Operaional Amplifier OP 2. Jus enlarge he DC gain of OP 2 and he oupu curren REF would equal o pre-se value REF / R 2 wih enough accuracy. As for COMP, is value is deermined by a dynamic COMP, which is ramping down in each duy cycle o suppress sub-harmonic oscillaion wihin PCM boos converer. Therefore, he clamp operaional amplifier OP 1 needs o be designed o rapidly rack he imevarying COMP a he oupu. Wihin purple dashed wireframe in Fig. 11, he circui implemenaion for Clamper 1 of PCCU is presened. To mee he requiremens menioned above, a folded cascode OPA is adoped. The dominan pole of he folded cascode OPA comes from node C for is high oupu resisance and large load capaciance. The mos aracive feaure of a folded cascode OPA is ha i only has one non-dominan pole. is he feaure ha enables he folded cascode OPA o operae wih high speed. n addiion o high bandwidh, he folded cascode OPA can oupu medium swing relaed wih inpu. Wih high speed and considerable swing, he folded cascode OPA fis well wih dynamic clamp circuis in he proposed PCCU. should be poined ou ha a capacior wih proper value is needed a node C for sabiliy when enlarging he inpu pair ransisor for high bandwidh.. POST-LAYOUT SMULATON RESULTS The proposed conroller C is implemened wih CSMC um BCD process. The chip layou is Fig. 12. Layou of he proposed boos conroller C. Table 1. Boos converer configuraion presened in Fig. 12. The size of he whole chip is mm and he proposed PCCU including 2 convenional PCM pars occupies an area of mm. The pos-layou simulaion resuls are given below and he circui configuraion is shown in Table Feedforward Delay Si GaN Swiching frequency 3 MHz 5 MHZ npu volage range 6 o 20 6 o 20 Oupu volage Load curren 2 2 Duy-raio range 0.17 o o 0.75 nducor 833 nh/20 mω (HLM-2225CZ-A1) 500 nh/17 mω (ZHLM-252JCZ-A1) Capacior 4.7 µf /5 mω 2.5 µf /5 mω Power MOS SiR836DP EPC2014C GaN PN Conneced o ground Conneced o R LDO PCCU PN Conneced o ground Conneced o R PCCU Noe For comparison, ake EPC2014C For comparison, ake 833 nh and 4.7 uf The feedforward delay disribuion under differen line volages (ranging from 6 o 20 ) of he convenional PCM and he PCCU-based boos converer are depiced in Fig. 13. As we can see, i akes a leas ns for convenional PCM boos converer o ransfer urn-off signal from curren sensing por o low-side gae driver oupu. By conras, he delay for PCCU-based converer is less han ns. The inroducion of PCCU decreases he feedforward delay by 42.2%. As a resul,

11 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, Fig. 13. Feedforward delay disribuion of convenional PCM and PCCU-based boos converers under differen line volages (ranging from 6 o 20 ). Fig. 15. Line response of convenional PCM and PCCU-based boos converer wih 11 /us inpu sep. Fig. 14. Convenional PCM boos converer operaing waveforms wih 5 MHz oscillaor period-doubling. Fig. 16. Load response of convenional PCM and PCCU-based boos converer wih 180 A/us load in= 6. he convenional PCM boos converer canno operae under a high frequency of which he on ime is less han feedforwad _ con. f we force his converer o work under such condiion, i will adap he whole period o mach he proper on-ime. As shown in Fig. 14, he converer is supposed o work under 5 MHz, D=0.16. Due o mach long feedforwad _ con, he converer swiching period auomaically has doubled based on oscillaor cycle. Fig. 17. Load ransien of convenional PCM and PCCU-based boos converer wih 180 A/us load in=9. 2. Line and Load Response The line responses under wo differen configuraions are presened in Fig. 15. As we analyzed above, he boos converer wih proposed PCCU shows beer performance han he convenional one. The recovery ime of he laer is around wice han he former and i induces higher spike during line ransien. Fig show he load response of he wo converers under ree differen line volages. The PCCUbased boos converer can operae beer han he Fig. 18. Load ransien of convenional PCM and PCCU-based boos converer wih 180 A/us load in=20.

12 782 SHENGPENG TANG e al : A Si/GaN-BASED SYNCHRONOUS BOOST DC-DC CONERTER WTH HGH SPEED AND HGH Fig. 19. Maximum inducor curren limi disribuion (running wih maximum prese and fixed ) of convenional comp PCM and PCCU-based boos converer under hree represenaive corners. convenional one under any condiion. 3. Peak Curren Conrol Accuracy Fig. 19 presens he maximum inducor curren limi disribuion of he wo boos converers under hree represenaive corners. As we menioned above, he peak inducor curren of he convenional PCM boos converer can vary sharply wih process and emperaure changes, while he peak inducor curren of he PCCUbased converer is no as sensiive o hese parameers as he convenional one. The maximum peak curren difference in he PCCUbased converer is A, while his difference for he convenional one is up o A. For he maximum rae of change based on _27, his value for he PCCUbased converer is 13.67% and for he convenional PCM converer is 69.21%. Obviously, he proposed PCCU can significanly increase he peak curren conrol accuracy. The above performance parameers of PCCU and convenional PCM conrol are lised in Table 2. ou Table 2. Performance comparison of boos converers wih convenional PCM conrol and PCCU Convenional PCM PCCU npu volage range 6 o 20 6 o 20 Oupu volage Load curren 2 2 Duy-raio range 0.17 o o 0.75 nducor 833 nh/20 mω (HLM-2225CZ-A1) 833 nh/20 mω (ZHLM-252JCZ-A1) Capacior 4.7 µf /5 mω 4.7 µf /5 mω Power FET EPC2014C EPC2014C Feedforward delay 48.5 ns 28.0 ns Swiching frequency 3 MHz 5 MHZ Line response Load in=6 Load in=9 Load in=20 Peak curren limi relaive offse Fig. 20. Line regulaion. 2.2 /240 us 1.7 /200 us 3.4 /198 us 2.6 /200 us 2.0 /198 us 2.0 /200 us 0.96 /206 us 1.04 /202 us 1.6 /100 us 1.2 /119 us 2.0 /98 us 1.8 /98 us 1.3 /100 us 1.2 /96 us 0.67 /100 us 0.67 /102 us 13.67% 69.21% 4. Line and Load Regulaion Fig are relaed wih Si 3 MHz and GaN 5 MHz GaN-based boos converer configuraion. Fig. 20 and 21 show he line and load regulaion of Si/GaN based boos converers. Due o shorer feedforward delay and high bandwidh in a GaN-based boos converer, he conrol can reac wih inpu/oupu more rapidly. Hence, boh line and load regulaion of he GaN-based converer are smaller han he Si-based one. Fig. 21. Load regulaion.

13 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, Fig. 22. Efficiency disribuion of 5 MHz GaN-based boos converer. has dominaed he whole converer loss. Table 3 gives a performance comparison of his paper wih oher PCM DC-DC convers. Among all works, he boos converer wih proposed PCCU possesses he shores maximum feedforward delay, which is around 28 ns. Due o he limied performance of his 0.8 um process, here is considerable room for improvemen if his converer is designed in more advanced process. Similarly benefiing from low curren feedforward delay wih proposed PCCU, his converer has he lowes line regulaion as well as load regulaion for is relaively high loop bandwidh.. CONCLUSONS Fig. 23. Efficiency disribuion of 3 MHz Si-based boos Converer. 5. Efficiency Fig. 22 shows he efficiency disribuion of GaN-based boos converer under differen line volage and load curren. The minimum efficiency appears wih minimum line volage and he lowes load curren. However, in Fig. 23, he Si-based converer shows he worse efficiency when supplying maximum curren wih minimum volage. n his siuaion, he conducion loss n his paper, a Si/GaN-based synchronous boos converer wih a high-speed and high-accuracy PCCU is addressed. Due o open-loop fully differenial amplifiers (OTA, TA) and moving forward of EA compensaed oupu signal, he proposed PCCU can easily realize prey high speed and high accuracy for conrol. Wih he proposed PCCU, a boos conroller for 3/5 MHz 48 W applicaion can be reasonably designed by CSMC 0.8 um 60 BCD process. The pos-simulaion resuls show ha he converer wih he PCCU can decrease he feedforward delay by 42.2% and enable he converer o work wih excellen dynamic response. Furhermore, he inroducion of he PCCU markedly improve he peak curren conrol accuracy under differen corners. The maximum peak curren rae of change based on ypical condiion is only 13.67%. Boh 3 MHz Si/5 MHz GaN converers can work well under wide duy cycles ranging from o The line regulaion and load regulaion is below 9.6 m/ and 6.72 m/, respecively. Table 3. Performance comparison beween PCCU-based boos converer and previous work Process [7] [4] [11] [10] AMS 0.6 µm CMOS process 0.35 µm CMOS process TSMC 0.35 µm CMOS process N/A This work (Pos-Sim) CSMC µm BCD process Swiching frequency (MHz) 0.3 o /5 Oupu power (W) Maximum feedforward delay (ns) N/A <200 > Line regulaion =2 A N/A 10.5 N/A N/A 9.6 Load regulaion N=18 N/A 8 N/A N/A 6.72 Max. full load 89.5% 91% N/A 95% 93.5%/95.4%

14 784 SHENGPENG TANG e al : A Si/GaN-BASED SYNCHRONOUS BOOST DC-DC CONERTER WTH HGH SPEED AND HGH REFERENCES [1] Texas nsrumens Applicaion Noes: "Designing he fron-end DC/DC conversionsage o wihsand auomoive ransiens," [2] Texas nsrumens Applicaion Noes: "Auomoive Wide N DC/DC, Power Soluions for Emerging Applicaions," [3] R. B. Ridley, "A new, coninuous-ime model for curren-mode conrol," in EEE Transacions on Power Elecronics, vol. 6, no. 2, pp , Apr [4] M. Du, H. Lee and J. Liu, "A 5-MHz 91% Peak- Power-Efficiency Buck Regulaor Wih Auo- Selecable Peak- and alley-curren Conrol," in EEE Journal of Solid-Sae Circuis, vol. 46, no. 8, pp , Aug [5] L. Cheng, Y. Liu and W. H. Ki, "A 10/30 MHz Fas Reference-Tracking Buck Converer Wih DDA-Based Type- Compensaor," in EEE Journal of Solid-Sae Circuis, vol. 49, no. 12, pp , Dec [6] Y. S. Kim, B. M. No, J. S. Min, S. Al-Sarawi and D. Abbo, "On-chip curren sensing circui for curren-limied minimum off-ime PFM boos converer," 2009 nernaional SoC Design Conference (SOCC), Busan, 2009, pp [7] Cheung Fai Lee and P. K. T. Mok, "A monolihic curren-mode CMOS DC-DC converer wih on-chip curren-sensing echnique," in EEE Journal of Solid- Sae Circuis, vol. 39, no. 1, pp. 3-14, Jan [8] N. Mirovic, R. Enne and H. Zimmermann, "An inegraed curren sensing circui wih comparaor funcion for a buck DC-DC converer in H- CMOS," 2016 EEE nernaional Conference on Elecronics, Circuis and Sysems (CECS), Mone Carlo, 2016, pp [9] L. Yang, J. Park and A. Q. Huang, "An adapive exernal ramp conrol of he peak curren conrolled Buck converers for high conrol bandwidh and wide operaion range," 2010 Tweny-Fifh Annual EEE Applied Power Elecronics Conference and Exposiion (APEC), Palm Springs, CA, 2010, pp [10] Texas nsrumens, LM5022-Q1 2.2MHz, 60 low-side conroller for boos and sepic, SNSAG9-MARCH [11] W. Huang, X. Yang and C. Ling, "A novel curren sensing circui for Boos DC-DC converer," Anicounerfeiing, Securiy, and denificaion, Taipei, 2012, pp [12] S. Tang, X. Meng, D. Gu, J. Xi, L. He and K. Sun, "A synchronous boos converer wih high speed and high accuracy peak curren conrol uni," 2016 nernaional SoC Design Conference (SOCC), Jeju, 2016, pp [13] Efficien Power Conversion: "Enhancemen-Mode Gallium Niride Technology", [14] M. K. Song, L. Chen, J. Sankman, S. Terry and D. Ma, "16.7 A W 20MHz four-phase GaN DC-DC converer wih fully on-chip dual-sr boosrapped GaN FET driver achieving 4ns consan propagaion delay and 1ns swiching rise ime," 2015 SSCC, 2015, pp [15] A. Seidel and B. Wich, "25.3 A 1.3A gae driver for GaN wih fully inegraed gae charge buffer capacior delivering 11nC enabled by high-volage energy soring," 2017 EEE nernaional Solid- Sae Circuis Conference (SSCC), San Francisco, CA, 2017, pp [16] Abraham Pressman and Keih Billings and Taylor Morey, Swiching Power Supply Design, 3 rd Ed., McGraw-Hill, [17] Sergio Franco, Design wih Operaional Amplifiers and Analog negraed Circuis, 4 h Ed., McGraw- Hill. and GaN drivers. Shengpeng Tang received he B.S. in College of Elecrical Engineering from Zhejiang Universiy, in He is now a maser candidae in nsiue of LS Design from Zhejiang Universiy. His research ineress include DC-DC converers, Donglie Gu received he B.S. in he School of Sofware and Microelecronics from Norh-wesern Polyechnical Universiy, Xian, China, in He is now a Ph.D. candidae in nsiue of LS Design from Zhejiang Universiy. His research ineress include LED lighing and power managemen.

15 JOURNAL OF SEMCONDUCTOR TECHNOLOGY AND SCENCE, OL.17, NO.6, DECEMBER, Xianzhi Meng received he B.S. in College of Elecrical Engineering from Zhejiang Universiy, in He is now a maser candidae in nsiue of LS Design from Zhejiang Universiy. His research ineress include DC-DC converers. managemen. Jianxiong Xi received he M.S. degree in nsiue of LS Design from Zhejiang Universiy, in He is now working in nsiue of LS Design from Zhejiang Universiy. His research ineress include daa converer and power Kexu Sun received he B.S. degree in College of Elecrical Engineering from Zhejiang Universiy, in He is now a Ph.D. candidae in he Deparmen of Elecrical Engineering from Souhern Mehodis Universiy. His research ineress include power managemen and daa converer. Lenian He received he B.S. degree in Deparmen of Elecronic Engineering from Souheas Universiy and he Ph.D. degree in Kanazawa Universiy, in 1983 and 1996 respecively. He is now a professor in nsiue of LS Design from Zhejiang Universiy. His research ineress include power managemen, LED lighing and daa converer.