Three-Level TAIPEI Rectifier Analysis of Operation, Design Considerations, and Performance Evaluation

Transcription

1 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics Three-Level TAIPEI RecifierAnalysis of Operaion, Design Consideraions, and Performance Evaluaion Yungaek Jang, Fellow, IEEE, Milan M. Jovanovi, Fellow, IEEE, Misha Kumar, and Juan M. Ruiz AbsracA new low-cos, hree-phase, four-swich, hree-level, zero-volage-swiching (ZVS), disconinuous-curren-mode (DCM), power-facor-correcion (PFC) boos recifier, for shor named he hree-level TAIPEI recifier, ha achieves a low inpu-curren oal-harmonic-disorion (THD) and feaures ZVS of all he swiches is inroduced. Since in he proposed recifier he volage sress of he four swiches is equal o one-half of he oupu volage, he recifier can uilize swiches wih a lower volage raing ha, generally, have lower conducion losses. To reduce he swichingfrequency range and maximize he ligh-load efficiency, he conrol is implemened by a combinaion of variable-swiching-frequency and phase-shif pulse-widh modulaion (PWM) conrol. Deailed design guidelines for and performance evaluaion of a hree-phase 6-kW prooype designed for he line-o-line volage range from 34 V RMS o 5 V RMS are presened. The prooype recifier exhibis efficiency in he 96-98% range and achieves less han 5% inpu-curren THD over he enire nominal inpu-volage range (38-48 V L-L,RMS ) and above 5% of full load. Index Terms boos converer, power facor correcion, hree phase, disconinuous conducion mode, zero volage swiching, hree level, Taipei recifier, frequency foldback. I. ITRODUCTIO Achieving high efficiency in high-volage applicaions is a major design challenge ha requires he opimizaion of conducion and swiching losses hrough a careful selecion of he converer opology and swiching device characerisics. Generally, swiching losses can be reduced and virually eliminaed by resoring o a variey of resonan or sof-swiching opologies []- [9], whereas he conducion losses can be minimized by employing mulilevel opologies ha enable he use of swiches wih lower volage raings ha generally exhibi lower conducion losses []- [5]. Furhermore, employing opologies wih a reduced number of acive swiches usually resuls in a more cos effecive design []- [7], [6]-[3]. Recenly, a low-cos, hree-phase, wo-swich, zero-volageswiching (ZVS), disconinuous-curren-mode (DCM), powerfacor-correcion (PFC) boos recifier, for shor named he TAIPEI recifier, ha achieves a low inpu-curren oal-harmonicdisorion (THD) and feaures ZVS of all he swiches wihou any addiional sof-swiching circuiry was inroduced [4]. When designed for Japanese/U.S. nominal hree-phase line-o-line Auhors are wih he Power Elecronics Laboraory, Dela Producs Corporaion, P.O. Box 73, 5 Davis Drive, Research Triangle Park, C779, USA, Tel: (99) , Fax: (99) , yungaek.jang@delaww.com volage /4 V RMS where 65-V MOSFETs can be used for he wo swiches, his minimum-componen recifier exhibis excellen performance wih he inpu-curren THD below 5% and efficiency in he 96-97% range, as repored in [5]. However, because he oupu volage of he TAIPEI recifier designed o work wih European/U.S nominal line-o-line volage 38/48 V RMS mus be a leas around 8 V and because he volage sress of he swiches is equal o he oupu volage, he recifier mus be implemened wih swiches ha are raed a leas V. As documened in [4], by employing commercially available silicon carbide (SiC) MOSFET swiches [6], he recifier exhibis excellen performance wih a full-load efficiency of approximaely 98%. However, a relaively high price of SiC swiches diminishes he cos-effeciveness of he circui making i less aracive in 38/48-V applicaions. In his paper, a low-cos, hree-level, ZVS, DCM, PFC boos recifier ha can uilize swiches wih a lower volage raing is proposed. In his hree-level TAIPEI recifier, which employs only four swiches, he volage sress across all he swiches is clamped o one half of he oupu volage. To furher opimize he efficiency by limiing he swiching frequency range, a combinaion of variable-swiching-frequency and phase-shif pulse-widh modulaion (PWM) conrol is employed. The performance evaluaion of he proposed hree-level TAIPEI recifier was performed on a hree-phase 6-kW prooype designed for he lineo-line volage range from 34 V RMS o 5 V RMS. II. THREE-PHASE THREE-LEVEL TAIPEI RECTIFIER Figure shows he proposed hree-phase hree-level ZVS PFC DCM boos recifier. The inpu of he circui consiss of hree boos inducors L, L, and L 3 coupled o hree capaciors C, C, and C 3 conneced in he Y ( sar ) configuraion and he hreephase inpu erminals hrough an EMI filer (no shown in Fig. ). The common poin of he capaciors is conneced o he midpoin beween serially-conneced swich pairs S & S and & and also o he mid-poin of spli oupu capaciors C O and C O. The mid-poin of serially-conneced swiches S & S is conneced o oupu capacior C O hrough clamping diode D C so ha he volage across swich S is clamped o he volage across capacior C O, which is one half of oupu volage. Similarly, he midpoin of serially-conneced swiches & is conneced o oupu capacior C O hrough clamping diode D C and he volage across swich is also clamped o one-half of oupu volage. Clamping capacior C C ha is conneced beween he mid-poins of he wo pairs of serially-conneced swiches is pre-charged o is seady-sae average volage of one-half of he oupu volage hrough he loop consising of capacior C O, he body diode of swich S, pre-charge resisor R PR, and a winding of coupled inducor L C. Capacior C R ha is used o rese he boos-inducor currens is conneced across he serially-conneced pairs of (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

2 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics S D D D 3 V A L S V L B C R C C V L C 3 D C L C C O R C O S S D O O T S D O O D C C C C 3 D 4 D 5 D 6 Fig.. Proposed hree-phase hree-level ZVS PFC DCM boos recifier. swiches and is decoupled from he oupu by coupled inducor L C. Is average volage is equal o he oupu volage since he average volage across he windings of L C is zero. The volages across swiches S and are clamped o he difference of he volages across capacior C R and C C hrough he body diodes of swich and swich S, respecively. Since his difference is equal o onehalf of he oupu volage, he volages across all four swiches in he circui in Fig. are clamped o one-half of he oupu volage. Generally, any kind of swich ha is capable of conducing curren in boh direcions and blocking volage in one direcion such as for example a MOSFET or an IGBT wih an aniparallel diode is suiable for his applicaion. To achieve a low inpu-curren THD, high PF, and a wideload-range sof-swiching of he swiches, he circui in Fig. mus operae in DCM wih a low-bandwidh oupu-volage conrol. This conrol can be implemened by employing various modulaion sraegies of swiches S -. Figure shows iming waveforms of he four swiches of he circui in Fig. for convenional swiching-frequency modulaion. In he swiching-frequency modulaion in Fig., wo pairs of swiches S &S and & are swiched in a complemenary fashion wih a small dead ime D beween heir commuaion insans o enable he pair of swiches ha is abou o urn on o achieve ZVS. Since dead ime D is very small in comparison wih swiching period T S, he effec of he dead ime is negligible, i.e., i can be assumed ha he duy cycle of each swich is approximaely 5%. Because he swiches of each pair operae wih he idenical gae signals as shown in Fig., his modulaion scheme is idenical o ha of he wo-level woswich, ZVS, DCM, PFC TAIPEI recifier [4]. Figure shows anoher modulaion mehod of he swiches in he circui in Fig.. In his modulaion approach, ouer swiches S and are swiched a a consan frequency in a complemenary fashion wih a small dead ime, i.e., wih approximaely 5% duy raio. The duy raio of inner swiches S and, whose urn-on insans are synchronized wih he urn on insans of S and, respecively, is pulse-widh modulaed o provide regulaion of he oupu. While he recifier oupu volage can be fully regulaed by his consan-frequency PWM conrol, he recifier exhibis increased inpu-curren THD and loses ZVS of swiches S and when he duy cycle becomes small. However, by properly combining swiching-frequency modulaion and PWM, a low THD and wide ZVS range can be achieved wih a reduced R PR S S S S O DT S O DT S O O D T S Fig.. Gaing waveforms of swiches S : frequency conrol; pulsewidh-modulaion (PWM); (c) phase-shif PWM. T S (c) frequency range, which brings abou efficiency improvemens a ligh loads. amely, since in he oupu-volage-regulaed converer in Fig. he swiching frequency increases as he load decrease, he frequency range can be reduced by employing swiching-frequency modulaion over he load range from full load down o a pre-deermined level a ligh load and resoring o he consan-frequency PWM for he loads below his level. Moreover, by keeping he urn-on imes of swiches S and consan and decreasing he swiching frequency proporional o he load, i.e., by implemening frequency foldback PWM conrol, addiional reducion of swiching-relaed losses a ligh loads can be achieved. Consan-frequency PWM conrol of he recifier in Fig. can also be implemened by employing he phase-shif PWM illusraed in Fig. (c). In his modulaion mehod, each pair of swiches S & and S & is swiched a a consan frequency in a complemenary fashion wih a fixed duy raio of approximaely 5%. The PWM is achieved by a phase shif of he swiching insans of he ouer swich S & pair wih respec o he corresponding swiching insans of he inner swich S & pair. In his phase-shif PWM, he oupu volage is maximum when phaseshif angle is zero and is zero when phase-shif angle is 8, i.e., T S /. By combining he swiching-frequency modulaion and phase-shif PWM, a conrol mehod for he hree-level TAIPEI recifier ha provides a low THD and wide ZVS range wih a reduced swiching-frequency range can be implemened. D DT S O D O DT S O O (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

3 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics III. AALYSIS OF OPERATIO Figure 3 shows a simplified model of he circui in Fig. along wih reference direcions of currens and volages. To simplify he analysis of operaion, i is assumed ha ripple volages of he inpu and oupu filer capaciors shown in Fig. are negligible so ha he volage across he inpu and oupu filer capaciors can be represened by consan-volage source V A, V B, V C,, and. Also, i is assumed ha in he on sae, semiconducors exhibi zero resisance, i.e., hey are shor circuis. However, he oupu capaciances of he swiches are no negleced in his analysis. Coupled inducor L C in Fig. is modeled as a wowinding ideal ransformer wih magneizing inducance L M and leakage inducances L LK and L LK. I should be noed ha he average volage across flying capacior C R is equal o oupu volage = and he average volage across clamping capacior C C is equal o one half of oupu volage. The circui diagram of he simplified recifier is shown in Fig. 3. The reference direcions of currens and volages in Fig. 3 correspond o he 6- degree segmens of a line cycle when V A >, V B <, and V C <. To furher faciliae he explanaion of he operaion, Fig. 4 shows opological sages of he circui in Fig. 3 during a swiching cycle, whereas Fig. 5 shows he power-sage key waveforms. As can be seen from he gae-drive iming diagrams of swiches S - in Fig. 5, in his explanaion a combinaion of swiching-frequency modulaion and phase-shif PWM is used. In Fig. 5, swiches S and and swiches S and operae in a complimenary fashion wih a shor dead ime beween heir commuaion insans, i.e., wih a fixed duy raio of approximaely 5%. This gaing sraegy enable ZVS of he swiches ha are abou o urn on. The oupuvolage regulaion is primarily done by frequency conrol, excep a ligh loads and/or high inpu volages where phase-shif PWM conrol is used. As shown in Figs. 4 and 5, before swich S is urned off a =T, inducor curren i L flows hrough swiches S and S. The slope of inducor curren i L is equal o V A /L and he peak of he inducor curren a =T is approximaely V A V C i L V B i L L L D V CR D 5 L 3 D 6 C R i S i S i S3 i S4 S S Fig. 3. Simplified circui diagram of proposed hree-phase boos power sage showing reference direcions of currens and volages. The model is valid for 6 -segmen where V A > and V B < V C <. i M L M D C i DC L LK V CC CC D C i DC L LK IL(PK) VA DTS L, () where V A is he line-o-neural volage and T S is he swiching period. Because he dead ime beween urn-off of swich S and urn-on of swich is very small in comparison wih swiching period T S, he effec of he dead ime is negleced in Eq. (). During he ime period beween T and T, curren decreases a a rae of - /(L M L LK ) while curren increases a a rae of (V CR - )/(L M L LK ). Magneizing curren i M is he difference beween currens and. I should be noed ha he magneizing inducance value of coupled inducor L M is designed o be sufficienly large so ha he ripple curren of he coupled inducor does no significanly affec recifier operaion. As shown in Fig., he wo windings of inducor L C are coupled in such a way as o cancel he magneic fluxes from he differenial curren of he wo windings so ha he large magneizing inducance can be obained by a small gap in he core wihou sauraion. Since he effec of he curren ripple of currens and is negligible, hey are no furher discussed, alhough hey are shown in he opological sages in Fig. 4. A =T, when swich S is urned off, inducor curren i L sars charging he oupu capaciance of swich S, as shown in Fig. 4. Because he sum of he volages across swich S and swich is clamped o clamping capacior volage V CC, he oupu capaciance of swich discharges a he same rae as he charging rae of he oupu capaciance of swich S. This period ends when he oupu capaciance of swich S is fully charged and clamping diode D C sars o conduc a =T, as shown in Fig. 4(c) and Fig. 5. Afer =T, swich is urned on wih ZVS. Because clamping dioded C is forward biased, inducor curren i L begins o linearly decrease. The slope of inducor curren i L is equal o (V A - )/L and he inducor curren a =T 3 is approximaely VA D V i O L T3 TS L, () A =T 3, when swich S is urned off, inducor curren i L sars charging he oupu capaciance of swich S, as shown in Fig. 4(d). Because he sum of he volages across swich S and swich is clamped o he volage difference beween flying capacior volage V CR and clamping capacior volage V CC, he oupu capaciance of swich discharges a he same rae as he charging rae of he oupu capaciance of swich S. This period ends when he oupu capaciance of swich is fully discharged and he ani-parallel body diode of swich sars o conduc a =T 4, as shown in Fig. 4(e) and Fig. 5. A =T 5, swich is urned on wih ZVS and inducor curren i L is commuaed from he aniparallel body diode of swich o he swich, as illusraed in Fig. 4(f). Because he body diode of swich is forward biased and swich is on, inducor currens i L and begin o linearly increase afer =T 4. A =T 5, swich is urned on wih ZVS and inducor currens i L and are commuaed from he aniparallel body diode of swich o he swich, as illusraed in Fig. 4(f). This period ends when inducor curren i L decreases o zero a =T 6. To mainain DCM operaion, minimum volage V CR (MI) across flying capacior C R, which is equal o oupu volage, is (MI) VA(PK) VLL, RMS (3) D 3 D (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

4 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics i L i L i L V A V A V A V C V B V C V B V C V B [T -T ] [T -T ] (c) [T -T 3 ] i L i L i L V A V A V A V C V B V C V B V C V B i L i L (d) [T 3 -T 4 ] (e) [T 4 -T 5 ] (f) [T 5 -T 6 ] V A V A V A V C V B V C V B V C V B i L i L i L (g) [T 6 -T 7 ] (h) [T 7 -T 8 ] (i) [T 8 -T 9 ] i L V A V A V A V C V B V C V B V C V B i L i L i L (j) [T 9 -T ] (k) [T -T ] (l) [T -T ] i L i L V A V A V C V B V C V B i L (m) [T -T 3 ] (n) [T 3 -T 4 ] Fig. 4. Topological sages of proposed recifier when V A >, V B <, and V C <. where V A(PK) is he peak line-o-neural volage. I should also be noed ha because during he T 4 -T 6 inerval inducor currens i L and flow in he opposie direcion from inducor curren i L, he average curren hrough swiches and is reduced so ha he swiches in he proposed recifier exhibi reduced power losses. During he ime period beween =T 6 and =T 7, inducor currens i L and coninue o flow hrough swiches and, as illusraed in Fig. 4(g). As shown in Fig. 5, he slopes of inducor currens i L and during his period are equal o -V B /L and (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

5 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics T S S S O O S O O S i L i L V S V S V LC i S DT S S O O S O O i L V A -V CR V A L L V CR -V B L V CR - V CR Fig. 5. Key waveforms of proposed recifier when V A >, V B <, and V C <. V C /L 3, respecively. The peaks of he inducor currens a he momen when swich urns off a =T 7 are approximaely V I B L(PK) DTS (4) L and -V B L IL3(PK) -V C L 3 -V C / L -V B / 3 L ZVS ZVS V C DTS L3 V A - / L - V -V / i CR O O L M i S -V CR / V V -V / A L A O M L L V A L. (5) As i can be seen in Eqs. (), (4), and (5), he peak of each inducor curren is proporional o is corresponding inpu volage as long as duy cycle D and swiching period T S are consan during one half of he line cycle. Afer swich is urned off a =T 7, inducor currens i L and sar o simulaneously charge he oupu capaciance of swich and discharge he oupu capaciance of swich S, as shown in Fig. 4(h). This period ends a =T 8 when he oupu capaciance of swich is fully charged and clamping diode D C sars o conduc a =T 8, as shown in Fig. 4(i) and Fig. 5. Afer =T 8, swich S is urned on wih ZVS. i L V CR -V B V A L L V CR -V B V A L V A - / L i Dc L Because clamping diode D C is forward biased, inducor currens i L and begin o linearly increase. This period ends when inducor curren reaches zero a =T 9. The slopes of inducor currens i L and are equal o (-V B )/L and (- V C )/L 3, respecively. Inducor curren i L a =T when swich urns off is approximaely VB DV i O L T TS. (6) L A =T, when swich is urned off, inducor curren i L sars charging he oupu capaciance of swich, as shown in Fig. 4(k). Because he sum of he volages across swich S and swich is clamped o he volage difference beween flying capacior volage V CR and clamping capacior volage V CC, he oupu capaciance of swich S discharges a he same rae as he charging rae of he oupu capaciance of swich. This period ends when he oupu capaciance of swich S is fully discharged and he ani-parallel body diode of swich S sars o conduc a =T, as shown in Fig. 4(l) and Fig. 5. A =T, swich S is urned on wih ZVS and inducor currens i L is commuaed from he aniparallel body diode of swich S o he swich, as illusraed in Fig. 4(m). Because swiches S and S are on, inducor curren i L begins o linearly increase afer =T. During period T -T 3, increasing inducor curren i L coninues o flow hrough swiches S and S, as shown in Fig. 4(m). Finally, afer inducor curren i L reaches zero a =T 3, a new swiching cycle begins, as shown in Fig. 4(n). Since in he circui shown in Fig. he charging curren of each boos inducor during he ime when he relaed swich is on is proporional o is corresponding phase volage and is discharging curren proporional o he difference of flying capacior volage V CR and he corresponding phase volage, as shown in he inducor-curren waveforms in Fig. 5, average inducor curren <I L (AVG) > Ts of each boos inducor during a swiching cycle is T I S L(AVG) Ts 3L 4D VL, RMS sin ( D), (7) V V CR L, RMS sin where L= L =L =L 3, and is he angular frequency of he line volage. For maximum duy cycle D MAX =.5, average inducor curren <I L (AVG) > Ts, D=.5 of each boos inducor during a swiching cycle is T V V sin I S CR L, RMS L (AVG). (8) Ts, D.5 8L VL, RMS sin By defining inpu-o-oupu volage conversion raio M as V M O (9) VL, RMS and recalling ha he volage across flying capacior C R is equal o oupu volage, i.e., V CR =, average inducor curren <I L (AVG) > Ts in Eq. (7) can be rewrien as V T 4D sin ( D) M I O S L (AVG), () Ts 3L M sin i.e., for D MAX =.5, (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

6 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics V I L(AVG) O T S sin. () Ts, D.5 8L M sin The curren disorion of he average inducor curren in Eq. () is brough abou by he denominaor erm (M sin) and i is dependen on volage-conversion raio M. I should be noed ha he curren disorion of he average inducor curren is also dependen on duy cycle D if duy cycle D is less han.5 as shown in Eq. (). Figure 6 shows calculaed average boos inducor curren <I L-AVG G> Ts wih duy cycle D=.5, D=., and D=. for various TABLE I THD and harmonics of average boos inducor currens shown in Fig. 6. M THD D=.5 3 rd h -99 h THD D= =. 3 rd 5 h -99 h THD D=. 3 rd 5 h -99 h Fig. 6. IV. DESIG COSIDERATIOS (c) Calculaed average boos inducor curren <I L-AVG > Ts for various inpu-o- oupu volage conversion raios M and: D=.5; D=.; (c) D=.. inpu-o-oupu volage conversion raios M. The harmonic conen of he average inducor currens shown in Fig. 6 is summarizedd in Table I. As can be seen from Table I, he 3 rd harmonic is he dominan disorion componen. However, since in he hree-wire power sysems he neural wire is no available (or no conneced), he linee currens canno conain he riplen harmonics (he 3 rd harmonic and he oddd muliples of he 3 rd harmonic). As a resul, he proposed circui exhibis a very low THD and high PF since according o Table I he remaining harmonics conribue less han 3% of oal curren disorion up o D=.. I should be noed ha since he line currens canno conain he hird harmonic, he 3 rd harmonic of he inducor currens flow hrough filer capaciors C - C 3. Finally, i should be noed ha he proposed recifier auomaically balances he volages across he wo oupu capaciors, i.e., no addiional volage-balancing circui is required. aural l volage-balancing is achieved because in he circui in Fig. F he average volages and across capaciors C O and C O are equal o he average volages across corresponding serially- across he windings of inducor L C are zero. Because swich pairs S & S and & are operaed symmerically, heir average volagess are equal o V CR / so ha = =V C CR/. I should be conneced swich pairs S &S and & since he average volages also noed ha clamping volage V CC is equalized o hrough clamping diode D C whenever swich S is urned on. Clamping volage V CC is also equalized o hrough clamping diode D C when swich is urned on. As a resul, he volages across capaciors C C, C O, and C O are equal o one half of oupu volage. Inn his secion, design guidelines for he proposed recifier are oulined using he example prooype circui ha is evaluaedd in Sec. V. The evaluaion prooype of he 6-kW, hree-phase, hree- he level, Taipei recifier has been designed and buil according o following key specificaions: Inpu volage V I : 3-phase, 3-wire, 34-5 V L- -L, RMS Oupu volage : 78 V DC Oupu power P O : 6 kw a nominal inpu (38-48 V L-L,RM MS), 5.4 kw a V I =34 V L-L, RMS Efficiency : > 97% above 5% load (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

7 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics Inpu-Curren THD: < 5% Power Facor (PF): < 98% Power Densiy (PD): > 5 W/in 3 A. Swiching-Frequency Selecion Because he proposed recifier employs variable swichingfrequency conrol, boh is minimum and maximum swiching frequency, i.e., is frequency range, need o be seleced. Generally, he selecion of he minimum swiching frequency is based on he rade-off beween efficiency and size, i.e., power densiy, whereas he maximum frequency is primarily deermined considering limiaions imposed by high-frequency swiching losses and/or gae-drive capabiliy. In his design, he minimum frequency, which occurs a he minimum inpu volage and full load is se a khz, which is abou he lowes frequency ha can make he prooype mee he specified power densiy. The maximum frequency is se o 5 khz o primarily limi he swiching frequency relaed losses. Wih he 5 khz limi, he prooype recifier can regulae he oupu volage a high line down o % load. For loads below % of he full load, he burs-mode or PWM operaion can be applied. B. Boos Inducor Design Based on derivaions in [4], he approximae value of boos inducance L = L = L = L 3 is given by 3 V.48 L O () 8fS M PO M.9 where P O is he oupu power and M is defined in Eq. (9). For seleced swiching frequency of khz a full load of 6 kw and he minimum nominal inpu volage 38 V L-L, RMS, he required value of he boos inducors is approximaely L=7 H. When selecing he core maerial for he boos inducors, i should be aken ino consideraion ha he recifier operaes in DCM so ha he pulsaing currens of he boos inducors produce significanly higher core losses compared o hose in coninuousconducion-mode (CCM) operaion. In addiion, o achieve a low THD, i is necessary o mainain consan slopes of he boosinducor currens, i.e., i is desirable ha inducance value does no change wih he inducor curren. As a resul, ferrie cores wih an air gap are he bes choice since hey offer he lowes core loss and heir permeabiliy does no significanly change under he varying magneic field srengh. To provide packaging flexibiliy, he boos inducor in each phase of he prooype circui is implemened by wo inducors conneced in series. Each inducor was buil using a pair of ferrie cores (PQ-4/4, 3C96) wih 45 urns of Liz wire (.mm, 8 srands) and 8.5 mm gaps a inner and ouer legs o achieve inducance of 85 H. The Liz wire was used o reduce he fringing-effec-induced winding loss near he gap of he inducor cores. For his inducor design, he maximum flux densiy which occurs a full load and he minimum inpu volage is approximaely.3 T. C. Coupled Inducor Design The magneizing inducance of coupled inducor L C should be sufficienly large so ha he ripple curren in he coupled inducor does no significanly affec he recifier operaion. As shown in Fig. by he do convenion, he wo windings of inducor L C are coupled so ha he magneic fluxes from he differenial curren of he wo windings are cancelled. As a resul, a large magneizing inducance can be obained by a small gap in he core wihou sauraion. Coupled inducor L C was buil using a pair of ferrie cores (ETD-54/8/9, 3C96) wih 6 urns of Liz wire (.mm, 5 srands) for each winding and. mm gap. The measured magneizing and leakage inducances are approximaely 3 mh and 8 H, respecively. Peak magneizing curren I M(PK) ha occurs when he swiching frequency is minimum is given by I O M(PK) 8 LM f, (3) S(MI) where L M is he magneizing inducance of coupled inducor L C and f S(MI) is he minimum swiching frequency a full load and he minimum inpu volage. According o Eq. (3), he maximum peak-o-peak magneizing curren a full load (6 kw) and he minimum inpu volage (38 V L-L,RMS ) is approximaely.63 A. The maximum flux densiy a seady sae operaion is approximaely.8 T, which gives pleny of margin from he sauraion flux of he ferrie core. D. Inpu Capacior Selecion Inpu capaciors C -C 3 provide filering of he swichingfrequency ripple of he boos inducor currens and a pah for heir low-frequency riplen harmonics. Since he magniude of he riplen harmonic componen is much smaller han ha of he ac componen of he boos-inducor currens, he raing of he inpu capaciors is essenially deermined by he RMS value of he ac componen of he peak boos inducor curren ha occurs a full load and low line. Since in his design he maximum RMS curren of capaciors C -C 3 is approximaely 5.5 A, a 5-F low-esr film capacior (3 Vdc/6 Vac,.5 khz, khz, ESR=9.8 m) was used for each of inpu filer capaciors C, C, and C 3. E. Selecion of Oher Capaciors The peak curren of flying capacior C R is equal o he sum of he ac componens of he peak boos inducor curren and he peak magneizing curren of coupled inducor L C. Since in his design, he RMS value of he sum does no exceed A, wo 5-F parallel-conneced film capaciors (3 Vdc/6 Vac,.5 khz, khz) were used for flying capacior C R. The curren hrough clamping capacior C C is insignifican because he majoriy of he clamping curren flows hrough clamping diodes D C and D C o he oupu capaciors. A -F film capacior (875 Vdc, 5 khz) was used for clamping capacior C C. Three 56 F / 45 Vdc capaciors conneced in parallel were used for oupu capaciors C O and C O. Because of addiional filering by he leakage inducance of coupled inducor L C and V (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

8 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics capacior C R, he RMS curren hrough oupu capaciors C O and C O is small. F. Semiconducor Device Selecion Because he volage sress of swiches S - is approximaely equal o one half of oupu volage, i.e., i is around 39 V, i is necessary o use swiches ha are raed a leas 5-V o mainain desirable design margin of %. The swiches conduc he peak curren of approximaely 3 A. As a resul, in he prooype circui a IPW65R4CFD MOSFET (V DS = 65 V, R DS =.4, C OSS =4 pf, Q rr =.9 C) from Infineon was used for each swich. Since inpu diodes D -D 6 mus block he peak volage ha is approximaely equal o oupu volage, i.e., i is around 78 V, and conduc he peak curren (approximaely 6 A), an C4DD diode (V RRM = V, I FAVM = A) from Cree was used for each diode. G. Conrol Implemenaion The conrol of he prooype recifier was implemened by TMS3F87 DSP from TI. Since he recifier naurally provides racking of he average inducor curren wih he corresponding phase volage, his DSP conrol consiss only of a low-bandwidh feedback loop ha regulaes he oupu volage. Figure 7 shows a simplified block diagram of he conroller. As i can be seen in Fig. 7, variable-frequency conrol is implemened by a volage-conrolled oscillaor (VCO) whose frequency is deermined by he oupu V CTRL of volage conroller G C which processes he error beween sensed oupu volage (SES) and is reference (REF). In addiion, he conroller implemens sof-sar and frequency-foldback conrol by employing a combinaion of frequency modulaion and phase-shif PWM. Alhough sof-sar conrol can be implemened by swiching-frequency conrol alone, i.e., by slowly decreasing he swiching frequency from he maximum frequency oward he required conrol frequency, combining i wih PWM conrol enables more conrollable and smooh sar up. However, he frequency foldback conrol ha is used o exend he minimum-load regulaion range and/or improve ligh-load efficiency requires PWM conrol. amely, frequencyfoldback mode, i.e., he operaion where he swiching frequency is decreased as he load is reduced, can only be implemened if PWM conrol is also employed o provide regulaion a a reduced oupu power. In he implemenaion in Fig. 7, he drive signals of swiches S - are obained by using digial pulse-widh modulaor (DPWM) wih wo idenical synchronized digial carrier ramps ha are generaed by couning DSP clock periods T CLK. Since he carrier ramp period T S = CAR T CLK, where CAR is he number of clock periods, carrier frequency f S is proporional o / CAR. As shown in Fig. 7, he ramp frequency is se by muliplexer MUX FREQ ha based on he sae of sof-sar flag Flag SS and frequency-foldback flag Flag selecs eiher he frequency of VCO, or he frequency of frequency-foldback VCO, or he frequency of he sof-sar circui. The number of clock periods CAR is obained by finding he reciprocal value of he MUX FREQ oupu. The VCO ransfer funcion is se by he selecion of is maximum frequency, i.e., minimum coun number, and gain K VCO. According o Fig. 7, he VCO oupu is given by KVCO VCTRL (4) VCO MI Since fvco TCLK fvco (5) VCO fclk and f T MAX CLK fmax, (6) MI fclk relaionship in (4) can be wrien as fvco f MAX KVCO VCTRL. (7) fclk fclk As i can be seen from (7), he normalized frequency of he VCO wih respec o f CLK is a linear funcion of conrol volage V CTRL wih negaive slope K VCO. As a resul, he VCO frequency increases as he conrol volage decrease, i.e., as he load curren decreases. The drive signals of complemenary swiches S and ha always operae wih 5% duy cycle are obained by comparing he carrier ramp wih one-half of is coun value CAR, i.e., wih.5 CAR, as shown in Fig. 7. The drive signals of complemenary swiches S and ha also always operae wih 5% duy cycle bu also can be phase shifed wih respec o swiches S and are obained by comparing he carrier ramp wih.5 CAR - PS and CAR - PS, where PS is proporional o phase shif, i.e., PS = (/36) CAR. Since he PS range is from o.5 CAR, phase shif is in he -8 range. The PS value ha is seleced by MUX PS is deermined eiher by he sof-sar or frequency foldback circui. The reason for he ramp comparison wih wo levels is o preserve 5% duy cycle of swiches S and during phase-shif operaion. amely, he ramp comparison wih.5 CAR - PS defines he beginning of he off ime, whereas he comparison wih CAR - PS defines is end. Since he difference beween he wo levels is.5 CAR, i.e., i is equal o one-half of he digial ramp heigh, he drive signals for swiches S and operae wih 5% off ime, i.e., wih 5% duy cycle. The frequency foldback circui is acivaed a ligh loads whenever oupu of he conroller V CTRL falls below reference level V CTRL(REF) and frequency foldback flag Flag is se o. The frequency foldback circui consiss of he frequency-foldback VCO, VCO, and he preprogramed phase shif as a funcion of he VCO s frequency. The VCO ransfer funcion is se by he selecion of is minimum frequency, i.e., maximum coun number MAX and gain. I should be noed ha opposie from VCO, VCO is se up o decrease he frequency as he load decreases, i.e., is normalized frequency is a linear funcion of conrol volage V CTRL wih posiive slope K VCO given by fvco fmi KVCO VCTRL. (8) fclk fclk In he frequency-foldback mode, he oupu volage is regulaed by he phase-shif modulaion illusraed in Fig. (c) by employing open-loop conrol where he phase shif is preprogramed as a (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

9 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics S S DSP TMS3F87 f CLK = 6MHz DPWM Ramp Ramp TCLK DIGITAL RAMP CAR T CLK FREQUECY SOFT START X.. SS PS 8 PREPROGRAMMED PHASE SHIFT 6 7 o SS PS 4 36 o T CLK = 6.67ns DIGITAL RAMP o 5 CAR 6 4 Ts Ts CAR Flag SS Flag MUX FREQ = SS f SS [khz] 3 3 T CLK T SS = =44 o f SS f CLK SS Flag SS SS MUX SS VCO MI MAX ssramp K VCO VCO ssramp MI MAX SOFT START FREQUECY T sep T SS COTROLLER ADC V CTRL (SES) G C (z) FSR (REF) SESIG K D FSR=3.3V K D =.5 78 V o FREQUECY FOLDBACK Flag PS Flag Flag SS MUX PS SS PS PS PREPROGRAMMED PHASE SHIFT PS =73 o 58 o o 8 o VCO o 5 f VCO [khz] 4 = VCO VCO MAX T CLK T VCO = V CTRL(REF) K VCO f VCO f CLK VCO Fig. 7. Simplified block diagram of DSP-based conroller employed in prooype circui of proposed recifier (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

10 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics funcion of he foldback frequency. Generally, any relaionship where he phase shif is monoonically increasing as he foldback frequency decreases can be used. Figure 7 shows preprogramed phase shif dependence on he foldback frequency. As can be seen, he phase shif increases as he foldback frequency decreases. The phase-shif dependence on frequency shown in Fig. 7 is obained by assuming a linear relaionship beween phase-shif coun PS and swiching-period coun VCO, i.e., PS.5(VCO 4), where 4 VCO 3, which corresponds o he 5--kHz foldback-frequency range. In he prooype circui, he maximum phase shif of PS was se a 3 VCO minimum frequency fvco khz. This phase shif corresponds (8 73 ) o he minimum duy cycle of DMI.. 36 The sar-up of he circui is managed by he sof-sar circui which gradually decreases he swiching frequency from he maximum frequency down o ha required by he regulaion loop. As shown in Fig. 7, sof-sar frequency / SSRamp is decreased by increasing swiching period coun SSRamp from MI o MAX by one coun every ime sep sep. For a given frequency range, i.e., for given MI and MAX, he duraion of ime sep sep is deermined by desired maximum sof-sar duraion T SS, as sep =T SS /( MAX - MI ). In he experimenal prooype circui he frequency sof-sar range is from 3 khz ( MI =) o khz ( MAX =3) and sep =ms which resuls in T SS = 5.6s. As shown in Fig. 7, during he sof sar normalized sof-sar frequency / SSRamp =f SS /f CLK is compared wih VCO s normalized frequency / VCO =f VCO /f CLK and he higher frequency is seleced by MUX SS which is hen passed o he DPWM since during sar up Flag SS = and Flag =. Generally, a sar up, he VCO frequency is a he minimum unil he conroller sars responding by decreasing is oupu and he VCO frequency sars increasing. Since a he beginning of sar up he sof-sar frequency is greaer han he frequency of VCO, he sof-sar circui deermines he swiching frequency. When he frequency of VCO becomes larger han he decreasing sof-sar frequency, he conrol loop deermines he swiching frequency. This implemenaion of sof sar offers seamless ransiion from he sof sar conrol o he feedback-loop conrol. Furhermore o enable as smooh as possible sof-sar conrol, he open-loop phase-shif conrol is also implemened alongside he frequency-modulaion conrol. As shown in Fig. 7, he preprogramed sof-sar phase shif is maximum a he maximum sof-sar frequency and decreases as he sof-sar frequency decreases. The phase-shif dependence on frequency shown in Fig. 7 is obained by assuming a linear relaionship beween phase-shif coun SS PS and swiching-period coun SS, i.e., SS PS.(SS 6), where SS 3, which corresponds o he 3--kHz sof-sar frequency range. In he prooype circui, he maximum phase shif of SS PS was se a maximum SS frequency f SS 3 khz. This phase shif corresponds o he (8 44 ) minimum duy cycle of DMI.. 36 The conroller is design by applying analog-redesign approach, i.e., by designing conroller G C in he s-domain and mapping i in he z-domain. The equivalen s-domain volage-loop gain of he conrol loop of he experimenal converer is st T D V (s) KD GC(s) KVCO GPS(s) e FSR KD GC(s) KVCO GPS(s), (9) FSR where K D is he sensing gain of he oupu volage, FSR is he fullscale range of analog-o-digial (ADC) converer, G PS (s) is he lowfrequency power-sage small-signal ransfer funcion, and e is std he oal digial-loop delay ha includes ADC conversion ime, DSP compuaional ime, and he delayed updae of DPWM o achieve synchronizaion o he reseing of DPWM ramp. Since in he experimenal circui he sampling frequency f SAMPL =5 khz is much greaer han he desired -Hz bandwidh of he loop, he digial-loop delay can be negleced since i has no measurable effec on he volage-loop phase margin. For a resisive load, power sage small-signal ransfer funcion G PS (s) is a single-pole ransfer funcion GPS(s) KPS. () s fpo By using small-signal measuremens, i was esimaed ha for he experimenal circui a full-power of 6-kW and a line-o-line volage of 38 V, power-sage gain K PS =.5 and power-sage pole frequency f P =.4 Hz. To compensae he loop, wo-pole one-zero conroller, i.e., PI conroller wih high-frequency pole, was used. The conroller s s- domain ransfer funcion is s K f G Z C(s). () s s fp To obain -Hz bandwidh, he conroller parameers were seleced as K=36, f Z = Hz, and f P = khz. Since he sampling frequency in he prooype circui is f SAMPL = 5 khz, he conroller s z-domain ransfer funcion obained by bilinear (Tusin s) ransformaion ha is coded in he DSP is GC(z) z.88 z..598 z.598 z. () Finally, i should be noed ha he conrol signals a he oupu of he DSP conroller are coupled o he gae-o-source volage of he corresponding swiches wih SI835 drivers from Silicon Labs and ha he oupu overvolage proecion and swich curren overcurren proecion are implemened ouside he DSP, i.e., by using analog comparaors. Curren-sensing ransformers wih urns raio : were used for sensing curren of he swiches (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

11 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics V. EXPERIMET TAL RESULTSS The performancee of he proposed recifier was evaluaed on a 6-kW prooype circui ha was designed according o he key specificaions lised in Sec. IV. Figure 8 shows he power-sage schemaics of he experimenal prooype circui along wih he componen informaion. Figure 9 shows he measured volage waveforms of clamping capacior C C and wo serially conneced oupu capaciors C O and C O during sar up. Because volages across hose capaciors limi he peak volage sresses of he primary swiches, volages V CC,, and should always be equal o one half of he oupu volage even during he sar up. Figure 9 shows he V CC,, and volage waveforms immediaely afer he ac source is conneced and Fig. 9 shows he same waveforms afer he conroller is subsequenly urned on. As i can be seen from Figs. 9 andd, during he enire sar-up period, volages,, and V CC C are equal o one half of he oupu volage. Figures and show he measured inpu-curren waveforms of he experimenal circui operaing a full power from 38V L-L L, RMS and 48 V L-L, RMS inpu, respecively. I should be L A -L 3B PQ4/4-3C96 Liz. dia. x 8 srands 45 urns, 85 H D -D 6 C4DD D D D 3 C R x 5 F/.3 kv Film S L C ETD54/8/9-3C96 Liz. dia. x 5 srands 6 urns : 6 urns L M =3 mh, L LEAK = 8 S - IPW65R4CFD D C H V A V B V C i L L A L A i L L 3A L B L B L 3B C R S C C C C F/875 V Film L C C O D C C O C C C 3 C C 3 5 F/.3 kv Film D 4 D 5 D 6 D C, D C RHRP56 C O, C O 3 x 56 F /45 V Aluminum Fig. 8. Experimenal prooype circui of proposed recifier. Fig.. Measured inpu-curren waveforms a full power for hree-phase line-o- line RMS inpu volage: 38 V; 48 V. Time scale is 5 ms/div. Fig. 9. Measured volage waveforms of clamping capacior C C and oupu capaciors C O and C O during sar up: afer ac source is conneced and afer conrollerr is urned on. Time scale is 4 ms/ /div. Fig.. Measured waveforms of inducor currens i L, i L, and a full power for hree-phase line-o-line RMS inpu volage: 38 V; 48 V (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

12 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics Fig.. Measured waveforms of swich volages V S, V S, VS3, and V S4 for hree- Fig. 4. Measured inpu curren waveforms and volage waveformss of phase line-o-line RMS inpu volage: 38 V; 48 V. clamping capacior C C and wo serially conneced oupu capaciors C O and C O wih phase A volage waveform when recifier delivers 3 kw from hree-phasee line ha iniially has balanced 38 V L-L. Afer ransien command, phasee A line is disconneced. Fig. 3. Measured waveforms a full power for hree-phase line-o-line RMS inpu volage 5 V of: : swich volages V S, V S, V S3, and V S4 ; inducor currens i L, i L, and. I should be noed ha phase shif beween swich pairs S & and S & is increased o reduce swiching frequency a above nominal inpu volage 48 V.. noed ha inpu currens i A, i B, and i C are measured beween he hree-phase AC source and he inpu EMI filer of he recifier which is no shown in Fig. 8. The measured full-power THDs of he inpu currens are below 3% for boh inpu volages. Figure Fig. 5. Measured inpu curren waveforms and volage waveformss of clamping capacior C C and wo serially conneced oupu capaciors C O and C O wih phase A volage waveform when recifier delivers 3 kw from hree-phasee line ha iniially has balanced 38 V L-L. Afer ransien command, one phase volage drops o zero. shows he measured curren waveforms of boos inducors L, L, (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.

13 This aricle has been acceped for publicaion in a fuure issue of his journal, bu has no been fully edied. Conen may change prior o final publicaion. Ciaion informaion: DOI.9/TPEL , IEEE Transacions on Power Elecronics and L 3 a full power. The measured waveforms and he ideal waveforms in Fig. 5 differ during he ime inervals when he inducor currens are supposed o be zero. This difference is caused by he parasiic resonance of he juncion capaciances of he reverse-biased inpu bridge recifiers D -D 6 wih he boos inducors. This curren ringing increases slighly he THD of he inpu curren and, if necessary, can be minimize by selecing recifiers wih smaller juncion capaciances. Figure shows he waveforms of he drain volages of swiches S -. I can be seen ha all he swich volages are well clamped o one half of oupu volage. The oupu-volage regulaion in he prooype circui is implemened by a combinaion of variable-swiching-frequency and phase-shif PWM conrol. The phase-shif PWM conrol is employed a ligh load and can also be employed a high inpu volage o limi he swiching-frequency range. Figure 3 shows he waveforms of he drain volages of swiches S - a full power and 5V L-L, RMS inpu. As i can be seen from Fig. 3, in he phase-shif mode, each pair of swiches S & and S & is swiched in a complemenary fashion wih a fixed duy raio of approximaely 5% wih he swiching insans of he ouer swich S & pair phase shifed wih respec o he corresponding swiching insans of he inner swich S &. Figure 3 shows he measured curren waveforms of boos inducors L, L, and L 3 ha correspond o volage waveform shown in Fig. 3. The measured waveforms shown in Figs. 3 and mach well wih he ideal waveforms shown in Fig. 5. The operaion of he circui wih unbalanced line volages is illusraed in Figs. 4 and 5. Figure 4 shows inpu-curren waveforms of he experimenal circui wih phase A open. Even under his exreme unbalanced condiion, he measured THD of he remaining wo phases is below %. Figure 4 shows he measured volage waveforms of clamping capacior C C and wo serially conneced oupu capaciors C O and C O during he same ransien of phase A open. As i can be seen from Fig. 4, during he enire ransien period, volages,, and V CC are well balanced and equal o one half of he oupu volage. Figures Inpu Volage [V L-L ] TABLE II Measured THD of proposed recifier. Oupu Power [kw] Inpu Volage [V L-L ] TABLE III Measured PF of proposed recifier. Oupu Power [kw] Efficiency V L-L, RMS 48 V L-L, RMS 38 V L-L, RMS =78 VDC Oupu Power [kw] Fig. 6. Measured efficiencies of experimenal prooype as funcions of oupu power. 5 and illusrae operaion of he circui wih one phase shored (volage of phase A se o zero). Under his unbalanced condiion, he measured THD of he line currens is sill well below % and volages,, and V CC are well balanced and equal o one half of he oupu volage as shown in Fig. 5. Tables II and III, show measured THD and PF a nominal inpu volages, respecively. The proposed recifier achieves less han 5% inpu-curren THD a he nominal inpu (38/48 V L-L,RMS ) and above 5% of he full load. The THD a ligher load can be furher improved by employing a low juncion capaciance recifiers in he inpu bridge. Finally, he measured efficiencies of he proposed recifier as a funcion of he oupu power for 34 V L-L, RMS, 38 V L-L, RMS, 48 V L-L, RMS, and 5 V L-L, RMS inpu are ploed in Fig. 6. The measured peak efficiency a 48 V L-L, RMS is 98.%, whereas he peak efficiency a 38 V L-L, RMS is 97.4%. For boh inpu volages, he peak efficiency occurs a half load. VI. SUMMARY In his paper, a new hree-phase four-swich hree-level ZVS PFC DCM boos recifier has been inroduced and is analysis of operaion, design consideraions, and performance evaluaion have been presened. In he proposed recifier, all semiconducor swiches operae wih ZVS and heir off-sae volage is always clamped o one-half of he oupu volage. To reduce he swichingfrequency range and maximize he ligh-load efficiency, he conrol is implemened by a combinaion of variable-swiching-frequency and phase-shif PWM conrol. The proposed sof-swiched recifier exhibis efficiency in he 96-98% range and achieves less han 5% inpu-curren THD over he nominal inpu (38-48 V L-L,RMS ) and above 5% of he full load. The performance evaluaion was done on a hree-phase 6-kW prooype designed for he 34-5-V L-L, RMS line-volage range. The measured full-load inpu-curren THD a 38 V L_L, RMS and V I = 34 V L-L, RMS (c) 5 IEEE. Personal use is permied, bu republicaion/redisribuion requires IEEE permission. See hp:// for more informaion.