V SS R SS(on) max I S. 20V GS1,2 = 4.5V ±6.5 GS1,2 = 2.5V ±5.2

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1 l Ultra Low R SS(on) per Footprint Area l Low Thermal Resistance l BiDirectional NChannel Switch l Super Low Profile (<.8mm) l Available Tested on Tape & Reel l ESD Protection Diode Description True chipscale packaging is available from International Rectifier. Through the use of advanced processing techniques and a unique packaging concept, extremely low onresistance and the highest power densities in the industry have been made available for battery and load management applications. These benefits, combined with the ruggedized device design that International Rectifier is well known for, provide the designer with an extremely efficient and reliable device. The FlipFET package, is onefifth the footprint of a comparable TSSOP8 package and has a profile of less than.8mm. Combined with the low thermal resistance of the die level device, this makes the FlipFET the best device for applications where printed circuit board space is at a premium and in extremely thin application environments such as battery packs, mobile phones and PCMCIA cards. PD 94592B FlipFET Power MOSFET V SS R SS(on) max I S 20V 40m:@V G,2 = ±6.5 60m:@V G,2 = 2.5V ±5.2 Absolute Maximum Ratings Parameter V SS SourcetoSource Voltage 20 V I T A = 25 C Continuous Current, V G = V G = e ±6.5 I T A = 70 C Continuous Current, V G = V G = e ±5.2 A I SM Pulsed Current c 33 P A = 25 C Power Dissipation e 2.5 W P A = 70 C Power Dissipation e.6 Units Linear Derating Factor 20 mw/ C V GS GatetoSource Voltage ±2 V T J Operating Junction and 55 to 50 C T STG Storage Temperature Range Thermal Resistance Parameter Typ. Max. Units R θja JunctiontoAmbient e 50 C/W R θjpcb JunctiontoPCB 35 Max. 06/5/06

2 Electrical T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)SSS SourcetoSource Breakdown Voltage 20 V V GS =0V, I S =250µA,See Fig. 23a&b V (BR)SSS / T J Breakdown Voltage Temp. Coefficient 6 mv/ C Reference to 25 C,I S =ma,fig.23a&b R SS(on) Static SourcetoSource OnResistance mω V G,2 =, I S = 6.5A d Fig.a&b V G,2 = 2.5V, I S = 5.2A d V GS(th) Gate Threshold Voltage V V SS = V GS, I S = 250µA d Fig. 0a&b gfs Forward Transconductance 8 S V SS = 0V, I S = 6.5A, See Fig. 4.0 µa V SS = 20V, V GS = 0V,See Fig.23a&b I SSS Zero Gate Voltage Source Current 25 V SS =, V GS = 0V, T J = 25 C 50 na V SS =, V GS = 0V, TJ = 25 C 00 V SS =, V GS = 0V, T J = 60 C I GSS GatetoSource Forward Leakage µa V GS = 2V, See Fig. 22 GatetoSource Reverse Leakage V GS = 2V GatetoSource Forward Leakage µa V GS = GatetoSource Reverse Leakage V GS = Q g Total Gate Charge 2 8 I S = 6.5A Q gs GatetoSource Charge nc V SS = Q Miller Charge V GS = 5.0V, See Fig. 4a,b&c t d(on) TurnOn Delay Time 8.0 V SS = 0V t r Rise Time 3 ns I S =.0A t d(off) TurnOff Delay Time 33 R G = 3.0Ω t f Fall Time 26 V GS = 5.0V, See Fig. 2a,b&c C iss Input Capacitance 950 V GS = 0V C oss Output Capacitance 20 pf V SS = 5V C rss Reverse Transfer Capacitance 50 ƒ =.0KHz, See Fig. 3a,b,c,d,e&f V ssf SourcetoSource Diode Forward.2 V See Fig. 7a&b Voltage, One Device On I ss = 2.5A Notes: Repetitive rating; pulse width limited by max. junction temperature. Pulse width 400µs; duty cycle 2%. Gate voltage applied to both gates. ƒ When mounted on inch square 2oz copper on FR4. Figures, 2 and 3: One Fet is biased with V GS = 9.0V and curves show response of the second FET. See Fig.4. Figures 5, 6 and 7: and are shorted. See Fig.9a&b. The diode connected between the gate and source serves only as protection against ESD. No gate over voltage rating is implied. 2

3 I S, SourcetoSource Current (Α) I S, SourcetoSource Current (A) I S, SourcetoSource Current (A) 00 0 VGS TOP 7.0V 5.0V 2.5V.8V.5V.2V BOTTOM.0V 00 0 VGS TOP 7.0V 5.0V 2.5V.8V.5V.2V BOTTOM.0V.0V.0V µs PULSE WIDTH Tj = 25 C V SS, SourcetoSource Voltage (V) 20µs PULSE WIDTH Tj = 50 C V SS, SourcetoSource Voltage (V) Fig. Typical Output Characteristics. Fig 2. Typical Output Characteristics T J = 25 C 9V 0.00 T J = 50 C VSS V SS = 5V 20µs PULSE WIDTH V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics. Fig 4. Output and Transfer Test Circuit. 3

4 I GSS, Gate Current ( ma) I GSS, Gate Current (µa) R SS(on), Sourceto Source On Resistance ( mω) R SS (on), SourcetoSource On Resistance ( mω) V GS = 2.5V V GS = 200 I D = 6.5A V GS, Gate to Source Voltage (V) I S, Source Current (A) Fig 5. Typical OnResistance vs. Gate Voltage. Fig 6. Typical OnResistance vs. Source Current T J = 50 C T J = 25 C V GS, GatetoSource Voltage (V) V GS, GatetoSource Voltage (V) Fig 7a. GateCurrent vs. GateSource Voltage Fig 7b. GateCurrent vs. GateSource Voltage 4

5 R SS(on), SourcetoSource On Resistance I S, (Normalized) Source Current (A) 2.0 I D = 6.5A V GS = T J, Junction Temperature ( C) T C, Case Temperature ( C) Fig 8. Normalized OnResistance vs. Temperature. Fig 9. Maximum Source Current vs. Case Temperature. To Drain To Drain To Source To Source Fig 0a. V GS(th) is symmetrical and can be measured when connected as shown on figure 0a. Fig 0b. V GS(th) is symmetrical and can be measured when connected as shown on figure 0b. 5

6 C, Capacitance(pF) 2.5V 2.5V Fig a Fig b R SS(on) is symmetrical and can be measured when connected as shown in either figures a or b V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 000 Ciss Coss Crss V SS, SourcetoSource Voltage (V) Fig 2. Typical Capacitance vs. SourcetoSource Voltage. 6

7 High Capacitance Bridge Low 0MΩ Low Capacitance Bridge High 0MΩ Fig 3a Fig 3b Ciss capacitance is symmetrical and can be measured as shown either in figures 3a or 3b. L Capacitance Bridge H Capacitance Bridge H L Fig 3c Fig 3d Coss capacitance is symmetrical and can be measured as shown either in figures 3c or 3d. Capacitance Bridge L H Common H Capacitance Bridge L Common Fig 3e Fig 3f Crss capacitance is symmetrical and can be measured as shown either in figures 3e or 3f. 7

8 V GS, GatetoSource Voltage (V) 6.0 I D = 6.5A V DS = V DS = 0V Q G 3.0 Q GS Q GD Q 2.0 V G.0 Charge Q G Total Gate Charge (nc) Fig 4. Typical Gate Charge vs. GatetoSource Voltage. Fig 4a. Basic Gate Charge Waveform. Current Regulator 2V 2µ F 50K 4.5 V.5µF Same type as 2V Current Regulator 2µF 4.5 V 50K.5µF Same type as 3mA I G I D 3mA I G Fig 4b I D Fig 4c Gate Charge is symmetrical and can be measured as shown in either figures 4b or 4c. 8

9 I S, SourcetoSource Current (A) I ss, Reverse Source Current (A) 00 OPERATION IN THIS AREA LIMITED BY R SS (on) µsec 0.00 T J = 50 C msec 0msec T A = 25 C Tj = 50 C Single Pulse 0 00 V SS, SourcetoSource Voltage (V) T J = 25 C V GS = 0V V ssf, SourcetoSource Diode Forward Voltage (V) Fig 5. Maximum Safe Operating Area. Fig 6. Typical SourceSource Diode Forward Voltage. (See Fig.7a&b for Connection) To Drain To Drain (V S ) (V S ) To Source To Source Fig 7a Fig 7b V ssf is symmetrical and can be measured when connected as shown either in figures 7a or 7b. 9

10 Thermal Response ( Z thja ) Power (W) V GS(th) Gate threshold Voltage (V) I D = 250µA Time (sec) T J, Temperature ( C ) Fig 8. Typical Power vs. Time. Fig 9. Threshold Voltage vs. Temperature. 00 D = P DM t 0. SINGLE PULSE ( THERMAL RESPONSE ) Notes:. Duty factor D = t / t 2 t 2 2. Peak T J = P DM x Z thja T A 0.0 E006 E t, Rectangular Pulse Duration (sec) Fig 20. Typical Effective Transient Thermal Impedance, JunctiontoAmbient. 0

11 R S = 0ohm 6ohm V GS 0V 6ohm V GS 0V R S = 0ohm Fig 2a Fig 2b Switching times are symmetrical and can be measured as shown in either figures 2a or 2b. V GS t d(on) t r t d(off) t f 0% 90% V DS Fig 2c. Switching Time Waveforms.

12 Fig 22a Fig 22b I GSS Test Connection Fig 23a Fig 23b I SSS and V (BR)SSS are symmetrical and can be measured when connected either as figures 23a or 23b. 2

13 BiDirectional MOSFET Pinout Outline Dimension and Tape and Reel Information Drawing No. 005 & % $ & ; PP ; & $ % & $%$// /2&$7,2 PP & & 3$'$66,*0(76 )(('',5(&7,2 PP 27(6 7$3($'5((/287/,(&2)250672(,$ (,$ $ * $ * % 6 % 6 & 6 & 6 *DWH $ 6RXUFH % *DWH $ 6RXUFH % [ & 6RXUFH & 6RXUFH & ; IPU@T) 9DH@ITDPIDIB UPG@S6I8DIBQ@S6TH@` #$H ((#!8PIUSPGGDIB9DH@ITDPI)HDGGDH@U@S "9DH@ITDPIT6S@TCPXIDIHDGGDH@U@STbDI8C@Td FlipFET Part Marking Information 5(&200('(')22735,7 Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (30) TAC Fax: (30) Visit us at for sales contact information.06/06 3