TVS Diode Arrays (SPA Diodes) SP723 Series 5pF 8kV Diode Array. General Purpose ESD Protection - SP723 Series. RoHS Pb GREEN.

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1 SP7 Series 5pF 8kV Diode rray RoHS Pb GREEN Description The SP7 is an array of SR/Diode bipolar structures for ESD and over-voltage protection of sensitive input circuits. The SP7 has protection SR/Diode device structures per input. There are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. Overvoltage protection is from the (Pins - and Pins 5-7) to V+ or V-. Pinout The SR structures are designed for fast triggering at a threshold of one +V BE diode threshold above V+ (Pin 8) or a -V BE diode threshold below V- (Pin ). From an input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one V BE above V+. similar clamp to V- is activated if a negative pulse, one V BE less than V-, is applied to an input. Functional Block Diagram V+ V- SP7 (PDIP, SOI) TOP VIEW 8 V-, V+ Refer to Fig and Table for further details. Refer to pplication Note N90 and N96 for further detail. Features ESD Interface per HBM Standards - IE , Direct Discharge... 8kV (Level ) - IE , ir Discharge...5kV (Level ) - MIL-STD kV Peak urrent apability - IE /0µs Peak Pulse urrent... ±7 - Single Transient Pulse, 00µs Pulse Width... ± Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to... +0V - Differential Voltage Range to... ±5V Fast Switching...ns Risetime Low Input Leakages...n at 5º Typical Low Input apacitance...5pf Typical n rray of 6 SR/Diode Pairs Operating Temperature Range...-0º to 05º dditional Information pplications Datasheet Resources Samples Microprocessor/Logic Input Protection Data Bus Protection nalog Device Input Protection Voltage lamp Life Support Note: Not Intended for Use in Life Support or Life Saving pplications The products shown herein are not designed for use in life sustaining or life saving applications unless otherwise expressly indicated.

2 bsolute Maximum Ratings Parameter Rating Units ontinuous Supply Voltage, (V+) - (V-) +5 V Forward Peak urrent, I to V, I to GND (Refer to Figure 5) ±, 00µs Peak Pulse urrent, 8/0µs ±7 UTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Note: ESD Ratings and apability (Figure, Table ) Load Dump and Reverse Battery (Note ) Thermal Information Parameter Rating Units Thermal Resistance (Typical, Note ) θ J o /W PDIP Package 60 o /W SOI Package 70 o /W Storage Temperature Range -65 to 50 o Maximum Junction Temperature (Plastic Package) 50 o Lead Temperature (Soldering 0-0s) (SOI Lead Tips Only) 60 o. θ J is measured with the component mounted on an evaluation P board in free air. Electrical haracteristics T = -0 o to 05 o, V = 0.5V, Unless Otherwise Specified Parameter Symbol Test onditions Min Typ Max Units Operating Voltage Range, V SUPPLY - to 0 - V V SUPPLY =[(V+)-(V-)] Forward Voltage Drop to V- V FWDL I =(Peak Pulse) - - V to V+ V FWDH - - V Input Leakage urrent I n Quiescent Supply urrent I QUIESENT n Equivalent SR ON Threshod Note -. - V Equivalent SR ON Resistance V FWD /I FWD ; Note Ω Input apacitance PF Input Switching Speed t ON - - ns. In automotive ans battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, acurrent limiting resistor should be connectied in series between the external supply and the SP7 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.0µF or larger from the V+ and V- Pins to ground are recommended.. Refer to the Figure graph for determine peak current and dessipation under EOS conditions. Typical pplication of the SP7 (pplication as an Input lamp for Over-voltage, Greater than V BE bove V+ or less than -V BE below V-) +V +V PUT DRIVERS OR SIGNL SOURES LER OR DIGITL I TERFE TO +V V+ SP7 V- SP7 PUT PROTETION IRUIT ( OF 6 SHO WN) FIGURE. TYPIL PPLI TION OF THE SP7 S N PUT LMP FOR OVER-VOLTGE, GRETER THN V BE BOVE V+ OR LESS THN -V BE BELOW V-

3 ESD apability ESD capability is dependent on the application and defined test standard.the evaluation results for various test standards and methods based on Figure are shown in Table. The SP7 has a Level HBM capability when tested as a device to the IE standard. Level specifies a required capability greater than 8kV for direct discharge and greater than 5kV for air discharge. For the Modified MIL-STD-05.7 condition that is defined as an in-circuit method of ESD testing, the V+ and V- pins have a return path to ground and the SP7 ESD capability is typically greater than 5kV from 00pF through.5kω. By strict definition of MIL-STD-05.7 using pin-to-pin device testing, the ESD voltage capability is greater than 0kV. For the SP7 EIJ I Machine Model (MM) standard, the ESD capability is typically greater than kv from 00pF with no series resistance. Figure : Electrostatic Discharge Test H.V. SUPPLY V D Standard Type/Mode R D D ±V D IE (Level ) MIL- STD-05.7 HRGE SWITH R DUT HBM, ir Discharge 0 Ω 50pF 5kV HBM, Direct Discharge 0 Ω 50pF 8kV Modified HBM.5k Ω 00pF 5kV Standard HBM.5k Ω 00pF 0kV EIJ I Machine Model 0k Ω 00pF kv EIJ I Machine Model 0kΩ 00pF kv D R D IE 000--: R 50 to 00M MIL-STD-05.7: R to 0M DISHRGE SWITH FIGURE. ELETR OSTTI DISHRGE TEST Table : ESD Test onditions Figure : Low urrent SR Forward Voltage Drop urve Figure : High urrent SR Forward Voltage Drop urve T = 5 T = 5 SGLE PULSE SGLE PULSE 5 5 T = 5º T = 5º SGLE PULSE SGLE PULSE FORWRD ST URRENT (m) FORWRD ST URRENT (m) FORWRD SR URRENT () FORWRD SR URRENT () EQUIV. ST. EQUIV. ON. ST. ON. THRESHOLD THRESHOLD ~.V ~.V V FWD IFWD V FWD IFWD FORWRD FORWRD SR VOLTGE SR VOLTGE DROP (mv) DROP (mv) FORWRD FORWRD SR VOLTGE SR VOLTGE DROP (V) DROP (V)

4 Peak Transient urrent apability of the SP7 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP7 s ability to withstand a wide range of peak current pulses vs time. The circuit used to generate current pulses is shown in Figure. The test circuit of Figure is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP7 input pin and the (+) current pulse input goes to the SP7 V- pin. The V+ to V- supply of the SP7 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 5 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of 5º and 05º and a 5V power supply condition. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of Figure 5. Note that adjacent input pins of the SP7 may be paralleled to improve current (and ESD) capability. The sustained peak current capability is increased to nearly twice that of a single pin. PEK URRENT () Figure : Typical SP7 Peak urrent Test ircuit with a Variable Pulse Width Input V X - R VOLTGE PROBE R ~ 0 TYPIL V X DJ. 0V/ TYPIL ~ 00 µf (+) VRIBLE TIME DURTION URRENT PULSE GENERTOR URRENT SENSE (-) V SP7 6 - V- 5 Figure 5: SP7 Typical Single Peak urrent Pulse apability Showing the Measured Point of Overstress in mperes vs pulse width time in milliseconds T = 05 T = 5 UTION: SFE OPERTG ONDITIONS LIMIT THE MXIMUM PEK URRENT FOR GIVEN PULSE WIDTH TO BE NO GRETER THN 75% OF THE VLUES SHOWN ON EH URVE. V+ TO V-SUPPLY = 5V PULSE WIDTH TIME (ms)

5 Temperature TVS Diode rrays (SP Diodes) Soldering Parameters Reflow ondition - Temperature Min (T s(min) ) 50 Pb Free assembly T P Ramp-up t P ritical Zone TL to TP Pre Heat - Temperature Max (T s(max) ) 00 - Time (min to max) (t s ) secs verage ramp up rate (Liquidus) Temp (T L ) to peak T S(max) to T L - Ramp-up Rate 5 /second max 5 /second max T L T S(max) T S(min) t S Preheat t L Ramp-down Reflow - Temperature (T L ) (Liquidus) 7 - Temperature (t L ) seconds 5 time to peak temperature Time Peak Temperature (T P ) 60 +0/-5 Time within 5 of actual peak Temperature (t p ) 0 0 seconds Ramp-down Rate 5 /second max Time 5 to peak Temperature (T P ) 8 minutes Max. Do not exceed 60 Package Dimensions Dual-In-Line Plastic Packages (PDIP) DEX RE BSE PLNE SETG PLNE D B N N/ B D E -B- D e e 0.00 (0.5) M B S NOTES:. ontrolling Dimensions: H. In case of conflict between. ontrolling English Dimensions: and Metric H. dimensions, In case of the conflict inch dimensions between English control. and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per NSI Y.5M-98.. Dimensioning and tolerancing per NSI Y.5M-98.. Symbols are defined in the MO Series Symbol List in Section. Symbols. are of defined Publication in the No. MO 95. Series Symbol List in Section. of Publication No Dimensions. Dimensions, and, L are and measured L are measured with the with package the package seated in seated JEDE seating plane gauge GS-. in JEDE seating plane gauge GS-. 5. D, D, 5. D, and D, E and dimensions E dimensions do not include do not mold include flash mold or protrusions. flash or protrusions. Mold flash or protrusions shall Mold not flash exceed or 0.00 protrusions inch (0.5mm). shall not exceed 0.00 inch 6. E and e(0.5mm). are measured with the leads unconstrained to be perpendicular to datum E and e are measured with the leads constrained to be perpendicular e 7. e B and are measured to datum the -- lead. tips with the leads uncon-strained. e must be zero or greater. 7. e B and e are measured at the lead tips with the leads unconstrained. dimensions e must be do zero not include or greater. dambar protrusions. Dambar protrusions shall not 8. B maximum exceed 0.00 inch (0.5mm). 8. B maximum dimensions do not include dambar protrusions. 9. N is the Dambar maximum protrusions number of shall terminal not exceed positions inch (0.5mm). 0. orner 9. N leads is the (, maximum N, N/ and number N/ + ) of for terminal E8., E6., positions. E8., E8., E.6 will have a B dimension 0. orner of 0.00 leads - (, 0.05 N, N/ inch and (0.76 N/ -.mm). + ) for E8., E6., E8., E8., E.6 will have a B dimension of inch ( mm). L E L e e B Package PDIP Pins 8 JEDE MS-00 Millimeters Inches Min Max Min Max Notes B B , D D E E e.5 BS 0.00 BS - e 7.6 BS 0.00 BS 6 e B L N 8 8 9

6 Package Dimensions Small Outline Plastic Packages (SOI) N DEX RE e D B 0.5(0.00) M M E SETG PLNE B S H 0.5(0.00) M B 0.0(0.00) -B Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per NSI Y.5M-98.. NOTES: Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side.. Symbols are defined in the MO Series Symbol List in Section. of. Dimension E does not include interlead flash or protrusions. Inter-lead flash Publication Number 95. and protrusions shall not exceed 0.5mm (0.00 inch) per side. 5.. The Dimensioning chamfer on the and body tolerancing is optional. If per it is NSI not present, Y.5M-98. a visual index feature. must Dimension be located D within does the not crosshatched include mold area. flash, protrusions or gate burrs. 6. L Mold is the flash, length protrusion of terminal for and soldering gate burrs to a shall substrate. not exceed 0.5mm ( N inch) is the per number side. of terminal positions. 8.. Terminal Dimension numbers E are does shown not for include reference interlead only. flash or protrusions. Interlead 9. The eadl width flash B, and as protrusions measured 0.6mm shall not (0.0 exceed inch) 0.5mm or greater (0.00 above the inch) per seating side. plane, shall not exceed a maximum value of 0.6mm (0.0 inch) ontrolling The chamfer dimension:millimeter. the body is optional. onverted If it inch is not dimensions present, are a visual not index necessarily feature exact. must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. Part 7. N Numbering is the number of System terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, SP as 7 measured ** 0.6mm * * (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm TVS Diode (0.0 rrays inch). (SP 0. ontrolling Diodes) G=Green dimension:millimeter. onverted inch dimensions are not necessarily exact. P=Lead Free Series T= Tape and Reel Package μ L M h x 5 o B = 8 Ld SOI P = 8 Ld PDIP Package SOI Pins 8 JEDE MS-0 Millimeters Inches Min Max Min Max Notes B D E e.7 BS BS - H h L N µ 0º 8º 0º 8º - Product haracteristics Lead Plating Matte Tin Lead Material opper lloy Lead oplanarity 0.00 inches (0.0mm) Substitute Material Silicon Body Material Molded Epoxy Flammability UL 9 V-0 Ordering Information Part Number Temp. Range (º) Package Environmental Informaton Marking Min. Order SP7PP -0 to 05 8 Ld PDIP Lead-free SP7P(P) 000 SP7BG -0 to 05 8 Ld SOI Green SP7(B)G 960 SP7BTG -0 to 05 8 Ld SOI Tape and Reel Green SP7(B)G 500. SP7P(P) means device marking either SP7P or SP7PP.. SP7(B)G means device marking either SP7G or SP7BG which are good for types SP7BG and SP7BTG. Disclaimer Notice - Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and test each product selected for their own applications. Littelfuse products are not designed for, and may not be used in, all applications. Read complete Disclaimer Notice at