Importance of Layer-to-Layer Alignment
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1 Importance of Layer-to-Layer ignment Exampe: meta ine to contact hoe margina contact no contact! Exampe of Design Rue: If the minimum feature size is 2, then the safety margin for overay error is. safety margin to aow for misaignment Design Rues are needed: Interface between designer & process engineer Guideines for designing masks
2 IC RESISTOR MSK LYOUTS REGISTRTION OF ECH MSK Registration of mask patterns is critica show separate ayouts to avoid ambiguity Oxide mask (dark fied) Contact mask (dark fied) mask (cear fied) B B registration shows overay of patterns scae in m for B-B cut Registration of one mask to the next (aso caed aignment and overay ) is a crucia aspect of ithography
3 Same Layout but with misregistration (misaignment) B perfect registration scae in m for B-B cut B B Contact mask misaigned by 2 m scae in m for B-B cut B Lets ook again at cross-section - to understand the consequence of this misaignment. Note contact mask 2 m
4 Layout with no misregistration (misaignment) B B perfect registration STEP 7 p-type ayer
5 Layout with misregistration (misaignment) B B Contact mask misaigned by 2 m This resistor has an open circuit!! scae in m for B-B cut STEP 7 p-type ayer Thus we need safety margins in ayout which take into account the possibe toerances in fabrication. Each process has a set of design rues which specify the safety margins.
6 Layout Design Rues (1) bsoute-vaue Design Rues * Use absoute distances (2) -based Design Rues 6 6
7 EE143 Layout Design Rues 1. Basic ength unit = = 2 m 1.1 Lithography and etching imit =2 1.2 Overay accuracy = 7
8 2.1 Meta-Si Contact Hoe 2 2 (same rue for Meta-poy) Min. contact hoe = 2 x 2 Min contact hoe to diffusion ayer distance = SiO 2 n + SiO 2 n + p-sub p-sub 8
9 2.2. Meta Lines Min width = 2 Min. meta-meta spacing = 3 Line Line 2 [Rationae] meta runs on rough topography 3 spacing to ensure no shorting between the 2 ines. 9
10 Min overap of contact hoe = SiO 2 Etching probem CVD SiO 2 deposition. probem in narrow gap Si 10
11 Meta ine-width is arger when running over a contact hoe Configuration 1 Configuration
12 Min width = Poy-Si Lines Min poy-poy spacing = 2 poy meta Line 1 [Rationae: Unike meta ines, poy-si runs on smoother topography] Line Min underap of meta/poy contact =
13 Exampe: Meta Contact to Poy meta poy Note: Both meta and poy inewidths wi enarge to accommodate contact hoe overay error 13
14 2.4. MOS Thin-Oxide Region Thick Oxide Region (FOX) Min Width = 2 2 Thin Oxide Region (active device area) 2 Min spacing =
15 Min underap of thin-oxide contact = 15
16 3. Poy-Si Gate Min gate-overap of fied oxide = 2 2 [Comment] void n+ channe formation during S/D Impant n + n + n + idea With overay error 16
17 Min thin-oxide contact to gate spacing =
18 Comment: to poy contact shoud not be directy on top of gate oxide area Gate oxide Poy gate Si Poy ~400 O C spike Poy SiO 2 Si SiO 2 Si 18
19 contact on thick oxide area ok 2 SiO 2 (CVD) FOX 19
20 Min Gate Width = 2 Min Gate Length = 2 Usuay: W/L are specified by circuit requirement. Min. poy to thin oxide spacing = 20
21 Exampe Design a minimum-size poy-gate MOS transistor with W/L = 4 m/4 m (2 x 2 ) Haf-way distance to next MOSFET ( = 1. 5 ) Minimum size contact = 2x2 Minimum thin-oxide-region underap of contact = Minimum source/drain contact to gate spacing = 2 Minimum L = 2 Minimum W = 2 Minimum gate overap of fied-oxide region = 2 Minimum meta overap of contact = Minimum thin-oxide-region to thin-oxide-region spacing = 3 * Layout area /transistor = 15x7 = meta poy ctive region Contact hoe 21
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