Homework Assignment # 9 (Due April 6, 8am)
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1 EE143 Homework Assignment # 9 (Due Apri 6, 8am) S2006 Week of 3/27 is Spring Recess Midterm Exam #2 wi be on Apri 5 (Wed) 6:00-7:30pm, GPB Room 100, cosed book exam, 8 sheets of handwritten notes aowed. Topics of HW#1-HW#8 wi be incuded. Reading Assignment 1)Jaeger, pp )Summary sheet of EE143 ayout rues (attached) 3) EE143 Reader ( Design Rue Basics from Physica Design of CMOS IC Using L-Edit, J.P. Uyemura). This genera reading provides bakground info on why different rues are needed. Read here before you start your homework : The ayout schematics shown beow are not to scae. The exact ayout may depend on the constraints imposed by the design rues. You have to do a ayouts with a scae of 0.2 to 1. A graph paper with such a scae is attached is aso posted on the web. You can photocopy/print it for your homework probems. The reader wi not grade any homework turned in with other arbitrary scaes. You have to draw the ayout and specify which design rues are used. If you wish, you can aso use coor pencis to distinguish the different boundaries. Suggestions: Start wih a smaest feature first (e.g. contact hoe, poy-gate ength) and then sketch outward. Note: 1) Active device region is aso caed Thin oxide region; 2) The S/D area is aso caed the diffusion region athough it is doped by ion impantation. Probem 1 MOS Transistor a warmup exercise Your textbook shows the schematic ayout of a MOSFET (not drawn to scae) with two contact hoes for the source/drain. Use our EE143 ayout design rues to do a minimum geometry ayout which can accommodate two contact hoes for the source and the drain. Given: The transistor channe ength L = 4 and channe width W =8 Probem 2 NMOS Inverter Layout a minimum geometry NMOS (poy-gate) inverter with the EE143 design rues in the graph paper provided. The circuit diagram and the schematic cross-section are shown beow. V in, V out and are the 1
2 input votage ine, output votage ine, and suppy votage ine respectivey. A interconnects are auminum ines. Both transistors have W=4 µm (2λ) and L=4 µm (2λ). The poy-gate of transistor is eectricay connected to its drain with an auminum ine.dash ines indicate contact cut to the poy-si is to the V V V in out DD V n+ n+ n+ out SiO2 Vin p substrate Probem 3 NOR Gate Use our EECS143 design rues to draw a minimum-geometry two-input NMOS NOR gate using poy-si gate transistors. is connected to the gate of T3 with A ine. To conserve space and to minimize the number of contact hoes, the n+ diffusion regions are merged wherever possibe. GIVEN : and : W/L = 10 µm / 4µm ; T3: W/L = 4 µm / 10µm. To hep you started, an unfinished (not-to-scae) sketch of the top-view is provided. Any reasonabe deviation from this sketch is acceptabe. Draw the composite ayout (incuding meta ines) and state the design rue used. T3 (A+B) T3 poy (A+B) A B A n+ diffusion B 2
3 Probem 4 How design rues can be changed The foowing cross-section shows a CMOS inverter fabricated with siicon-on-insuator (SOI) technoogy. Note that the buried oxide (SiO2) is a perfect eectrica insuator. If we choose to use this technoogy. Expain how three of our EE143 MOS ayout design rues can be changed (i.e., arger or smaer). Justify your expanations. Gate oxide (therma SiO2) Buried Oxide (SiO2) Si substrate 3
4 1. Background EE143 Standard Layout symbos and Design Rues for MOS 1.1 Lithography/etching imit on minimum feature or spacing = 2λ 1.2 Aignment imit (overay accuracy) = λ 1.3 Uness specified, defaut vaue: λ = 2 µm 2. Symbos and Rues 2.1 Contacts (meta to siicon) minimum size 2λ x 2λ Meta minimum spacing: 3λ minimum underap of contact: λ 2 meta ine 3 spacing 2 meta ine 2.3 Poysiicon minimum spacing: 2λ minimum underap of contact: λ 2 poy ine spacing 2 poy ine meta ine 3. MOS Devices 3.1 Thin oxide of MOS minimum space: 3λ minimum underap of contact: λ [ The thin oxide region is aso known as diffusion region. The fied oxide region is aso caed the thick oxide region] 2 Fied Oxide 3 spacing 3.2 Si Gate of MOS Minimum gate overap of fied =2λ Minimum contact to gate spacing =2λ Contacts to poysiicon aowed on thick oxide ony. Minimum spacing to thin oxide = 2λ Minimum poy to thin oxide spacing = λ Fied Oxide Fied Oxide
5 λ λ
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