IMPROVED IP3 BEHAVIOUR OF THE 900MHz LOW NOISE AMPLIFIER WITH THE BFG425W

Transcription

1 Phiips Semiconductors B.V. Gerstweg 2, 6534 AE Nijmegen, The Netherands Report nr. : RNR-T45-96-B-1025 Author : T.F. Buss Date : 10 Dec Department : P.G. Transistors & Diodes, Deveopment IMPROVED IP3 BEHAVIOUR OF THE 900MHz LOW NOISE AMPLIFIER WITH THE BFG425W UPDATE OF REPORT RNR-T45-96-B-771 Abstract: This appication note contains an exampe of a Low Noise Ampifier with the new BFG425W Doube Poy RF-transistor. The LNA is designed for a frequency f=900mhz, V SUP ~3.8V, I SUP =10mA. Measured performance at f=900mhz: Noise Figure NF~1.7dB, gain S 21 ~17dB and the input IP3=+3dBm. Appendix I: 900MHz LNA circuit Appendix II: Printayout and ist of used components & materias Appendix III: Resuts of simuations and measurements 1

2 Phiips Semiconductors B.V. Introduction: With the new Phiips siicon bipoar doube poy BFG400W series, it is possibe to design ow noise ampifiers for high frequency appications with a ow current and a ow suppy votage. These ampifiers are we suited for the new generation ow votage high frequency wireess appications. In this note an exampe of such an ampifier wi be given. This ampifier is designed for a working frequency of 900MHz. Designing the circuit: The circuit is designed to show the foowing performance: transistor: BFG425W V ce =2V, I c =10mA, V SUP ~3.5V freq=900mhz Gain~18dB NF<=1.6dB IP3>0dBm (input) VSWRi<1:2 VSWRo<1:2 In the simuations the effect of extra RF-noise caused by the SMA-connectors was omitted, so in the practica situation the NF is ~0.1dB higher. This LNA is aso optimised for the highest IP3. The IP3 can be optimised by: I. an extra series C-decouping of the base to the ground II. increasing I C With the soution I. an extra component is necessary, and with soution II, the Noise Figure of the LNA increases and the optimum source impedance aso. The in- and outputmatching is reaised with a LC-combination. Aso extra emitter-inductance on both emittereads (µ-strips) are used to improve the matching and the Noise Figure. Designing the ayout: A ay-out has been designed with HP-MDS. Appendix II contains the printayout. Measurements: Simuations (with reaistic RF-modes of a used parts) and measurements of the tota circuit (epoxy PCB) are done (Appendix III). 2

3 Phiips Semiconductors B.V. Appendix I: Schematic of the circuit C6 C3 C4 R1 +V SUP C2 R3 R4 Coi_1 Coi_2 IN 50Ω C1 BFG425W R2 C7 µs4: C5 W1 OUT 50Ω L1 µs4 µs4 L2 D1 L3 W2 Figure 1: LNA circuit 900MHz LNA Component ist: 900MHz LNA Component ist: Component Vaue Purpose, comment R1 8.2 kω Bias (co.-base) R2 10 Ω in series with co. for better S22, stabiity and reducing gain. R3 22 Ω RF bocking R4 150 Ω Bias, series with co., canceing hfe spread C1 8.2 pf Input match (input to base) C2 27 pf 900 MHz short (L1 to ground) C3 27 pf 900 MHz short (L2 to ground) C4 100 nf RF decouping coector bias C5 22 pf Output match (coector to output) C6 100 nf To improve IP3 (by decouping LF IP3 products) C7 3.3 pf Output match, stabiity (coector to emitter) Coi_2 nh Input match (base-bias) Coi_2 12 nh Output match (coector-bias) µs4 (see next µ-stripine Emitter-induction tabe) 3

4 Phiips Semiconductors B.V. µs4 Emitter inductance of µ-stripine and via-hoe (see on former page: Schematic of the circuit): Name Dimension Description L.5mm ength µ-stripine; Z 0 ~48Ω (PCB: ε r ~4.6, H=0.5mm) L2 1.0mm ength interconnect stripine and via-hoe area L3 1.0mm ength via-hoe area W1 0.5mm width µ-stripine W2 1.0mm width via-hoe area D1 0.4mm diameter of via-hoe 4

5 Phiips Semiconductors B.V. Appendix II: Printayout and ist of used components & materias RFin C1 C6 L1 C7 C5 R2 RFout C2 C4 R1 L2 Vsup R4 R3 C3 900MHz LOW NOISE AMP. Figure 2: Printayout 900MHz LNA Component ist: Component: Vaue: size: PCB FR4: ε r ~4.6 H=0.5mm R1 8.2 kω 0603 Phiips R2 10 Ω 0603 Phiips R3 22 Ω 0603 Phiips R4 150 Ω 0603 Phiips C1 8.2 pf 0603 Phiips C2 27 pf 0603 Phiips C3 27 pf 0603 Phiips C4 100 nf 0805 Phiips C5 22 pf 0603 Phiips C6 100 nf 0805 Phiips C7 3.3 pf 0603 Phiips L2 nh 0805CS Coicraft L2 12 nh 0805CS Coicraft 5

6 Phiips Semiconductors B.V. Appendix III: Resuts of simuations and measurements Conditions: V SUP =3.7V, I C =10mA, f=900mhz Simuation (HP-MDS): Measurements PCB: Comment: S21 2 [db] S12 2 [db] VSWRi VSWRo Noise Figure [db] note 1 IP3 [dbm] (input) f=200khz, note 2 note 1: The Noise Figure of the PCB is higher than the simuations (~0.1 db). This is caused by the infuence of the SMA-connectors and the microstrips on the epoxy PCB. note 2: The IP3 of the PCB is higher than the simuations. This can be expained by the deviation of the Spice parameters, used in the IP3 simuations, from the sampe transistor-parameters used in the LNA. CMP286 CMP287 CMP289 OD=0.4 mm L=1 nh L=Lvi a Ccmc=Contkop CMP417 L CMP418 C CMP419 R C=100 nf mode cap.100nf CMP428 R=0.3 OH LOW NOISE AMP. WITH BFG425W@2V/10mA L=0.5 mm CMP230 OD=0.4 mm L=Lvi a CMP231 mode cap.100nf L=1 nh CMP265 L CMP430 C=1 nf CMP263 C CMP264 R R1=22 OH CMP406 R=0.3 OH CMP429 R1=39 OH CMP235 L L=100 uh AGROUN W=W50_Ohm L=6 mm smd CMP399 coicraft_1008 _cs Lx=Li n CMP281 W=W3 L=L3 W=W3CMP408 L=L3 R1=11 k CMP236 SB1/BFG425W@2V/10mA CMP257 TWOPORT DATA=DEBBY_425_2V_10m_1c.spar.SP.,freq=freq CMP383 R1=Rout CMP405 L=0.5 mm CMP358 Lx=Lout smd CMP394 coicraft_1008 _cs CMP197 L=3 mm CMP409 L=0.5 mm W=W50_Ohm L=6 mm CMP203 Ccmc=Contkop L=Lvi a CMP227 CMP266 OD=0.4 mm CMP18 PORT_SPAR CMP401 PORTNUM=1 R=50 JX=0 Ccmc=Cin CMP CMP431 L=L4 CMP438 W=W4 L=0.5 mm Ccmc=Cout CMP5 MSSUBSTRATE CMP403 CMP270 PORT_SPAR PORTNUM=2 R=50 JX=0 AGROUND Ccmc=Ccex HU=1.0E+3 m ER=4.6 T=35um MUR=1 COND=5.8e07 H=0.5mm ROUGH=10 um AGROUND TAND=0.02 CMP350 W=0.5 L=L1 mm CMP351 W=0.5 L=L1 mm W2=0.5 mm W2=0.5 mm CMP250 MSTAPER CMP252 MSTAPER W1=Wvia_e L=L2 W1=Wvia_e L=L2 CMP180 _e OD=0.4 mm CMP210 _e OD=0.4 mm Figure 3: HP-MDS simuation circuit 6