UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EE143 Final Exam

Transcription

1 UNIVERSITY OF CALIFORNIA Coege of Engineering Department of Eectrica Engineering and Computer Sciences Spring 2006 EE143 Fina Exam Famiy Name First name SID Signature Sampe Soutions Instructions: DO ALL WORK ON EXAM PAGES Make sure your copy of the exam paper has 11 pages (incuding cover page) This is a 3-hr exam (12 sheets of handwritten notes aowed) Grading: Whenever possibe, use sketches to support your expanation. Show correct units and agebraic sign for numerica answers. No partia credit for numerica answers orders of magnitude off. Probem 1 (40 points) Probem 2 (20 points) Probem 3 (40 points) Probem 4 (40 points) Probem 5 (35 points) Probem 6 (25 points) Information which may be usefu ε s = F/cm for Si ε ox = F/cm for SiO 2 q = couombs Botzmann constant k = ev/k n i of Si= cm -3 at 300K E g of Si = 1.12 ev at 300K Eectron Affinity of Si =4.15 ev Eectric potentia φ =(E f -E i )/q n= n i exp(qφ/kt) x d = [ 2ε s q ( φ i -V a ) ( 1 N a + 1 N d )]1/2 MOS: V GB = φ MS +V ox +V Si TOTAL (200 points) V FB = φ MS - x ox 1 [ Q C f + x ρ (x) ox dx ] ox x ox 0 MOSFET I-V (n-channe): I DS = µ W n L C ox [ (V G - V T ) V DS - V DS 2 /2 ] (beow saturation) I Dsat = µ W n L C ox [(V G -V T )2 /2] (above saturation) 1

2 Probem 1 Lab Questions (40 points tota) (a) (10 points) In Cory 218, we ony have the foowing processing equipment: Mask aigner Spinning, baking, and deveopment setups for photoresist and spin-on gass Wet chemica bench for ceaning and wet etching Oxidation furnace Anneaing furnace A evaporator. Describe a process sequence using ONLY the avaiabe equipment in Cory 218 to fabricate the foowing DRAM structure, which is simpy an A-gate n-channe MOSFET connected to a capacitor A A Gate A eectrode for capacitor n+ Si boundary A Fied Oxide Gate oxide p-type Si Gate oxide boundary MOSFET Capacitor Process Description Cross-section 1) Spin on phosphorus doped SOG.: n+ region patterning (Mask 1). Drive-in. 2) Strip SOG. Therma oxidation to form fied oxide. 3) Gate oxide patterning after fied oxide growth (Mask 2). Grow thin gate oxide. 4) Contact opening (Mask 3) 5) Aunminum deposition.: Meta patterning (Mask 4) 2

3 Probem 1 Lab Questions continued (b) (8 points) Suppose the ab has an ion impanter, which step(s) in the process sequence wi you change to improve the MOS device performance of the Ee143 chip? What improvement wi you expect? Repace a SOG doping of poy-si and source/drain by ion impantation. More precise contro of dose and junction depths. The shortest channe device wi work because of ess atera diffusion. Can aso perform threshod impant to contro V T if desired. (c)( 4 points) The ring osciator test structure on the EE143 chip usuay has ow yied. What are the major probems? ALL components of the osciator (transistors, contacts, and interconnects) have to work. If anyone of the components fais, the osciator wi not function. Most common probems: misaignment, overetch, contact ceaning. (d) (4 points) Why do we annea the chip with forming gas after metaization? 1) Reduce interface charge of the Si/SiO2 interface by hydrogen passivation 2) Enhance A diffusion through oxide residua eft by surface ceaning. Better A/Si ohmic contact. (e) (4 points) Why do we use XeF2 to reease the MEMS structure instead of using KOH? Avoid stiction probem of wet etching when oxide beam is reeased. 3

4 Probem 1 continued (f ) The I D versus V G pot of the EE143 MOSFET [Device 8D with W/L = 15µm/ 10µm] is shown beow. The V DS bias is kept constant at 50mV. (i) (5 points) Extract the threshod votage from the data. Show a your cacuations. For sma V DS (i.e. 50mV), I DS = µ n W L C ox (V G - V T ) V DS Data has a background current of A, the inear dependence on V G takes off at V G ~0.75 vots wich is V T. (ii) (5 points) From C-V measurement, we know the gate oxide thickness 73nm. Extract the channe eectron mobiity µ n from the I-V data. Show a your cacuations. C ox = F/cm 2 For sma V DS (i.e. 50mV), I DS = µ n W L C ox (V G - V T ) V DS Sope of I DS versus V G curve = µ n W L C ox V DS µ n ~ (15/10) = 1500 cm 2 /V-sec ~ A/V from curve 4

5 Probem 2 Layout (20 points tota) In the homework assignment, you have done the ayout of a two-input NMOS NOR gate using poy-si gate transistors. V DD is connected to the gate of T3 with A ine. The circuit diagram and conceptua ayout are shown beow. V DD V DD T3 (A+B) T3 poy (A+B) A T1 T2 B A n+ diffusion B T1 T2 (a) (5 points) What is the major advantage of the conceptua ayout (shown above) in terms of ayout area? Circuit connections of the source/drains of T1,T2 and T3 are done with n+ Si (i.e. extension of the S/D regions). Since no contact hoes or A ines are used for these connections, ayout area is substantiay reduced. (b) (15 points) Layout the NOR gate in the graph paper provided beow if ALL transistors have the same minimum dimension of W/L = 4 µm/4 µm (i.e., 2 λ x 2 λ). V DD (A+B) Active region Poy A A B Contact hoe Ground 5

6 Reference: EE143 Standard Layout symbos and Design Rues 1. Background 1.1 Lithography/etching imit on minimum feature or spacing = 2λ 1.2 Aignment imit (overay accuracy) = λ 1.3 Uness specified, defaut vaue: λ = 2 µm 2. Symbos and Rues 2.1 Contacts (meta to siicon) minimum size 2λ x 2λ Meta minimum width: 2λ minimum spacing: 3λ minimum underap of contact: λ 2 meta ine 3 spacing 2 meta ine 2.3 Poysiicon minimum width: 2λ minimum spacing: 2λ minimum underap of contact: λ 2 poy ine spacing 2 poy ine meta ine 3. MOS Devices 3.1 Thin oxide of MOS minimum width: 2λ minimum space: 3λ minimum underap of contact: λ [ The thin oxide region is aso known as diffusion region. The fied oxide region is aso caed the thick oxide region] 2 Thin Oxide Fied Oxide Thin Oxide 3 spacing 3.2 Si Gate of MOS Minimum gate overap of fied =2λ Minimum contact to gate spacing =2λ Contacts to poysiicon aowed on thick oxide ony. Minimum spacing to thin oxide = 2λ Minimum poy to thin oxide spacing = λ Fied Oxide Thin Oxide Fied Oxide

7 Probem 3 MOS Anaysis (40 points tota) (a) (25 points) The foowing structure is a p-susbtrate MOS capacitor with a n+ side contact so that the inversion charge can be biased independenty by a votage suppy V C. V G Meta Gate inversion eectrons SiO2 x dmax n+ V C depetion region p-si Indicate in the tabe beow how the MOS parameters wi change when the (i) gate work function φ M, (ii) substrate doping concentration N a, (iii) gate oxide thickness x ox, (iv) channe bias V C, (v) Positive oxide interface charge increases. Use an,, or 0 to denote an increase, decrease, or no change respectivey. Votage drop across Si substrate V Si x dmax Votage drop across oxide V ox V T High-frequency sma-signa capacitance C min φ M N a f x ox 0 0 f V C f Q f (+) 0 0 f f 0 (b) MOSFET A and MOSFET B are both n-channe transistors. They are identica except MOSFET B has an Si/SiO2 interface charge Q f. (i) (7 points) MOSFET A has I Dsat = 1 ma for V G =5 vots, V S = 0 vot, and V B (body bias) =0 vots. V T is known to be +0.7V. MOSFET B has I Dsat = 1.5 ma for V G =5 vots, V S = 0 vot, and V B (body bias) =0 vots. What is the V T of MOSFET B? I Dsat = µ n W L C ox [(V G -V T )2 /2] 1/1.5= (5-0.7) 2 / (5-V T (B)) 2 V T (B) = -0.27vots V B =0 (ii) (4 points) What is the corresponding V Dsat for MOSFET B with V G =5 vots, V S = 0 vot, and V B (body bias) =0 vots. V Dsat = V G V T = 5.27 vots (iii) (4 points) Gate oxide thickness is 100nm, cacuate the oxide interface charge Q f for MOSFET B? V T = vots = - Q f /C ox Q f = 0.97 ( / 10-5 ) = F/cm 2 or q /cm 2 7

8 Probem 4 MEMS (40 points tota) (A) The foowing description and figure are taken from Chapter 11 of your Jaeger textbook. Figure depicts a process deveoped at the University of Caifornia at Berkeey in which the mechanica structures are formed foowing competion of the CMOS circuitry. A standard p-we CMOS process forms the CMOS circuitry, except for the use of tungsten metaization, which is a refractory meta that can withstand high-temperature processing. A nitride passivation ayer protects the CMOS devices during MEMS machining. The MEMS devices are fabricated over the nitride, and oxide-insuated region. Interconnection between the eectromechanica devices and the active CMOS circuitry is accompished with the poysiicon gate ayer of the integrated circuit and the first poysiicon ayer of the MEMS region. (a) (5 points) Tungsten metaization is used because it can withstand high-temperature processing. What particuar high-temperature processing step(s) are the description referring to? Poy-Si (P1,P2, and P3) deposition are high temperature steps ( o C), A metaization wi met if used for CMOS interconnects. Tungsten can withstand this high temperature. (b) (5 points) Why is siicon nitride used as the passivation ayer for the CMOS instead of siicon oxide? During sacrificia ayer (usuay oxide) etch for MEMS reease, siicon nitride passivation ayer wi protect the CMOS area from etching. (c) (5 points) What is the purpose of the Etch Hoe shown in the MEMS structure? Etch hoes aow etchant having easy access to sacrificia ayer underneath, shortening atera undercut etching time (d) (5 points) What is the function of the Limit Stop shown in the MEMS structure? Eectrostatic defection more than ~1/3 of gap height wi coapse the beam towards the bottom. The Limit Stop can prevent excessive defection. The Limit stop aso minimize the contact area during MEMS reease (stiction probem) 8

9 Probem 4 MEMS Continuation of Part(A) (e) (10 points) After competion of the CMOS structure processing, how many ithography steps are needed to compete fabrication of the MEMS structure? List a MEMS fabrication ithography steps AND describe their functions. Mask 1 contact hoe opening to CMOS P1 deposition Mask 2- P1 patterning Etch P1 PSG1 deposition Mask 3 contact hoe (P2 to P1) patterning Etch contact hoe Mask 4 Limit stop patterning on PSG1 Etch Limit Stop feature P2 deposition Mask 5- P2 patterning Etch P2 PSG2 deposition Mask 6 contact hoe (P3 to P2) patterning Etch contact hoe Mask 7 Limit stop patterning on PSG2 Etch Limit Stop feature P3 deposition Mask 8- P3 and etch hoe patterning (same mask) Etch P3 (B) A 500 µm -thick bare Si wafer is originay fat. After a 300nm-thick oxide deposition, the wafer radius of curvature is measured to be +200 m. A 600nm nitride fim is then deposited on top of the oxide and the wafer radius of curvature becomes infinity ( i.e., fat, no curvature). Cacuate the stress of the nitride fim aone. Is the nitride stress compressive or tensie? (Given: ν Si = 0.272, E Si = 1.9 x Newton/m 2 ) RADIUS OF CURVATURE RELATIONSHIP : σ f = E s t s 2 ( 1- ν) s 6 r t f ) With the oxide deposited, the oxide stress is compressive since r = +200m t f = m t s = m σ f (oxide) = ( ) ( ) = N/m 2 With both the nitride and the oxide deposited, r =, therefore σ f (oxide + nitride) = 0 σ f (nitride) = N/m 2 (tensie) 9

10 Probem 5 CMOS on Siicon-on-insuator (35 points tota) Design a process fow to produce the foowing poy-si gate CMOS on SOI (siicon on insuator) structure. The starting materia is 1µm-thick n-type singe-crystaine siicon on SOI with N d = / cm 3. CVD oxide CVD oxide CVD oxide Gate oxide (therma SiO2) Buried Oxide (SiO2) Si substrate (a) (10 points) List major processing advantages for CMOS on SOI as compared with CMOS on buk Si. Processing advantages: No Fied Oxide (an channe stop impant) needed No We needed for NMOS and PMOS (b) (25 points) Describe your process fow in a eft coumn and sketch and abe the cross-sections of the device after each ithography step in a right coumn. The process fow is simiar to a buk CMOS process fow except no we formation and no FOX steps are needed. You have to convert one of the Si isand from n-type to p-type to accommodate the NMOS. Process Description Cross-sections Starting Materia: SOI substrate Process Description Cross Section The foowing soutions is just one of the possibe soutions : Starting Materia: n-si on SOI (shown as A203 in figures) Mask#1 Define p-region opening Boron impantation Remove resist Boron drive-in Gate oxide growth Undoped Poy-Si deposition by CVD Mask#2 Pattern poy gates for both NMOs and PMOS 10

11 Mask#3 Protect PMOS regions (aignment not critica) As impantation to form n+ S/D and n+ gate Mask#4 Protect NMOS regions (aignment not critica) Boron impantation to form p+ S/D and p+ gate Mask #5 Define isoation area which wi be etched away Reactive ion etching of epi Si CVD SiO 2 Mask#6 Contact hoe opening A deposition Mask#7 A patterning 11

12 Probem 6 Nonpanar Device Processing (25 points tota) You found a conceptua process fow of the DELTA (DEpeted Lean-Channe TrAnsistor) SOI MOSFET in a pubished paper. The key idea is to form a vertica Si piar which is eectrica isoated from the substrate by atera therma oxidation of the bottom part of the piar. The top Si piar is then used as the active MOSFET region. Fabrication of this non-panar device structure is expected to be chaenging for severa process modues. In the tabe beow, expain concisey the difficuties you expect to encounter. Process Modue Difficuties Optica Lithography Panarization of photoresist Depth of focus to define gate Reactive Ion Etching Therma Oxidation Source and Drain Doping Meta Contact to Source and Drain Vertica sidewa of Si piar Large Seectivity needed to pattern gate Voume change at piar bottom can tit Si piar Need arge ange impant to doped Si piar sidewas to form S/D [ How to form LDD?] Conforma meta deposition on S/D and panarization 12