Digital Integrated Circuits EECS 312
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1 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) NTT Fujitsu M-780 IBM RY5 Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadrons IBM GP Pentium Radio Receive for Mesh Maintenance 2-6 ma Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9-15 ma Low Power Sleep ma Heartbeat 1-2 ma Time (seconds) Digital Integrated Circuits EECS Teacher: Robert Dick Office: 2417-E EECS dickrp@umich.edu Phone: Cellphone: GSI: Office: Shengshou Lu 2725 BBB luss@umich.edu HW engineers SW engineers Current (ma) IBM ES9000 Bipolar CMOS Power density (Watts/cm 2 ) Year of announcement IBM Z9
2 Review I Inverter noise margins 2 Robert Dick Digital Integrated Circuits
3 Review II Inverter noise margins How can the transfer curve for an inverter be derived from the I V curves of the MOSFETs comprising it? What useful property relevant to the inverter load curve diagram holds in steady state but not when transients are considered? Is the inverter load curve diagram useful for analyzing dynamic systems? 3 Robert Dick Digital Integrated Circuits
4 Midterm exam Inverter noise margins May cover anything up to and including 3 October. Make sure you did the assigned reading. Look though all the on-line slides for anything surprising. Review lab and homework assignments. If you want to study with other students, please use mailing list to find partners. Posted old exams to website. No class on Tuesday. 4 Robert Dick Digital Integrated Circuits
5 Lecture plan Inverter noise margins 1. Inverter noise margins Robert Dick Digital Integrated Circuits
6 V IH and V IL V IH V IL = V OH V OL g V IH = V M V M g = V DD g (1) (2) V IL = V M + V DD V M g (3) NM H = V DD V IH (4) NM L = V IL (5) 6 Robert Dick Digital Integrated Circuits
7 Inverter gain Inverter noise margins Can find gain by taking σv out /σv in at V M. g = 1 k n V DSATn + k p V DSATp I D (V M ) λ n λ p (1) g ( 1 + r V M V Tn V DSATn 2 ) (λ n λ p ) (2) 7 Robert Dick Digital Integrated Circuits
8 Change in transfer curve (and gain) with V DD 8 Robert Dick Digital Integrated Circuits
9 Subthreshold operation Higher gain. Lower current. Increased sensitivity to intrinsic noise. Increased sensitivity to fixed external noise. xkt q 9 Robert Dick Digital Integrated Circuits
10 Impact of process variation on inverter transfer function 10 Robert Dick Digital Integrated Circuits
11 Inverter performance Recall inverter propagation delay expression: t p = 0.69RC. Either decrease R or decrease C. Effective R depends on V DD. 11 Robert Dick Digital Integrated Circuits
12 Dependence of inverter delay on V DD I t phl = C L V DD 4 I DSATn t phl = 0.52 L n W n If V DD V Tn + V DSATn /2 C L V DD k nv DSATn (V DD V Tn V DSATn /2) t phl 0.52 L n C L W n k nv. DSATn Why? R eq = 1 VDD V DD /2 V DD /2 V I DSAT (1 + λv ) dv 3 4 V DD I DSAT ( 1 7 ) 9 λv DD 12 Robert Dick Digital Integrated Circuits
13 Dependence of inverter delay on V DD II where I DSAT = k W L ((V DD V T )V DSAT V DSAT 2 Ignore channel length modulation factor λ. 2 ). 13 Robert Dick Digital Integrated Circuits
14 Review Inverter noise margins Define noise margin and explain why it is a useful concept. What is V M? What influence does an asymmetric change in inverter MOSFET resistance have on the V out V in curve? What is inverter gain and how does it depend on V DD? What happens to inverter delay with decreasing V DD? 14 Robert Dick Digital Integrated Circuits
15 Lecture plan Inverter noise margins 1. Inverter noise margins Robert Dick Digital Integrated Circuits
16 Dependence of delay on width (R) Fix R L C L and vary W. 16 Robert Dick Digital Integrated Circuits
17 Dependence of delay on width (R) Fix R L C L and vary W. Eventually, self-loading dominates. 16 Robert Dick Digital Integrated Circuits
18 Impact of W p /W n ratio Warning: Broken concept, especially for short-chain analysis. β = Wp /W n. t p = t plh+t phl Robert Dick Digital Integrated Circuits
19 Impact of rise time on delay 18 Robert Dick Digital Integrated Circuits
20 Modeling rise time effects in inverter chains t i p = t i step + ηt i 1 step t i step: Delay of gate i in response to step input function. η: Technology-dependent constant, generally near Robert Dick Digital Integrated Circuits
21 Lecture plan Inverter noise margins 1. Inverter noise margins Robert Dick Digital Integrated Circuits
22 Midterm exam I 1 Uses of digital systems. 2 History of digital computing devices. Impact of technology improvements on performance, power consumption, size, and reliability. Bipolar to CMOS move. 3 Power consumption equation and components of total power consumption. Check Slide 19 in lecture notes packet 2. 4 Requirements for devices to permit use in digital system. Regeneration/restoration. 5 MOSFET structure and layout. 6 Schematic capture, e.g., using Cadence software. 7 Resistance basics, and their application to MOSFET channels and metal wires. 21 Robert Dick Digital Integrated Circuits
23 Midterm exam II 8 Basic logic gate and transmission gate structures. 9 NMOS, PMOS, and CMOS inverters. 10 Diode structure and operation. Drift and diffusion. Difference between charge carriers and stationary ions. Doping. 11 MOSFET operation. Change in conditions (especially I D ) with changing V GS, V DS, and V SB. MOSFET models. Cutoff, pinch-off, and velocity saturation. 12 Subthreshold leakage and subthreshold operation. 13 Process variation definition and influence on circuit behavior. 14 High-level understanding of FinFET structure and reason for improved k. 15 Steps in fabrication process. Dual damascene process. 16 Understanding what design rules are. 22 Robert Dick Digital Integrated Circuits
24 Midterm exam III 17 Packaging, MCMs, and board-level design. Implications of packaging and interconnect for performance. 18 Gate leakage. High-κ dielectric. See assigned article. 19 Transient diode and MOSFET behavior. Computing capacitances based on MOSFET structure and operating region. 20 Derivation from inverter transfer curve from MOSFET I V curves. Impact of inverter asymmetry on V M. 21 Noise margin definitions and purpose. Gain definition. 23 Robert Dick Digital Integrated Circuits
25 Upcoming topics Inverter chains for driving large loads. Complex behavior in logic gate. 24 Robert Dick Digital Integrated Circuits
26 Lecture plan Inverter noise margins 1. Inverter noise margins Robert Dick Digital Integrated Circuits
27 assignment 3 October: Read sections 5.3, 5.4.1, and in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, October: Lab October: 2 (which will help in your preparation for the midterm exam). 10 October: Read sections 5.4, 5.5, 5.6, and 3.5 in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, Robert Dick Digital Integrated Circuits
Digital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
Digital Integrated Circuits EECS 312
14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980
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