EE 330 Lecture 21. Bipolar Process Flow
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1 EE 330 Lecture 21 Bipolar Process Flow
2 Exam 2 Friday March 9 Exam 3 Friday April 13
3 Review from Last Lecture Simplified Multi-Region Model I C βi B JSA IB β V 1 V E e V CE BE V t AF V BE >0.4V V BC <0 Forward Active V t kt q V BE =0.7V V CE =0.2V I C <βi B 0<I B Saturation I C =I B =0 V BE <0 V BC <0 Cutoff A small portion of the operating region is missed with this model but seldom operate in the missing region
4 Review from Last Lecture Further Simplified Multi-Region dc Model Equivalent Simplified Multi-Region Model I C βi B VBE 0.6V V t kt q V BE >0.4V V BC <0 Forward Active V BE =0.7V V CE =0.2V I C =I B =0 I C <βi B 0<I B V BE <0 V BC <0 Saturation Cutoff A small portion of the operating region is missed with this model but seldom operate in the missing region
5 Review from Last Lecture Example: Determine I C and V OUT 12V 500K 4K I C V OUT A E =100u 2 J =10 s β 100 A/μ -16 2
6 Review from Last Lecture Example: Determine I C and V OUT 500K 12V 4K Solution: 1. Guess Forward Active Region 2. Solve Circuit with Guess 12V I C V OUT A E =100u 2 J =10 s β 100 A/μ K 500K I C I B V OUT V OUT 0.6V 100I B I B 500K IC I B mA 500K V 12 I 4K 2.88V OUT 3. Verify FA Region C V 0.6V 0.4V BE V 0.6V 2.88V 2.28V 0 BC Verify Passes so solution is valid I V C 2.28mA OUT 2.88V V BE >0.4V and V BC <0
7 Review from Last Lecture Example: Determine I C and V OUT, 12V 50K 4K I C V OUT A E =100u 2 J =10 s β 100 A/μ -16 2
8 Review from Last Lecture Example: Determine I C and V OUT. 50K 12V 4K I C Solution: 1. Guess Forward Active Region 2. Solve Circuit with Guess 12V 50K 4K I C V OUT A E =100u 2 I B V OUT 0.6V 100I B V OUT J =10 s β 100 A/μ I B 50K IC I B mA 50K V 12 I 4K 79.2V OUT C 3. Verify FA Region V BE >0.4V and V BC <0 V 0.6V 0.4V BE V 0.6V 79.2V 79.8V 0 BC Verify Fails so solution is not valid
9 Review from Last Lecture Example: Determine I C and V OUT 50K 12V 4K Solution: 4. Guess Saturation 5. Solve Circuit with Guess 12V I C V OUT A E =100u 2 50K I B V OUT 0.6V 0.2V 4K I C V OUT J =10 s β 100 A/μ OUT IB 228 A 50K IC 2.95mA 4K V 0.2V 6. Verify SAT Region I C <βi B I A 22.8mA I C B 2.95mA I 2.95mA I 22.8mA C B Verify Passes so solution is valid I 2.95mA V 0.2V C OUT
10 Review from Last Lecture Example: Determine I C and V OUT. Assume C is large and V IN is very small. 12V 500K 4K I C C V OUT A E =100u 2 V IN J =10 s β 100 A/μ -16 2
11 Review from Last Lecture Example: Determine I C and V OUT. Assume C is large and V IN is very small. 12V Solution: V IN C 500K 4K I C V OUT A E =100u 2 J =10 s β 100 A/μ Assume V IN =0, then no current flows through C so circuit is identical to circuit of previous-previous example so I 2.28mA V 2.88V C OUT Note: Since V IN is coupled directly to base, will amplify V IN if it is a small time varying signal and gain will be very large
12 Bipolar Process Description p-substrate epi
13 Components Shown Vertical npn BJT Lateral pnp BJT JFET Diffusion Resistor Diode (and varactor) Note: Features intentionally not to scale to make it easier to convey more information on small figures Much processing equipment is same as used for MOS processes so similar minimum-sized features can be made But will see that there are some fundamental issues that typically make bipolar circuits large
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16 Note some features have very large design rules Will discuss implication of this later
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23 In contrast to the MOSFET where process parameters are independent of geometry, the bipolar transistor model is for a specific transistor! Area emitter factor is used to model other devices Often multiple specific device models are given and these devices are used directly Often designer can not arbitrarily set A E but rather must use parallel combinations of specific devices and layouts
24 C D A A B B C Top View D
25 Layer Mappings n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
26 A A B B Dimmed features with A-A and B-B cross sections
27 A A B B
28 B C E E C vertical npn B B C E C B lateral pnp E C B E E B C
29 Diode (capacitor) G S W L D D S D G Resistor G S n-channel JFET
30 Detailed Description of First Photolithographic Steps Only Top View Cross-Section View
31 A A B B n + buried collector
32 Mask Numbering and Mappings Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7 n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
33 Mask 1: n + buried collector A A B B
34 Photoresist n Exposure Develop + buried collector mask A-A Section B-B Section
35 Implant A-A Section B-B Section
36 Strip Photoresist A-A Section B-B Section
37 p-substrate A A B n + buried collector n + buried collector B
38 Grow Epitaxial Layer A-A Section Note upward and downward diffusion of n+ buried collector B-B Section
39 Grow Epitaxial Layer p-substrate A A B n + buried collector n + buried collector B
40 A A B B Isolation Diffusion
41 Mask Numbering and Mappings Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7 n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
42 Mask 2: Isolation Deposition/Diffusion A A B B
43 Isolation Deposition/Diffusion Photoresist present but not shown Deposition and diffusion combined in slides A-A Section B-B Section
44 Isolation Diffusion p-substrate A A A A B B n + buried collector n + buried collector B Have created 5 islands of n - material on top of p -- substrate
45 A A B B p-base diffusion
46 Mask Numbering and Mappings Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7 n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
47 Mask 3: p-base diffusion A A B B
48 p-base Diffusion Photoresist present but not shown Deposition and diffusion combined in slides A-A Section B-B Section
49 p-base Diffusion p-substrate A A A A B B n + buried collector n + buried collector B
50 A A B B n + emitter diffusion
51 Mask Numbering and Mappings Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7 n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
52 Mask 4: n + emitter diffusion A A B B
53 n + emitter Diffusion Photoresist present but not shown Deposition and diffusion combined in slides A-A Section B-B Section
54 n + emitter Diffusion p-substrate A A A A B B n + buried collector n + buried collector B
55 Oxidation A-A Section B-B Section
56 Oxidation p-substrate A A A B B n + buried collector n + buried collector B
57 A A B B contacts
58 Mask Numbering and Mappings Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7 n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
59 Mask 5: contacts A A B B
60 Contact Openings Photoresist present but not shown Deposition and diffusion combined in slides A-A Section B-B Section
61 Contact Openings p-substrate A A A A B B n + buried collector n + buried collector B
62 A A B B metal
63 Mask Numbering and Mappings Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7 n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
64 Mask 6: metal A A B B
65 Metalization Photoresist present but not shown A-A Section B-B Section
66 Pattern Metal A-A Section B-B Section
67 Metalization p-substrate A A A A B B n + buried collector n + buried collector B
68 Pattern Metal p-substrate A A A A B B n + buried collector n + buried collector B
69 B C E E C vertical npn B A-A Section B C E C B E lateral pnp C B E B C E B-B Section
70 G D A-A Section S D S p-channel JFET G B-B Section
71 B C E E C vertical npn B B C E C B lateral pnp E C B E E B C
72 Diode (capacitor) G S W L D D S D G Resistor G S n-channel JFET
73 Mask Numbering and Mappings Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7 n + buried collector isolation diffusion (p + ) p-base diffusion n + emitter contact metal passivation opening Notes: passivation opening for contacts not shown isolation diffusion intentionally not shown to scale
74 Pad and Pad Opening p-substrate Epitaxial Layer Oxidation Metalization Protective Layer Pad Opening Mask Pad Opening
75 The vertical npn transistor Emitter area only geometric parameter that appears in basic device model Transistor much larger than emitter Multiple-emitter devices often used (TTL Logic) and don t significantly increase area
76 MOS and Bipolar Area Comparisions How does the area required to realize a MOSFET compare to that required to realize a BJT? Will consider a minimum-sized device in both processes
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79 Consider Initially the Emitter in the BJT surrounded by a base region
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82 From design rules (left to right) 4.3, 5.1, 5.4, 5.6,
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84 Add n+ buried for collector From design rule
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86 Add n-epi region from design rules 2.3 and
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88 1 5 Add contact to n-epi region from design rules 2.3 and
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91 1 5 But, there are some rather strict rules relating to the epi contact from (left to right) rules 4.4, 5.4, NOT TO SCALE Note: 26 required Between p-base and isolation diffusion 55
92 Consider a structure with a collector contact on both sides of epi Note: Not to vertical Scale Note: 26 required Between p-base and isolation diffusion
93 Note: Not to vertical Scale Note: 26 required Between p-base and isolation diffusion 50 55
94 Note: Not to vertical Scale 50 55
95 Note: Not to vertical Scale Bounding Area = Major contributor to large size of BJT is the isolation diffusion which diffuses laterally a large distance beyond the drawn edges of the isolation mask
96 Comparison with Area for n-channel MOSFET in Bulk CMOS Bounding Area =
97 Minimum-Sized MOSFET Bounding Area = Active Area =
98 MOSFET BJT Note: Not to vertical Scale
99 Area Comparison between BJT and MOSFET BJT Area = n-channel MOSFET Area = Area Ratio = 21:1
100 End of Lecture 21
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