Lecture 400 Oversampling ADCs Part II (3/29/10) Page 400-1

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1 Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4001 LECTURE 400 OVERSAMPLING ADCS PART II LECTURE ORGANIZATION Outline Implementation of modulators Decimation and filtering Bandpass modulators Digitalanalog oversampling converters Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages Lecture 400 Oversampling ADCs Part II (3/29/10) Page 4002 IMPLEMENTATION OF MODULATORS Modulators The Analog Part of the Oversampling ADC Most of today s deltasigma modulators use fully differential switched capacitor circuits. Advantages are: Doubles the signal swing and increases the dynamic range by 6dB Commonmode signals that may couple to the signal through the supply lines and substrate are canceled Charge injected by the switches are canceled to a firstorder Example: First integrator dissipates the most power and requires the most accuracy. V Ref Y φ 1d φ 1d X V Ref YB C C 0.5z1 1 z1 φ 1 φ 2 φ 2 2C 0.5z1 1 z1 V Ref Y φ 1d φ 1d V Ref YB C C Q 1 Y 2C φ 1 φ 1 φ 2 φ 2 Y YB YB Y V Ref V Ref φ 1 2C YB Y V Ref V Ref φ 1 2C Fig

2 Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98db AnalogDigital Converter α E X a 1 z 1 y 1 a 2 z 1 y 2 a 3 z 1 y 3 a 4 z 1 y 4 1bit A/D Y b 1 b 2 Fig where a 1 = 1/3, a 2 = 3/25, a 3 = 1/10, a 4 = 1/10, b 1 = 6/5, b 2 = 1 and = 1/6 Advantages: The modulator combines the advantages of both DFB and DFF type modulators: Only four op amps are required. The 1st integrator s output swing is between ±V REF for large input signal amplitudes (0.6V REF ), even if the integrator gain is large (0.5). A local resonator is formed by the feedback around the last two integrators to further suppress the quantization noise. The modulator is fully pipelined for fast settling. 1bit D/A A.L. Coban and P.E. Allen, A 1.5V, 1mW Audio Modulator with 98dB Dynamic Range, Proc. of 1999 Int. SolidState Circuits Conf., Feb. 1999, pp Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98dB AnalogDigital Converter Continued Integrator power dissipation vs. integrator gain DR = 98 db BW = 20 khz Cs = 5 pf 0.5 μm CMOS

3 Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98db AnalogDigital Converter Continued Modulator power dissipation vs. oversampling ratio OSR = 64 OSR = 32 OSR = 16 OSR = 8 DR = 98 db BW = 20 khz Integrator gain = 1/3 0.5μm CMOS Suppy Voltage (V) Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98dB AnalogDigital Converter Continued Circuit Implementation: Capacitor Values Capacitor Integrator 1 Integrator 2 Integrator 3 Integrator 4 Cs 5.00pF 0.15pF 0.30pF 0.10pF Ci 15.00pF 1.25pF 3.00pF 1.00pF Ca 0.05pF Cb1 0.12pF Cb2 0.10pF 1 1d 2 2d Fig

4 Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98dB AnalogDigital Converter Continued Microphotograph of the modulator. Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98dB AnalogDigital Converter Continued Measured SNR and SNDR versus input level of the modulator.

5 Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98dB AnalogDigital Converter Continued Measured baseband spectrum for a 7.5dBr 1kHz input. Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98dB AnalogDigital Converter Continued Measured baseband spectrum for a 80dBr 1kHz input. 80 dbr, 1 khz signal VREF = 1.5 V (diff.) 2048point FFT frequency, (khz)

6 Lecture 400 Oversampling ADCs Part II (3/29/10) Page V, 1mW, 98dB AnalogDigital Converter Continued Measured 4thOrder Modulator Characteristics: Table 5.4 Measured fourthorder deltasigma modulator characteristics Technology : 0.5 μm triplemetal singlepoly nwell CMOS process Supply voltage 1.5 V Die area 1.02 mm x 0.52 mm Supply current 660 μa analog part 630 μa digital part 30 μa Reference voltage 0.75V Clock frequency MHz Oversampling ratio 64 Signal bandwidth 20kHz Peak SNR 89 db Peak SNDR 87 db Peak S/D 101dB HD 5dBv 2kHz input 105dBv DR 98 db Lecture 400 Oversampling ADCs Part II (3/29/10) Page DECIMATION AND FILTERING DeltaSigma ADC Block Diagram The decimator and filter are implemented digitally and consume most of the area and the power. Function of the decimator and filter are; 1.) To attenuate the Analog Input x(t) f B Δ Modulator (Analog) Decimator (Digital) Lowpass Filter (Digital) quantization noise above the baseband 2.) Bandlimit the input signal 3.) Suppress outofband spurious signals and circuit noise Most of the ADC applications demand decimation filters with linear phase characteristics leading to the use of finite impulse response (FIR) filters. FIR filters: For a specified ripple and attenuation, Number of filter coefficients f s f t where f s is the input rate to the filter (clock frequency of the quantizer) and f t is the transition bandwidth. f S f D <f S 2f B Digital PCM Fig

7 Lecture 400 Oversampling ADCs Part II (3/29/10) Page A MultiStage Decimation Filter To reduce the number of stages, the decimation filters are implemented in several stages. Typical multistage decimation filter: f s f s /D 2f N f N L1th order Firsthalf band filter Secondhalf band filter Droop correction f N Fig ) For modulators with (1z1)L noise shaping comb filters are very efficient. Comb filters are suitable for reducing the sampling rate to four times the Nyquist rate. Designed to supress the quantization noise that would otherwise alias into the signal band upon sampling at an intermediate rate of f s1. 2.) The remaining filtering is performed by in stages by FIR or IIR filters. Supresses outofband components of the signal 3.) Droop correction may be required depending upon the ADC specifications Lecture 400 Oversampling ADCs Part II (3/29/10) Page Comb Filters A comb filter that computes a running average of the last D input samples is given as y[n] = 1 D 1 D x[ni] i = 0 where D is the decimation factor given as D = f s f s1 The corresponding zdomain expression is, D H D (z) = z i = 1 1 zd D 1 z 1 i = 1 The frequency response is obtained by evaluating H D (z) for z = ej2 fts, H D (f) = 1 sin fdt s D sin ft s e j2 ft s/d where T s is the input sampling period (=1/f s ). Note that the phase response is linear. For an Lth order modulator with a noise shaping function of (1z1)L, the required number of comb filter stages is L1. The magnitude of such a filter is, HD(f) = 1 D sin fdt s sin fts K

8 Lecture 400 Oversampling ADCs Part II (3/29/10) Page Magnitude Response of a Cascaded Comb Filter K = 1,2 and 3 0 HD(f) db K = 1 K= 2 K = f f b s 2 f s 3 f s 4 f s D D D D Frequency Fig Lecture 400 Oversampling ADCs Part II (3/29/10) Page Implementation of a Cascaded Comb Filter Implementation: X z1 z1 Numerator Section z1 K = L 1 Integrators Denominator Section z1 z1 z1 K = L 1 Differentiators Fig Comments: 1.) The L1 integrators operating at the sampling frequency, f s, realize the denominator of H D (z). 2.) The L1 differentiators operating at the output rate of f s1 (= f s /D) realize the numerator of H D (z). 3.) Placing the integrator delays in the feedforward path reduces the critical path from L1 adder delays to a single adder delay. f s /D Y

9 Lecture 400 Oversampling ADCs Part II (3/29/10) Page Implementation of Digital Filters Digital filter structures: x(n) h(0) y(n) Input Output z1 h(1) y(n) Output z1 h(0) h(1) x(n) Input z1 h(2) z1 h(2) z1 h(3) z1 h(3) z1 h(n1) z1 h(n1) Directform structure for an FIR digital filter. Transposed directform FIR filter structure. Fig S.R. Norsworthy, R. Schreier, and G.C. Temes, DeltaSigma Data ConvertersTheory, Design, and Simulation, IEEE Press, NY, Chapter 13, Lecture 400 Oversampling ADCs Part II (3/29/10) Page Digital Lowpass Filter Example of a typical digital filter used in removal of the quantization noise at higher frequencies Magnitude (db) Frequency (Hz)

10 Lecture 400 Oversampling ADCs Part II (3/29/10) Page Illustration of the DeltaSigma ADC in Time and Frequency Domain f S f D analog input fb MODULATOR DECIMATOR LOWPASS FILTER 2fB digital PCM Time Time Frequency Frequency Frequency Lecture 400 Oversampling ADCs Part II (3/29/10) Page BANDPASS DELTASIGMA MODULATORS Bandpass Modulators f S Block diagram of a bandpass modulator: x Resonator v y A/D Components: Resonator a bandpass filter of order u D/A 2N, N= 1, 2,... Fig A Quantizer Coarse quantizer (1 bit or multibit) The noiseshaping of the bandpass oversampled ADC has the following interesting characteristics: Center frequency = f s (2N1)/4 Bandwidth = BW = f s /M Illustration of the Frequency Spectrum db (N=1): Attenuation BW BW Application of the bandpass ADC is for systems with narrowband signals (IF frequencies) 0 f s4 3f s 4 f s Frequency Fig. 1132

11 Lecture 400 Oversampling ADCs Part II (3/29/10) Page A FirstOrder Bandpass Modulator Bandpass Resonator: V(z) = z1 [X(z) z1v(z)] = z1x(z) z2v(z) V(z) (1z2) = z1x(z) V(z) X(z) = z 1 1z2 Modulator: Q(z) X(z) z1 z1 V(z) Fig C X(z) z1 1z2 Fig B Y(z) = Q(z) [X(z) Y(z)] z1 1z2 Y(z) = 1z2 1 z1z2 Q(z) z1 1 z1z2 X(z) NTF Q (z) = 1z2 1 z1z2 The NTF Q (z) has two zeros on the j axis. Y(z) Lecture 400 Oversampling ADCs Part II (3/29/10) Page Resonator Design Resonators can be designed by applying a lowpass to bandpass transform as follows: X(z) z1 V(z) z1 1 z1 Replace z1 by z2 X(z) z2 V(z) z2 1 z2 Result: Simple way to design the resonator Inherits the stability of a lowpass modulator Center frequency located at f s /4 Fig D

12 Lecture 400 Oversampling ADCs Part II (3/29/10) Page FourthOrder Bandpass Modulator Block diagram: X(z) z z2 0.5 z2 1 z2 Y(z) Fig E Comments: Designed by applying a lowpass to bandpass transform to a secondorder lowpass modulator The stabilty and SNR characteristics are the same as those of a secondorder lowpass modulator The zdomain output is given as, Y(z) = z4x(z) (1z2)2Q(z) The zeros are located at z = ±j which corresponds to notches at f s /4. Lecture 400 Oversampling ADCs Part II (3/29/10) Page Resonator Circuit Implementation Block diagram of z2/(1z2): X(z) z1 z1 V(z) Fully differential switchcapacitor implementation: Fig F

13 Lecture 400 Oversampling ADCs Part II (3/29/10) Page Power Spectral Density of the Previous FourthOrder Bandpass Modulator Simulated result: Lecture 400 Oversampling ADCs Part II (3/29/10) Page DELTASIGMA DIGITALTOANALOG CONVERTERS Principles The principles of oversampling and noise shaping are also widely used in the implementation of DACs. Simplified block diagram of a deltasigma DAC: Input Nbit f N Interpolation filter Nbit Mf N Digital Section Digital deltasigma modulator 1bit Mf N DAC Mf N Analog Section Analog lowpass filter Output Fig Operation: 1.) A digital signal with Nbits with a data rate of f N is sampled at a higher rate of Mf N by means of an interpolator. 2.) Interpolation is achieved by inserting 0 s between each input word with a rate of Mf N and then filtering with a lowpass filter. 3.) The MSB of the digital filter is applied to a DAC which is applied to an analog lowpass filter to achieve the analog output.

14 Lecture 400 Oversampling ADCs Part II (3/29/10) Page Block Diagram of a DAC Digital Input f N Interpolation f S f S f S =Mf N f S Digital Filter f S Digital Code Conversion = = 1 Analog Analog Output Lowpass Filter MSB f S V Ref y(k) V Ref DAC Fig Operation: 1.) Interpolate a digital word at the conversion rate of the converter (f N ) up to the sample frequency, f s. 2.) The word length is then reduced to one bit with a digital sigmadelta modulator. 3.) The one bit PDM signal is converted to an analog signal by switching between two reference voltages. 4.) The highfrequency quantization noise is removed with an analog lowpass filter yielding the required analog output signal. Sources of error: Device mismatch (causes harmonic distortion rather than DNL or INL) Component noise Device nonlinearities Clock jitter sensitivity Inband quantization error from the modulator Lecture 400 Oversampling ADCs Part II (3/29/10) Page Frequency Viewpoint of the DAC Frequency spectra at different points of the deltasigma ADC: Magnitude Input 0.5f N 0 0.5f N f N (M1)f N Mf N Interpolation filter output Frequency 0.5f N 0 0.5f N Mf N Frequency Deltasigma modulator output 0.5f N 0 0.5f N Mf N Frequency Lowpass filter output Quantization noise after filtering 0.5f N 0 0.5f N Mf N Frequency Fig10.933

15 Lecture 400 Oversampling ADCs Part II (3/29/10) Page A ThirdOrder, Modulator for a DAC A digital equivalent of the thirdorder MASH modulator is shown below. X Digital Inputs Y 8state Output XY Latch XY Latch Clk Overflow flow Over Overflow Clk z 1 z 1 XY Latch Clk The mbit accumulators consist of an mbit adder and mbit latches. The 8state digital output is converted to an analog through means of an analog filter. Spectral outputs: Lecture 400 Oversampling ADCs Part II (3/29/10) Page BitDAC for the DigitaltoAnalog Converter The Analog Part The MSB output from the digital filter is used to drive a 1bit DAC. Possible architectures: V Ref I Ref φ 1 Analog y(k) φ 2 lowpass Analog φ 2 y(k) R filter Output with 3dB C φ φ frequency 2 1 y(k) of y(k) 0.5fN I Ref V Ref Voltagedriven DAC with a passive lowpass filter stage. C R Analog lowpass filter with 3dB frequency of 0.5fN Currentdriven DAC with a passive lowpass filter stage. Analog Output Fig A multibit output would consist of more parallel, controlled current sources and sinks.

16 Lecture 400 Oversampling ADCs Part II (3/29/10) Page SwitchedCapacitor DAC and Filter Typically, the DAC and the first stage of the lowpass filter are implemented using switchedcapacitor techniques. φ 1 y(k) φ 1 y(k) V Ref V Ref C 2 C 1 φ 2 φ 2 φ 1 R To analog lowpass filter Fig It is necessary to follow the switchedcapacitor filter by a continuous time lowpass filter to provide the necessary attenuation of the quantization noise. Lecture 400 Oversampling ADCs Part II (3/29/10) Page SUMMARY Comparison of the Various Types of ADCs Speed (Expressed in terms of T a clock period) Area Dependence on the number of bits, N, or other ADC parameters A/D Converter Type Maximum Practical Number of Bits (±1) Dual Slope 1214 bits 2(2NT) Independent Successive Approximation 1215 bits NT N with selfcorrection 1Bit Pipeline 10 bits T (After NT delay ) N Algorithmic 12 bits NT Independent Flash 6 bits T 2N Twostep, flash 1012 bits 2T 2N/2 Mulitplebit, Mpipe 1214 bits MT 2N/M Oversampled (1bit, L loops and M= oversampling ratio = f clock/2fb) 1517 bits MT L

17 Lecture 400 Oversampling ADCs Part II (3/29/10) Page Comparison of Recent ADCs Resolution versus conversion rate: Output word length Flash Pipelined Algorithmic Successive approximation Dualslope Deltasigma Folding/Interpolating Bandpass deltasigma Conversion rate, (samples/sec.) Figure Lecture 400 Oversampling ADCs Part II (3/29/10) Page Comparison of Recent ADCs Continued Power dissipation versus conversion rate: Power Dissipation (mw) Flash Pipelined Successive approximation Deltasigma Folding/Interpolating Bandpass deltasigma Conversion Rate (Samples/second) Figure

18 Lecture 400 Oversampling ADCs Part II (3/29/10) Page References for Previous Figures [1] A 12b, 60MSample/s Cascaded Folding and Interpolating ADC. Vorenkamp, P., IEEE JSC, vol. 32, no. 12, Dec [2] A 15b, 5Msample/s LowSpurious CMOS ADC. Kwak, S. U., IEEE JSC, vol. 32, no. 12, Dec [3] Error Suppressing Encode Logic of FCDL in a 6b Flash A/D Converter. Ono, K., IEEE JSC, vol. 32, no.9, Sep [4] A Cascaded SigmaDelta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 db SNR. Brooks, T. L., IEEE JSC, vol.32, no.12, Dec [5] A 10b, 100 MS/s CMOS A/D Converter. Kwang Young Kim, IEEE JSC, vol. 32, no. 3, Mar [6] A 1.95V, 0.34mW, 12b SigmaDelta Modulator Stabilized by Local Feedback Loops. Au, S., IEEE JSC, vol. 32, no. 3, Mar [7] A 250mW, 8b, 52Msamples/s ParallelPipelined A/D Converter with Reduced Number of Amplifiers. Nagaraj, K., IEEE J SC, vol. 32, no. 3, Mar [8] A DSPBased Hearing Instrument IC. Neuteboom, H., IEEE JSC, vol. 32, no. 11, Nov [9] An Embedded 240mW 10b 50MS/s CMOS ADC in 1mm 2. Bult, K., IEEE JSC, vol. 32, no. 12, Dec [10] LowVoltage DoubleSampled Converters. Senderowicz, D., IEEE JSC, vol. 32, no.12, Dec [11] Quadrature Bandpass Modulation for Digital Radio. Jantzi, S. A., IEEE JSC, vol. 32, no. 12, Dec [12] A TwoPath Bandpass Modulator for Digital IF Extraction at 20 MHz. Ong, A. K., IEEE JSC, vol. 32, no. 12, Dec [13] A 240Mbps, 1W CMOS EPRML ReadChannel LSI Chip Using an Interleaved Subranging Pipeline A/D Converter. Matsuura, T., IEEE JSC, vol. 33, no. 11, Nov [14] A 13Bit, 1.4 MS/s SigmaDelta Modulator for RF Baseband Channel Applications. Feldman, A. R., IEEE JSC, vol. 33, no. 10, Oct [15] Design and Implementation of an Untrimmed MOSFETOnly 10Bit A/D Converter with 79dB THD. Hammerschmied, C. M., IEEE JSC, vol. 33, no. 8, Aug [16] A 15b Resolution 2MHz Nyquist Rate ADC in a 1μm CMOS Technology. Marques, A. M., IEEE JSC, vol. 33, no. 7, Jul [17] A 950MHz IF SecondOrder Integrated LC Bandpass DeltaSigma Modulator. Gao, W., IEEE JSC, vol. 33, no. 5, May [18] A 200MSPS 6Bit Flash ADC in 0.6μm CMOS. Dalton, D., IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 11, Nov Lecture 400 Oversampling ADCs Part II (3/29/10) Page References Continued [19] A 5V SingleChip DeltaSigma Audio A/D Converter with 111 db Dynamic Range. Fujimori, I., IEEE JSC, vol. 32, no. 3, Mar [20] A 256 x 256 CMOS Imaging Array with Wide Dynamic Range Pixels and ColumnParallel Digital Output. Decker, S., IEEE JSC, vol. 33, no.12, Dec [21] A 400 Msample/s, 6b CMOS Folding and Interpolating ADC. Flynn, M., IEEE JSC, vol. 33, no.12, Dec [22] An Analog Background Calibration Technique for TimeInterleaved AnalogtoDigital Converters. Dyer, K. C., IEEE JSC, vol. 33, no.12, Dec [23] A CMOS 6b, 400Msample/s ADC with Error Correction. Tsukamoto, S., IEEE JSC, vol. 33, no.12, Dec [24] A Continuously Calibrated 12b, 10MS/s, 3.3V ADC. Ingino, J. M., IEEE JSC, vol. 33, no.12, Dec [25] A DeltaSigma PLL for 14b, 50 ksamples/s FrequencytoDigital Conversion of a 10 MHz FM Signal. Galton, I., IEEE J SC, vol. 33, no.12, Dec [26] A Digital Background Calibration Technique for TimeInterleaved AnalogtoDigital Converters. Fu, D., IEEE JSC, vol. 33 no.12, Dec [27] An IEEE 1451 Standard Transducer Interface Chip with 12b ADC, Two 12b DAC s, 10kB Flash EEPROM, and 8b Microcontroller. Cummins, T., IEEE JSC, vol. 33, no.12, Dec [28] A SingleEnded 12bit 20 Msample/s SelfCalibrating Pipeline A/D Converter. Opris, I. E., IEEE JSC, vol. 33, no.12, Dec [29] A 900mV LowPower A/D Converter with 77dB Dynamic Range. Peluso, V., IEEE JSC, vol. 33, no.12, Dec [30] ThirdOrder Modulator Using SecondOrder NoiseShaping Dynamic Element Matching. Yasuda, A., IEEE JSC, vol. 33, no.12, Dec [31] R, G, B Acquisition Interface with LineLocked Clock Generator for Flat Panel Display. Marie, H., IEEE JSC, vol. 33, no.7, Jul [32] A 25 MS/s 8b 10 MS/s 10b CMOS Data Acquisition IC for Digital Storage Oscilloscopes. Kusayanagi, N., IEEE JSC, vol. 33, no.3, Mar [33] A Multimode Digital Detector Readout for SolidState Medical Imaging Detectors. Boles, C. D., IEEE JSC, vol. 33, no.5, May [34] CMOS ChargeTransfer Preamplifier for OffsetFluctuation Cancellation in Low Power A/D Converters. Kotani, K., IEEE J SC, vol. 33, no.5, May [35] Design Techniques for a LowPower LowCost CMOS A/D Converter. Chang, DongYoung, IEEE JSC, vol. 33, no.8, Aug

19 Lecture 400 Oversampling ADCs Part II (3/29/10) Page CONCLUDING THOUGHTS What is analog circuit design? The complex process of creating circuit solutions using analog circuit techniques. What is the analog integrated circuit design process? The even more complex process of combining analog design with IC technology which includes electrical, physical and test design. What are the key principles, concepts and techniques for analog IC design? Key principles Fundamental laws Key concepts Important relationships and ideas Key techniques Tools that allow simplification or insight How can the analog IC designer enhance creativity and solve new problems in today s industrial environment? Learn the key principles, concepts and techniques of analog circuit design Learn from mistakes Learn the technology Always try to understand the concept and operation of the circuit, never rely on a computer or someone else for this understanding Technology changes but principles, concepts and techniques remain the same.