Analog/RF design techniques

Transcription

1 Analog/RF design techniques in 28nm technology Andreia Cathelin, fellow STMicroelectronics, Crolles Shanghai, September 25, 2017

2 Fully depleted Silicon-on-Insulator (FD-SOI) 3 High k / metal gate FBB 0 1.1V Power and energy efficiency Elevated SD Total dielectric isolation Analog performance for mixed signal and RF design No channel doping Thin silicon film No pocket implant Robustness for mission critical applications Thin buried oxide <100> substrate FD-SOI is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance

3 ST 28nm FD-SOI Transistor Flavors Low VT (LVT) CMOS in FD-SOI; flipped-well VBBN D NMOS G BOX N-Well PMOS S P-Sub D PMOS G BOX NMOS S P-Well VBBP LVT NMOS LVT PMOS Nominal VBB GND GND Biasing mode FBB FBB Bulk type CMOS 4 VBBP D G BOX N-Well S P-Sub D G S BOX P-Well VBBN RVT PMOS RVT NMOS VDD GND -3 Vdd/ RBB RBB -3 3 Vdd/ Vth (V) RBB FBB FBB RBB NLVT NRVT PLVT PRVT Regular VT (RVT) CMOS in FD-SOI VB (V)

4 for Simpler Analog Integration 5 ST 28nm FD- SOI makes analog/rf/hs designer s life easier Improved Analog Performance Improved Noise Efficient Short Devices Very large V T tuning range High performance frequency behavior Speed increase in all analog blocks Higher gain for a given current density Lower gate and parasitic capacitance Lower noise variability Better matching for short devices and efficient design with L>L min Analog parameters wide range tuning via a new independent tuning knob (back-gate) f T / f max >300GHz for LVTNMOS and high performance passives enabling RF/mmW/HS integration with technology margin Higher bandwidth Lower power Smaller designs Improved design margins wrt PVT variations Novel flexible design architectures

5 Advantages in Analog Design 6 Efficient Short Devices Improved Analog Perf. Improved Noise DC gain-lin (Gm/Gds) 28FDSOI 28LP bulk Gm/Id (1/V) 28FDSOI 28LP bulk Input ref. voltage For NLVT W=1µm/L=1µm 28LP bulk Gate lenght (m) Gate lenght (m) 28FDSOI Avt (mv.µm) Curves for W=1µm 28LP bulk 28FDSOI Gate lenght (m) Efficient use of short devices : High analogue Low L Low Vt mismatch (Avt ~ 2mV.µm) Performance example: A 1µm/100nm device has a DC gain of 80 & a svt of only 6mV Higher Gm for a given current density Cgg (ff/µm) 28LP bulk 28FDSOI Lower gate capacitance Gate lenght (m) Higher achievable bandwidth or lower power for a given bandwidth Input ref. voltage For NLVT W=1µm/L=120nm 28FDSOI 28LP bulk For NLVT MOS 1µA drain current, get 1.5dB lower 1/f noise in FDSOI Idrain/W (µa/µm) Idrain/W (µa/µm)

6 V T [mv] Advantages in Analog Design-II 7 Very large V T tuning range by FBB Bulk FD-SOI ST 28nm LVT NMOS (typical) Forward body bias [V] VBBN D NMOS G BOX N-Well S D P-Sub PMOS G S BOX P-Well VBBP LVT NMOS P-Sub LVT PMOS +3V 0V Nominal VBB GND GND FBB VBBN VBBP -3 VBBN Flip-well devices: Large Forward Body Bias (FBB) range Negligible control current Use back-gate as «VT tuning knob»: Unprecendented ~250mV of tuning range for FD-SOI vs. ~ 10 s mv in any bulk VBBP FD-SOI (flip-well flavor/lvt devices) D PMOS G S D NMOS BOX BOX N-Well P-Well G S VBBN RVT PMOS RVT Biasin FBB -3V VDD P-sub

7 Advantages in RF/mmW Design 8 Active devices high frequency performance Performant passive devices Few passive devices examples: Inductor L=0.5nH 8ML For ST 28nm FD-SOI LVTNFET: f T / f max >300GHz For RF operation frequency : Work with L = 100nm MAG = NFmin ~ 10GHz current density: 125 µa/µm For mmw operation frequency (intrinsic models): Lmin MAG = NFmin ~ 60GHz current density: 200 µa/µm 33% less power than in 28LP bulk Varactor C=50fF Tline: Zc=50 Ohm, 8ML

8 Drain Source Drain Source Example of mmw- full BEOL implementation of RF transistor 9 Top View Cross Section Starting from Design Kit Pcell (up to M1): Gate compliant with EM current density C minimize transistor f t /f max degradation: Thin stair-case accesses for low fringe parasitic capacitors between drain and source and minimize parasitics to gate Dual gate access for improving gate resistance NLVT MOS in 10ML BEOL L = 30nm W finger = 800nm W total = 16µm N fingers = 20 I drain = 5.2mA Simulation PCell Gate Simulation Pcell + Back End Measurement f T 295 GHz 253 GHz 246 GHz f max 394 GHz 370 GHz 359 GHz H21 U -20dB/dec f max f T Nota: on-wafer measurements with classical pads and access de-embedding method; Measurements performed on GHz and GHz test benches independently [R. Guillaume at al, RFIC2017]

9 Advantages in Mixed Signal Design 10 Variability Switch performance Lower capacitance Vth (mv) 28lp bulk Tighter process corners and less random mismatch than competing processes Benefits: 28FDSOI Slow Typ Fast Slow Typ Fast Gate lenght (m) Simpler design process, shorter design cycle Improved yield or improved performance at given yield Improved gate control allows smaller VTH Backgate bias allows for VTH reduction by tuning Results is an unprecedented quality of analog switches Compounding benefits: smaller R -> smaller switch -> compact layout -> lower parastics -> even smaller switch Key for high performance data converters and other Switched-Cap. Circuits Lower junction capacitance makes a substantial difference in high-speed circuits Drastic reduction of self-loading in gain stages Drastic reduction of switch selfloading Two-fold benefit: Leads to incremental improvements Allows the designer to use circuit architectures that would be infeasible/inefficient in bulk technologies

10 [S] [S] [Hz] «Front side» transistor parameters monitoring for Vbody variation (measured data) 11 Red Vbody = 0V Blue Vbody = 2V [A] [A] [A] DC data, Gm vs ids Vbody = 0 2V Vds = 1.1V RF 10GHz, Gm vs ids Vbody = 0 2V Nfingers = 20 RF 10GHz, f T vs ids Vbody = 0 2V Nfingers = 20 *: intrinsic device (Pcell) Vbody has no impact on «front-side» transistor parameters (Gm, f T ), at a given drain current

11 electrical models and implementation in 28FDSOI DP

12 Leti-UTSOI: a Ψ S compact model based on PSP model for SOI 13 SOI device physics imply taking into consideration new phenomena: Interface coupling, does not exist in bulk new drain-source currents distribution; gate to bulk tunneling current does not exists in SOI Short channel effect: bulk type charge sharing is replaced by 2D electrostatic behavior Self heating effect; negligible in bulk The Leti- UTSOI2 model: a surface potential compact model including the bottom interface inversion (thin buried oxide with non-zero substrate bias) Id (A) Id (A) Id (A) V (V) GS V DS =0.9 V V (V) GS V BS =0.0 V V GS =0.0, V V DS =50 mv V BS =-5, 0 & 5 V V BS =-5, 0 & 5 V gm (A/V) gm (A/V) gd (A/V) V DS =50 mv V BS =-5, 0 & 5 V V (V) GS V DS =0.9 V V BS =-5, 0 & 5 V V (V) 10-2 GS V GS =0.9 V & V BS =0.0 V V DS (V) V DS (V)

13 LETI-UTSOI2: full back-interface modeling Signature of inversion channel at the SOI back interface Vb from -10V to +10V Vb from -1.8V to +3.6V Dots: Measurements Lines: LETI-UTSOI2 LETI-UTSOI2 model well captures all the effects due to inversion channel formation at the SOI back interface in Forward Body Bias (Vb>0) regime, both in DC and AC

14 RF subcircuit 15 Leti-UTSOI 2 takes into consideration: Intrinsic charges (Cox, Cinv, Cbox) Id, Ig Source/Drain access resistances Parasitic capacitances: Cfr, Cgbov RF Model Extension: Rg, gate resistance model Cfr, fringing cap from MEOL Cgb complete Back-Gate network adding NWELL/PWELL-PSUB junctions [JC Barbé et al, RFIC2015]

15 f T and f max for front-gate -measurements vs simulations with Leti-UTSOI2 16 Maximum measured values for front-gate 28nm FDSOI transistors: - Max(f T ) = 384GHz - Max(f max ) = 392GHz

16 f T and f max for back-gate -measurements vs simulations with Leti-UTSOI2 17 Maximum measured values for back-gate 28nm FDSOI transistors: - Max(f T ) = 72GHz - Max(f max ) = 38GHz

17 RF MOS PCell general features Handle layers up to Metal1 only Consistent with parasitic elements included in the model Access to front gate As small as possible poly head(s) Poly head(s) can have 1 or 2 contact rows Front gate can be connected on both sides Flexible topology for Source/Drain accesses Inner Source/Drain can have 1 or 2 contact rows Variable number of contacts per row Variable distance of contacts to poly Access to back-gate (well strap) is always drawn Allow accurate modeling of back-gate impedance Need to keep layout flexible for well strap

18 RF MOS PCell-based layout examples

19 RF modeling of back-gate access ST I B ST I G S D BOX NWELL STI B ST I S G BOX D STI B PSUB STI STI B ST I G S D BOX PWELL STI B ST I STI NWELL NWELL TW Triple-WELL PSUB

20 Non Quasi-Static (NQS) modeling Can be achieved using MOS transistor channel segmentation MOS for external parasitic Front Gate resistance Voltage sources for DIBL Channel segmentation features Back Gate resistance 5 segments are enough to capture NQS frequency dependence up to 10x Ft Each segment consists of an intrinsic MOS transistor model instance Extrinsic parasitic elements are accounted for in a sixth transistor model instance

21 NQS modeling of MOS trans-conductance vs. frequency Quasi-Static RF model Non Quasi-Static RF model dots: measure lines: LETI-UTSOI2 NMOS, W = 1µm, L=1µm, V gs =0.8V

22 Analog/RF/mmW Design examples in FD-SOI - on the usage of body biasing From bloc level to system level and SoC

23 Body biasing techniques for analog/ms/rf designs 25 Take advantage of the unique very wide-band body biasing (BB) voltage range Propose unique techniques bringing uncontested chip energy saving and revisiting performances SoA Method 1: BB voltage variable over time and PVT Cancel system level PVT effects by continously tuning transistors respective V T Design examples: J. Lechevalier ISSCC2015, D. Danilovic RFIC2016, G. De Streel VLSI2016, R. Guillaume RFIC2017 Reconfigure circuit/bloc/system depending on application operation mode Design examples: A. Larie ISSCC2015 (bloc level), G. De Streel VLSI2016 (system level) Propose new energy efficient design techniques for tunable blocs via body tie Design examples: I. Sourikopoulos ESSCIRC2016 Method 2: fixed BB voltage Enable operation at ULV (0.5V) and in the same time increase circuit speed Design examples: L. Fanori RFIC2015, A. Lahiri ESSCIRC2016 Minimize switches R on value and excursion for energy efficient and high speed switched-capacitors circuits (e.g. ADC) Design examples: S. Le Tual ISSCC2014, A. Kumar ESSCIRC2016 Non-overlapping clock generation in massively digital RF Receivers, to increase system linearity Design example: R. Kasri CICC2017

24 Analog Filter Design Example 26 Filters with several 100 s MHz bandwidth - PVT + ageing affect system operation - Need to tune/trim independently several parameters impacting overall system: V DD V Filter Regulator drop (>20%) Tuning margin Global supply cut-off frequency, linearity, noise, all for an optimal power consumption Filter supply Regular CMOS Tuning/trimming solution: Voltage regulator impacting directly the signal path behavior FD-SOI revolutionary solution: individual transistors body biasing oxide-isolated from the signal path behavior

25 Typical example of Analog Filter 27 Inverter-based analog functions: attractive implementations: simple and compact scale nicely with technology nodes Here: analog low-pass Gm-C filter Typical implementation: Fixed capacitors Tune the filter cut-off frequency by tuning Gm Bulk specific solution: Tune local Vdd Local V DD FD-SOI specific solution: Tune all VBB s

26 gm Tuning Gm with V DD OK: gm variation; NOK: linearity 28 Local V DD Tune Gm value with local VDD Major issue: it changes also linearity and noise behavior V DD high nominal low 0 V input

27 gm gm FD-SOI: Tuning gm with Vbody OK: gm variation; OK: linearity 29 New tuning knob (and off the signal path): VBBP and VBBN Compensate V DD variations Tune gm back to nominal Ensure constant linearity operation V DD high nominal low 0 Without back-gate bias V input 0 With back-gate bias V input

28 Inverter-based Analog Filter in 28FDSOI 30 RF low-pass Gm-C filter using CMOS inverters Tuned by back-gate instead of supply (no signal path interference) enabled by FDSOI Supply regulator-free operation Energy efficient Low voltage operation (VDD = 0.7V) Competitive linearity Compared to similar circuit in 65nm bulk [2], at same noise level, get X2 linearity for /4 power level Compared to best-in-class filters [7], at same noise level and Fc, get competitive linearity for /14 power level [J. Lechevalier at al, ISSCC2015] [2] Houfaf, et al., ISSCC 2012 [5] Saari, et al., TCAS-I 2009 [6] Mobarak, et al., JSSC 2010 [7] Kwon, et al., TMTT 2009 Best in class in terms of the compromise noiselinearity-power Integrated in ST 28nm FD-SOI CMOS

29 A Low-Power Inductor-less RFFE with IIP2 Callibration for BTLE applications, coexistence with LTE band 7 31 [D. Danilovic et al., RFIC2016 and NEWCAS2015] Compact, energy efficient RF Front-End in 28FDSOI System level performance within BT specs with LTE coexistence (IIP2 spec >70dBm) Inductor-less Low Noise Transconductance Amplifier Common gate with cross-coupling caps Complementary NMOS/PMOS Noise Cancellation Differential IQ passive mixer with 25% duty cycle Tune switches mismatch through body biasing VDD LO1 IF_Ip FDSOI advantages: LNTA: higher intrinsic gain, less parasitics Huge IIP2 improvement through body-biasing Overall energy efficient design 2xLO Vin Divide by 2 and 25% Clock Generator LO1 LO2 LO3 LO4 LO1 LO2 LO3 LO4 LO2 Back Bias LO4 Vout_Q Vinp Iout Vinn RFp RFn LO3 LO1 LO2 I Channel IF_In IF_Qp VB tune1 VB VB tune2 LO1 LO3 Vout_I LO4 Q Channel Back Bias GND LO2 IF_Qn

30 IIP2 (dbm) IIP2 (dbm) A Low-Power Inductor-less RFFE with IIP2 Callibration for BTLE applications, coexistence with LTE band 7 - IIP2 measurement results Different Blocker Scenarios: f1 = f LO +fx, f2 = f LO +fx+4mhz fx = 40MHz: +20dB IIP2 improvement fx = 100MHz: +25dB IIP2 improvement fx = 200MHz: +31dB IIP2 improvement IIP2_200MHz IIP2_100MHz IIP2_40MHz LO3 LO1 IF_Ip I Channel VB tune1 VB Different Chips, IIP2 improvement with Body biasing: Chip1: +24dB IIP2 improvement Chip2: +30dB IIP2 improvement Chip3: +23dB IIP2 improvement RFp RFn LO1 LO2 IF_In IF_Qp VB tune LO4 Q Channel VB differential (V) LO2 V B = 1V V Bdiff = V Btune1 V Btune2 IF_Qn VB differential (V) [D. Danilovic et al., RFIC2016 and NEWCAS2015]

31 Average PAE (at 8-dB back-off) [%] PAE at 8-dB back-off [%] dc consumption [mw] Dissipated power [mw] GHz transceivers (RF TX part) 65nm PA 65nm Other TX blocks 90nm 65nm 40nm High dc consumption Low average PAE High PAPR 60GHz PA WiGiG with max. operation 8dB back-off high linearity with optimized power 34 0 JSSC 2011 ISSCC 2011 JSSC 2013 ISSCC 2014 ISSCC 2014 Output Average power at 8-dB power back-off Output power [dbm] 50% power in mmw TRx spent in PA Solve the general trade-off linearity and power consumption CMOS 40nm CMOS 65nm JSSC, 2013 JSSC, 2012 ISSCC, 2014 RFIC, 2014 RFIC, 2014 JSSC, 2010 MWCL, 2015 ESSCIRC, dB compression point [dbm]

32 Novel mmw Power Amplifier thanks to FD-SOI and wide-range body biasing 35 Classical Doherty Power Amplifier Revisit classical Doherty power amplifier architecture FD-SOI-specific Doherty Power Amplifier Class C V DD, RF Out+ RF Out-, V DD Class AB Class AB Class C V B1 V B2 V B1 Two different class power amplifier in parallel Ability of gradualy change the overall class of the PA (mix of class AB and class C) thanks to wide range FBB optimise in the same time power efficiency and linearity Remove signal path power splitter as in classical implementations reduced signal path losses RF In+, V G_DC V G_DC, RF In-

33 60GHz Configurable PA 36 This work [A. Larie et al., ISSCC2015] S. Kulkarni ISSCC 2014 D. Zhao JSSC 2013 D. Zhao JSSC 2012 E. Kaymaksut RFIC 2014 A. Siligaris JSSC 2010 Technology 28nm UTBB FD-SOI 40nm 40nm 40nm 40nm 65nm PD-SOI Operating mode High gain High linearity NA Low/High power NA NA NA Supply voltage [V] Freq. [GHz] Gain [db] / P SAT [dbm] / P 1dB [dbm] / PAE max [%] / PAE 1dB [%] / PAE 8dB_backoff [%] / P DC [mw] / 75 # P DC_8dB_backoff [mw] / 78 # xP 1dB /P DC / 32 # Active area [mm²] * ITRS FOM [W.GHz²] 161,671 1,988 1,198 6, / 2,832 13, ,038 Fully WiGiG compliant (linearity and frequency range) New PA architecture enabled by FDSOI: continuously reconfigurable power cells Continuous operation class tuning thanks to body bias with 2 extreme modes: High gain mode: Highest ITRS FOM 10X better than previous SoA High linearity mode: Break the linearity / consumption tradeoff ULV high efficiency operation (Vdd_min = 0.8V) ITRS FOM = P SAT.PAE max.gain.freq² * : with pads # : estimated Integrated in ST 28nm FD-SOI CMOS

34 mmw Design Example: Distributed Oscillator at 134 GHz [R. Guillaume at al, RFIC2017] 38 f osc = 1 Δφ f /π 2nl LC Phase 1MHz Oscillation frequency (Fosc) - The oscillation frequency depends on: - The electrical Tline parameters - The transistor inverting properties around Fosc (Fmax) - The highest Fosc topology proposed so far in a 28nm node

35 Distributed Oscillator: Correlation measurements vs simulation Measurement average Simulation : f osc = GHz Theory : f osc = 134.2GHz Phase noise optimization/tuning/trimming via body biasing Oscillation frequency measurements, histogram over 8 locations on a wafer: <0.1% variation simulation vs measurements Very small on wafer dispersion

36 mmw Distributed Oscillator in 28nm FD-SOI: comparison with the SoA 40 (*full transmitter / **Without pads / at optimum Phase Noise) FoM = m 20 log f 0 f m + 10 log P diss 1mW

37 A 6b 10GS/s High-Speed Time Interleaved-ADC 41 Lower Vth, less variability Better switch: R ON & linearity Faster logic Reduced S/D capacitances Increased comparator BW Reduced switch parasitics [S. Le Tual et al., ISSCC2014] Verma ISSCC 2013 Tabasy VLSI 2013 Kull VLSI 2013 This Work Technology 40nm CMOS 65nm CMOS 32nm SOI 28nm FD-SOI Architecture TI-FLASH TI-SAR TI-SAR TI-SAR Power Supply (V) / Sampling Rate (GS/s) Resolution (bits) Power Consumption (mw) Nyquist (db) Active Area (mm 2 ) Nyquist (fj/conv) Max Input Frequency (GHz) Gain/Skew Calibration Yes Yes Yes No Energy efficient operation Integrated in ST 28nm FD-SOI CMOS O : 28FD-SOI or 32nm SOI Courtesy, B. Murmann, Stanford Univ.

38 A Single Channel 12b 600Ms/s ADC with no calibration - architecture: 2x 2.5b pipeline stages followed by a 8b A-SAR, with no calibration loop 42 [Ashish Kumar et al., ESSCIRC2016] [ Chiang ] JSSC 2014 [ Boo ] ISSCC 2015 [ Brandolini ] ISSCC 2015 FBB (± 1.8V) Switch linearity improved by a factor of 40 Ron improved by a factor of 5 Smaller switches with smaller parasitic cap [ Mulder ] ISSCC 2015 This Work Technology 65nm 65nm 28nm 28nm 28nm FDSOI Power Supply [V] / Area [mm 2 ] * Resolution 10b 12b 10b 13b 12b Sampling rate 800 MS/s 250 MS/s 2.5*/5 GS/s 800MS/s 600MS/s SNDR@Nyq [db] Power [mw] ** 19.8 FOM W [fj/conv-step] ** 37.2 FOM S [db] ** Calibration yes no yes yes no FBB (± 1.8V) 2x logic speed Improved comparator delay Integrated in ST 28nm FD-SOI CMOS Improved linearity and speed of switched cap circuits Only single channel work in this region of the plot Courtesy, B. Murmann, Stanford Univ.

39 A Digital Sine-Weighted Switched-Gm mixer for Single-Clock Power- Scalable Massive Parallel Receivers in 28FDSOI DDFS-driven mixer-dac is suitable for parallel RXs: Only one frequency reference Harmonic Rejection Mixing Power consumption scales with number of channels Binary-weighted Switched-Gm + 2-path filter proposed: Low-voltage-technologies compatible mixer-dac Power efficient Tolerant to out-of-band blockers Original non overlapping clock generation using body bias. Fine linearity tuning using body bias Non overlapping clock generation using body bias 43 [R. Kasri et al., CICC 17]

40 Pixel Pitch-Matched Ultrasound Receiver in 28FDSOI Inverter-based amplifier in SC DSM First proof-of-concept pitch-matched fully-digital subarray beamformer IC for 3D ultrasound Highest per-channel SNR with ~7x area reduction FDSOI Technology Enabler: High integration density Immune to latch-up allow the use of slewing-based amplifier using minimum length cascaded inverters Low V th devices provide area-efficient low R on switches [M-C. Chen et al., ISSCC 17]

41 SleepTalker - 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC 45 IR-UWB BPSK and BPM RF transmitter operated at 0.55V IEEE a compliant GHz channels reconfiguration Configurable Data Rate: 0.11, 0.85, 1.7, 6.81, 27.24Mb/s RF SoC: digital and RF transmit path, frequency synthetizer, DC-DC (1.2V to 0.55V) and Body Bias Generator (up to +/-1.8V, for variable output voltage) SoC architecture innovation enabled by FDSOI: Extremelly low power PLL-free architecture with aggressive duty cycling, compensated by on chip adaptive FBB for Local Oscillator tuning and trimming upon the requested transmit frequency Digital Power Amplifier with programmable pulse shaping enabled by body biasing control, meeting FCC spectral regulation for all channels High speed ultra low voltage digital implementation enabled by FBB Record energy efficiency improving by 16 the State of the Art (Tx: 14pJ/bit, SoC: 24pJ/bit) [G. de Streel, D. Bol et al., VLSI2016 and JSSC2017]

42 Conclusion

43 Takeaways for Analog/RF/mixed-signal body biasing 48 Unprecedented very wide V T tuning range of ~250mV for FDSOI vs ~10mV for bulk New tuning knob with no parasitic effects on the signal path (control under the BOX) Enhanced switches performances for all type of mixed-signal circuits Efficient revisited tuning/trimming strategies: Process/Temperature compensation Circuit reconfiguration Flexible and energy saving SoC solutions Simpler circuits revisit State of the Art Efficient Flexible Simple

44 FD-SOI will Enable the Ultimate Integration for Tomorrow s Connected World 49 5G Ultra low voltage operations with high performance. Easy and efficient analog integration (ADC/DACs, RF, LDOs, ) FBB for dynamic power/ leakage/ frequency tuning Smart City Smart Industrial Smart Home Enterprise & Cloud Datacenter Core Network Backhaul Mobile Network Performant Ft / Fmax, Performant passive devices Improved noise, Lower parasitic capacitances Adapt power consumption to load Excellent reliability and soft-error performances Smart Car Healthcare Access Network Radio Access Network Performance and power efficiency The Internet of Things Network infrastructure

45 50

46 Bibliography - I O. Rozeau, M. A. Jaud, T. Poiroux and M. Benosman, "Surface potential based model of ultra-thin fully depleted SOI MOSFET for IC simulations," in IEEE International SOI Conference, T. Poiroux, O. Rozeau, S. Martinie, P. Scheer, S. Puget, M. A. Jaud, S. El Ghouli, J. C. Barbé, A. Juge and O. Faynot, "UTSOI2: a complete physical compact model for UTBB and independent double gate MOSFETs," in IEEE International Electron Device Meeting, T. Poiroux, O. Rozeau, S. Martinie, P. Scheer, M. A. Jaud, A. Juge and J. C. Barbé, "UTSOI2: A compact model for UTBB devices accounting for back interface inversion," in International MOS-AK Workshop, Washington, T. Poiroux, P. Scheer, O. Rozeau, B. De Salvo, A. Juge, J. C. Barbé and M. Vinet, "New version of Leti-UTSOI2 featuring further improved predictability, and a new stress model for FDSOI technology," in International MOS-AK Workshop, Grenoble, T. Poiroux, O. Rozeau, P. Scheer, S. Martinie, M. Jaud, M. Minondo, A. Juge, J. Barbé and M. Vinet, "Leti-UTSOI2.1: A compact model for UTBB-FDSOI technologies - Part I: Interface potentials analytical model," IEEE Transactions on Electron Devices, vol. 62, no. 9, pp , T. Poiroux, O. Rozeau, P. Scheer, S. Martinie, M. Jaud, M. Minondo, A. Juge, J. Barbé and M. Vinet, "Leti-UTSOI2.1: A compact model for UTBB-FDSOI technologies - Part II: DC and AC model description," IEEE Transactions on Electron Devices, vol. 62, no. 9, pp , T. Poiroux, O. Rozeau, S. Martinie, P. Scheer, M. Jaud, A. Juge, M. Vinet and J. C. Barbé, "Compact modeling for UTBB-FDSOI technologies: main challenges and possible solutions," (invited) in Workshop on Compact Modeling (WCM), Washington, J. C. Barbé, L. Lucci, A. Siligaris, P. Vincent and O. Faynot, "4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors," in IEEE Radio- Frequency Integrated Circuits Symposium (RFIC), S. El Ghouli, P. Scheer, M. Minondo, A. Juge, T. Poiroux, J.M. Sallese and C. Lallement, "Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model," in 23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), 2016.

47 Bibliography - II N. Planes, O.Weber, V. Barral, S. Haendler, D. Noblet, D. Croain,M. Bocat, P. Sassoulas, X. Federspiel, A. Cros, A. Bajolet, E. Richard, B. Dumont, P. Perreau, D. Petit, D. Golanski, C. Fenouillet-Beranger, N. Guillot, M. Rafik, V. Huard, S. Puget, X. Montagner, M.-A. Jaud, O.Rozeau, O. Saxod, F. Wacquant, F. Monsieur, D. Barge, L. Pinzelli, M. Mellier, F. Boeuf, F. Arnaud, and M. Haond, 28 nm FD-SOI technology platform for high-speed low-voltage digital applications, in Proc. Symp. VLSI Technology (VLSIT), 2012, pp F. Arnaud, N. Planes, O. Weber, V. Barral, S. Haendler, P. Flatresse, and F. Nyer, Switching energy efficiency optimization for advanced CPU thanks to UTBB technology, in IEEE Int. Electron Devices Meeting (IEDM) Dig., 2012, pp David Jacquet; Frédéric Hasbani; Philippe Flatresse; Robin Wilson; Franck Arnaud; Giorgio Cesana; Thierry Di Gilio; Christophe Lecocq; Tanmoy Roy; Amit Chhabra; Chiranjeev Grover; Olivier Minez; Jacky Uginet; Guy Durieu; Cyril Adobati; Davide Casalotto; Frederic Nyer; Patrick Menut; Andreia Cathelin; Indavong Vongsavady; Philippe Magarshack, A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization, IEEE Journal of Solid-State Circuits, Year: 2014, Volume: 49, Issue: 4 Raphaël Guillaume, François Rivet, Andreia Cathelin, Yann Deval, Energy Efficient Distributed-Oscillators at 134 and 202GHz with Phase-Noise Optimization through Body-Bias Control in 28nm CMOS FDSOI Technology, RFIC 2017 Ashish Kumar; Chandrajit Debnath; Pratap Narayan Singh; Vivek Bhatia; Shivani Chaudhary; Vigyan Jain; Stephane Le Tual; Rakesh Malik, A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Year: 2016, Pages: Joeri Lechevallier; Remko Struiksma; Hani Sherry; Andreia Cathelin; Eric Klumperink; Bram Nauta, A forward-body-bias tuned 450MHz Gm-C 3rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, Year: 2015, Pages: 1 3 Aurélien Larie; Eric Kerhervé; Baudouin Martineau; Lionel Vogt; Didier Belot, A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, Year: 2015, Pages: 1 3 Dajana Danilovic; Vladimir Milovanovic; Andreia Cathelin; Andrei Vladimirescu; Borivoje Nikolic, Low-power inductorless RF receiver front-end with IIP2 calibration through body bias control in 28nm UTBB FDSOI, 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Year: 2016, Pages: 87 90

48 Bibliography - III 53 Guerric de Streel; François Stas; Thibaut Gurné; François Durant; Charlotte Frenkel; Andreia Cathelin; David Bol, SleepTalker: A ULV a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pj/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping, IEEE Journal of Solid-State Circuits, Year: 2017, Volume: PP, Issue: 99, Pages: 1 15 Ilias Sourikopoulos; Antoine Frappé; Andreia Cathelin; Laurent Clavier; Andreas Kaiser, A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Year: 2016, Pages: Luca Fanori; Ahmed Mahmoud; Thomas Mattsson; Peter Caputa; Sami Rämö; Pietro Andreani, A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process, 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Year: 2015, Pages: Abhirup Lahiri; Nitin Gupta, A mm2 600µW 32kHz input 307MHz output PLL with 190psrms jitter in 28nm FD-SOI, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Year: 2016, Pages: Stéphane Le Tual; Pratap Narayan Singh; Christophe Curis; Pierre Dautriche, A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Year: 2014, Pages: Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtić; Ben Keller; Steven Bailey; Milovan Blagojević; Pi-Feng Chiu; Hanh- Phuc Le; Po-Hung Chen; Nicholas Sutardja; Rimas Avizienis; Andrew Waterman; Brian Richards; Philippe Flatresse; Elad Alon; Krste Asanović; Borivoje Nikolić, A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC DC Converters in 28 nm FDSOI, IEEE Journal of Solid-State Circuits, Year: 2016, Volume: 51, Issue: 4, Pages:

49 Bibliography - IV 54 Robin Wilson; Edith Beigne; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; Julien Le Coz; Ivan Miro Panades; Jean-Philippe Noel; Bertrand Pelloux-Prayer; Philippe Roche; Olivier Thomas; Y. Thonnart; David Turgis; Fabien Clermidy; Philippe Magarshack, «A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking», 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, Pages: Edith Beigné; Alexandre Valentian; Ivan Miro-Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; Julien Le Coz; Jean-Philippe Noel; Olivier Thomas; Yvain Thonnart, «A 460 MHz at 397 mv, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking», IEEE Journal of Solid-State Circuits, 2015, Volume: 50, Issue: 1, Pages: Reda Kasri, Eric Klumperink, Philippe Cathelin,Eric Tournier, Bram Nauta, «A Digital Sine-Weighted Switched-Gm mixer for Single-Clock Power-Scalable Parallel Receiver», CICC 2017, Austin, April 2017 Man-Chia Chen, Aldo Peña Perez, Sri-Rajasekhar Kothapalli, Philippe Cathelin, Andreia Cathelin, Sanjiv Sam Gambhir, Boris Murmann, «A Pixel-Pitch-Matched Ultrasound Receiver for 3D Photoacoustic Imaging with Integrated Delta- Sigma Beamformer in 28nm UTBB FDSOI», ISSCC 2017