Technology Advantages for Analog/RF & Mixed-Signal Designs

Transcription

1 Technology Advantages for Analog/RF & Mixed-Signal Designs Philippe Cathelin, Andreia Cathelin STMicroelectronics, Crolles, France October 5, 2016 CMP 28FDSOI Training

2 Agenda 2 In the context of IoT ST 28nm UTBB FD-SOI CMOS: Simpler Analog Integration Advantages for analog design Advantages for RF/mmW design Advantages for Mixed-Signal design SoC integration examples Conclusion and takeaways Nota: all measurement data from ST 28nm FD-SOI CMOS, unless otherwise specified

3 IoT Strategic Focus 3 The leading provider of products and solutions for the Internet of Things Smart Industry Smart City Smart Home Smart Things

4 IoT Devices Come in Many Form Factors 4

5 but Their Needs are the Same 5 Processing & Security Sensing & Actuating Connectivity Signal Conditioning & Protection Power & Energy Management Smart Things Smart Home Smart City Ultra-Low Power to High Performance Scalable Security solutions Full range of sensors and actuators 10 cm to 10 km Nano Amps to Kilo Amps Nano Watt to Mega Watt Smart Industry

6 but Their Needs are the Same 6 Processing & Security Connectivity Power & Energy Management Signal Conditioning & Protection Sensing & Actuating Smart Things Smart Home Smart City Smart Industry Ultra-Low Power to 10 cm Nano Watt to Mega Watt Nano Amps FD-SOI enabling Integration Path High Performance Scalable Security solutions to 10 km to Kilo Amps Full range of sensors and actuators

7 Factors of Merit 7 FBB Power and energy efficiency Total dielectric isolation No channel doping No pocket implant Analog performance for mixed signal and RF design Robustness for mission critical applications FD-SOI is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance

8 ST 28nm FD-SOI Transistor Flavors 8 Low VT (LVT) CMOS in FD-SOI; flipped-well Bulk type CMOS RBB FBB NLVT NRVT PLVT PRVT 0.2 Vth (V) FBB RBB Regular VT (RVT) CMOS in FD-SOI VB (V)

9 for Simpler Analog Integration 9 ST 28nm FD- SOI makes analog/rf/hs designer s life easier Improved Analog Performance Improved Noise Efficient Short Devices Very large V T tuning range High performance frequency behavior Speed increase in all analog blocks Higher gain for a given current density Lower gate and parasitic capacitance Lower noise Better matching for short devices and efficient design with L>L min Analog parameters wide range tuning via a new independent tuning knob (back-gate) f T / f max >300GHz for LVTNMOS and high performance passives enabling RF/mmW/HS integration with technology margin Higher bandwidth Lower power Smaller designs Improved design margins wrt PVT variations Novel flexible design architectures

10 Advantages in Analog Design 10 Efficient Short Devices Improved Analog Perf. Improved Noise DC gain-lin (Gm/Gds) 28FDSOI 28LP bulk Gm/Id (1/V) 28FDSOI 28LP bulk Input refered 1/f noise Density vs Id/w (nlvt w=1µm, l=0.12mm) Gate lenght (m) Gate lenght (m) 28FDSOI 28LP bulk Avt (mv.µm) Curves for W=1µm 28LP bulk 28FDSOI Higher Gm for a given current density Cgg (ff/µm) 28LP bulk 28FDSOI Current Density (µa/µm) Input refered 1/f noise Density vs Id/w (nlvt w=1µm, l=1µm) Gate lenght (m) Efficient use of short devices : High analogue Low L Low Vt mismatch (Avt ~ 2mV.µm) Performance example: A 1µm/100nm device has a DC gain of 80 & a σvt of only 6mV Lower gate capacitance Gate lenght (m) Higher achievable bandwidth or lower power for a given bandwidth Current Density (µa/µm) For NLVT NMOS (1µm/120nm), 1.5 db noise improvement in FDSOI Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, STMicroelectronics

11 Advantages in Analog Design-II 11 Very large V T tuning range by FBB ST 28nm LVT NMOS (typical) +3V FBB T [mv] V T Bulk FD-SOI P-Sub 0V VBBN Forward body bias [V] VBBP Flip-well devices: Large Forward Body Bias (FBB) range Negligible control current FD-SOI (flip-well flavor/lvt devices) -3V P-sub Use back-gate as «VT tuning knob»: Unprecendented ~250mV of tuning range for FD-SOI vs. ~ 10 s mv in any bulk Courtesy, A. Cathelin, STMicroelectronics

12 Body biasing techniques for analog/ms/rf designs 12 Take advantage of the unique very wide-band body biasing (BB) voltage range Propose unique techniques bringing uncontested chip energy saving and revisiting performances SoA Method 1: BB voltage variable over time and PVT Cancel system level PVT effects by continously tuning transistors respective V T Design examples: J. Lechevalier ISSCC2015, D. Danilovic RFIC2016, G. De Streel VLSI2016 Reconfigure circuit/bloc/system depending on application operation mode Design examples: A. Larie ISSCC2015 (bloc level), G. De Streel VLSI2016 (system level) Propose new energy efficient design techniques for tunable blocs via body tie Design examples: I. Sourikopoulos ESSCIRC2016 Method 2: fixed BB voltage Enable operation at ULV (0.5V) and in the same time increase circuit speed Design examples: L. Fanori RFIC2015, A. Lahiri ESSCIRC2016 Minimize switches R on value and excursion for energy efficient and high speed switched-capacitors circuits (e.g. ADC) Design examples: S. Le Tual ISSCC2014, A. Kumar ESSCIRC2016

13 On the usage of FBB for inverter-based Analog/RF 28nm UTBB FDSOI: example of a 450MHz Gm-C filter with IIP3> 1dBv over a 0.7-1V power supply [J. Lechevalier at al, ISSCC2015]

14 Filters with several 100 s MHz bandwidth - PVT + ageing affect system operation - Need to tune/trim independently several parameters impacting overall system: cut-off frequency, linearity, noise, all for an optimal power consumption Analog Filter Design Example V DD V Filter Regulator drop (>20%) Tuning margin Filter supply 14 Global supply Regular CMOS Tuning/trimming solution: Voltage regulator impacting directly the signal path behavior FD-SOI revolutionary solution: individual transistors body biasing oxide-isolated from the signal path behavior

15 Typical example of Analog Filter 15 Inverter-based analog functions: attractive implementations: simple and compact scale nicely with technology nodes Here: analog low-pass Gm-C filter Typical implementation: Fixed capacitors Tune the filter cut-off frequency by tuning Gm Bulk specific solution: Tune local Vdd Local V DD FD-SOI specific solution: Tune all VBB s

16 Inverter based transconductor 16

17 Inverter-based filters 17 Tuned by supply voltage V DD LDO Regulator Voltage headroom Power V Filter V Filter Regulator drop (>20%) Tuning margin Filter supply Global supply

18 Inverter-based filters 18 Tuned by supply voltage V DD LDO Regulator Voltage headroom Power V Filter V Filter Regulator drop (>20%) Tuning margin Filter supply Global supply Eliminate the regulator by using FD-SOI technology

19 Inverter as V-I converter 19 I out 0 V tn V tp V in VFilter β n =β p β n <β p

20 Differential 20 I out V id gm β n =β p β n <β p V DD -V tn +V tp 0 V id

21 Tuning Gm with V DD OK: gm variation; NOK: linearity 21 Local V DD Tune Gm value with local VDD Major issue: it changes also linearity and noise behavior V DD high nominal low gm 0 V input

22 Fixed supply operation, tune by Vbody 22 Eliminate LDO regulator V Filter = V DD V DD V filter = V DD V Filter Bulk FD-SOI

23 FD-SOI: Tuning gm with Vbody OK: gm variation; OK: linearity 23 New tuning knob (and off the signal path): VBBP and VBBN Compensate V DD variations Tune gm back to nominal Ensure constant linearity operation gm high nominal low V DD gm 0 Without back-gate bias V input 0 With back-gate bias V input

24 LC ladder prototype 3 rd order Butterworth low-pass Gm-C filter Impedance scaling Filter Implementation 24 Filter area: 0.04 mm 2 Gm s: ~0.01 mm 2 Capacitors: ~0.03 mm 2

25 Gm Implementation 25 28nm node technology margin L > L min improves r out L = 110nm for all transistors Better linearity & matching Only frequency tuning, no Q-tuning

26 Cut-off frequency tuning 26 For a fixed VDD operation (0.9V), get wide range Fc tuning by Vbody f C = 190 MHz f C =1.08 GHz V BBN = V BBP

27 Cut-off frequency tuning - II 27 For a wide range of VDD (0.7-1V), get wide range Fc tuning by Vbody 0.9V 1V 0.8V 0.7V

28 Linearity - I 28 For a desired value of Fc, get in-spec linearity VDD, by Vbody tuning Cut-off freque ency [MHz] V BBN = V BBP

29 Linearity - II 29 Multiple possibilities, get in-spec linearity VDD, by independent Vbody tuning 1V 0.9V 0.8V 0.7V

30 Example of filter performance at Fc=450MHz, at optimum IIP3, tuning by Vbody 30 For a wide VDD range, get constant system-level behavior with superb analog features (Fc, linearity, noise)

31 Inverter-based Analog Filter 31 RF low-pass Gm-C filter using CMOS inverters Tuned by back-gate instead of supply (no signal path interference) Supply regulator-free operation Energy efficient Low voltage operation (VDD = 0.7V) Competitive linearity Compared to similar circuit in 65nm bulk [2], at same noise level, get X2 linearity for /4 power level [J. Lechevalier at al, ISSCC2015] [2] Houfaf, et al., ISSCC 2012 [5] Saari, et al., TCAS-I 2009 [6] Mobarak, et al., JSSC 2010 [7] Kwon, et al., TMTT 2009 Compared to best-in-class filters [7], at same noise level and Fc, get competitive linearity for /14 power level Best in class in terms of the compromise noise-linearity-power Integrated in ST 28nm FD-SOI CMOS

32 Advantages in RF/mmW Design 32 Active devices high frequency performance Performant passive devices Nbt= 1 For ST 28nm FD-SOI LVTNFET: f T / f max >300GHz Nbt= 2 to 6 For RF operation frequency : Work with L = 100nm MAG = NFmin ~ 10GHz current density: 125 µa/µm For mmw operation frequency (intrinsic models): Lmin MAG = NFmin ~ 60GHz current density: 200 µa/µm 33% less power than in 28LP bulk Operation frequency range : 2 GHz - 50 GHz Inductance range: 0.1 nh - 28 nh Q factor range: Size: 60x60 µm² 600x600 µm² Courtesy, L. Vogt, F. Paillardet, C. Charbuillet, P. Scheer, C. Durand STMicroelectronics

33 A 60GHz 28nm UTBB FD-SOI Reconfigurable Power Amplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC [A. Larie et al., ISSCC2015]

34 dc consumption [mw] GHz transceivers (RF TX part) 65nm PA Other TX blocks 90nm 65nm 65nm 40nm Dissipated power [mw] High dc consumption Low average PAE High PAPR 60GHz PA WiGiG with max. operation 8dB back-off high linearity with optimized power % power in mmw TRx spent in PA Solve the general trade-off linearity and power consumption Output Average power at 8-dB power back-off PAE at 8-dB back-off [%] Output power [dbm] CMOS 40nm CMOS 65nm JSSC, 2013 JSSC, 2012 ISSCC, 2014 RFIC, 2014 RFIC, 2014 JSSC, 2010 MWCL, 2015 ESSCIRC, dB compression point [dbm]

35 Novel mmw Power Amplifier thanks to FD-SOI and wide-range body biasing 35 Classical Doherty Power Amplifier FD-SOI-specific Doherty Power Amplifier Revisit classical Doherty power amplifier architecture Two different class power amplifier in parallel Ability of gradualy change the overall class of the PA (mix of class AB and class C) thanks to wide range FBB optimise in the same time power efficiency and linearity Remove signal path power splitter as in classical implementations reduced signal path losses

36 Reconfigurable linearized power cell - I Drain Drain Antenna diode Source Neutralization transistor Source Power transistor Gate Gate Schematic Layout - Segmented-bias (class-ab / class-c) to improve linearity and dc consumption

37 Reconfigurable linearized power cell - II Drain Drain Antenna diode Source Neutralization transistor Source Power transistor Gate Gate Schematic Layout - Segmented-bias (class-ab / class-c) to improve linearity and dc consumption - Operating class controlled by back-gate voltages V B1 and V B2 No splitter needed as gates can be connected Highly efficient compact alternative to Doherty PA

38 Reconfigurable linearized power cell - III Drain Drain Antenna diode Source Neutralization transistor Source Power transistor Gate Gate Schematic Layout - Segmented-bias (class-ab / class-c) to improve linearity and dc consumption - Operating class controlled by back-gate voltages V B1 and V B2 No splitter needed as gates can be connected Highly efficient compact alternative to Doherty PA - Capacitive neutralization with MOS device to track C gd Better immunity to process and bias variations

39 280µm RFo ut PA topology 580µm RF in Area CORE : 0.16mm²

40 Back-end implementation example 10 ML stack Strict density rules Less than 1dB IL TRF1 Drain Antenna diode Drain Source Neutralization transistor Source Power transistor Gate Gate

41 Small-signal measured results PA gain and linearity modes configured by body bias only, fixed VDD S-parameters results at VDD=1.0V Two highlighted modes : high gain & high linearity (intermediate modes possible) > 8 GHz bandwidth Unconditionally stable 40 S 21 [db] V B1 = V B2 = 2V B1 B2 V B1 = 0V, V B2 = 0.8V High linearity mode -10 High gain mode Freq [GHz]

42 40 Large-signal measured linearity results The power gain and linearity can be continuously tuned thanks to the body bias. When the high linearity mode is reached, the power gain is totally flat which boosts the linearity. 40 Gain [db] High gain mode High linearity mode Continuous tuning PAE [%] Output power 60GHz Gain [db] P 1dB [dbm] PAE 1dB [%] P DC [mw] PAE 8dB_backoff [%] P diss@8db_backoff [mw] 100xP 1dB /P DC High gain mode High linearity mode

43 This work Comparison with state of the art Performant gain, P SAT, linearity and efficiency thanks to FD-SOI technology and low-loss power combiner. Improves ITRS FOM by x10. S. Kulkarni ISSCC 2014 D. Zhao JSSC 2013 D. Zhao JSSC 2012 E. Kaymaksut RFIC 2014 A. Siligaris JSSC 2010 Technology 28nm UTBB FD-SOI 40nm 40nm 40nm 40nm 65nm PD-SOI Operating mode High gain High linearity NA Low/High power NA NA NA Supply voltage [V] Freq. [GHz] Gain [db] / P SAT [dbm] / P 1dB [dbm] / PAE max [%] / PAE 1dB [%] / PAE 8dB_backoff [%] / P DC [mw] / 75 # P DC_8dB_backoff [mw] / 78 # xP 1dB /P DC / 32 # Active area [mm²] * ITRS FOM [W.GHz²] 161,671 1,988 1,198 6, / 2,832 13, ,038 ITRS FOM = P SAT.PAE max.gain.freq² * : with pads # : estimated

44 Comparison with state of the art The high linearity mode reduces the dissipated energy at 8dB back-off with no compromise in linearity. This work S. Kulkarni ISSCC 2014 D. Zhao JSSC 2013 D. Zhao JSSC 2012 E. Kaymaksut RFIC 2014 A. Siligaris JSSC 2010 Technology 28nm UTBB FD-SOI 40nm 40nm 40nm 40nm 65nm PD-SOI Operating mode High gain High linearity NA Low/High power NA NA NA Supply voltage [V] Freq. [GHz] Gain [db] / P SAT [dbm] / P 1dB [dbm] / PAE max [%] / PAE 1dB [%] / PAE 8dB_backoff [%] / P DC [mw] / 75 # P DC_8dB_backoff [mw] / 78 # xP 1dB /P DC / 32 # Active area [mm²] * ITRS FOM [W.GHz²] 161,671 1,988 1,198 6, / 2,832 13, ,038 ITRS FOM = P SAT.PAE max.gain.freq² * : with pads # : estimated

45 Comparison with state of the art FD-SOI enables low supply low power operation still with high performance results. This work S. Kulkarni ISSCC 2014 D. Zhao JSSC 2013 D. Zhao JSSC 2012 E. Kaymaksut RFIC 2014 A. Siligaris JSSC 2010 Technology 28nm UTBB FD-SOI 40nm 40nm 40nm 40nm 65nm PD-SOI Operating mode High gain High linearity NA Low/High power NA NA NA Supply voltage [V] Freq. [GHz] Gain [db] / P SAT [dbm] / P 1dB [dbm] / PAE max [%] / PAE 1dB [%] / PAE 8dB_backoff [%] / P DC [mw] / 75 # P DC_8dB_backoff [mw] / 78 # xP 1dB /P DC / 32 # Active area [mm²] * ITRS FOM [W.GHz²] 161,671 1,988 1,198 6, / 2,832 13, ,038 ITRS FOM = P SAT.PAE max.gain.freq² * : with pads # : estimated

46 Comparison with state of the art system-level performance 8dB back-off 8dB back-off Output power (P SAT ) Low dc consumption Output power (P SAT ) Low dc consumption Linearity (P 1dB ) Max efficiency Previous references Zhao, JSSC 2013 Siligaris, JSSC 2010 Kulkarni, ISSCC 2014 Kaymaksut, RFIC 2014 Linearity (P 1dB ) Max efficiency This work (high linearity mode) Best linearity/consumption tradeoff!

47 This work S. Kulkarni ISSCC 2014 D. Zhao JSSC 2013 D. Zhao JSSC GHz Configurable PA 47 E. Kaymaksut RFIC 2014 A. Siligaris JSSC 2010 Technology 28nm UTBB FD-SOI 40nm 40nm 40nm 40nm 65nm PD-SOI Operating mode High gain High linearity NA Low/High power NA NA NA Supply voltage [V] Freq. [GHz] modes: Gain [db] / P SAT [dbm] / P 1dB [dbm] / PAE max [%] / PAE 1dB [%] / PAE 8dB_backoff [%] / P DC [mw] / 75 # P DC_8dB_backoff [mw] / 78 # xP 1dB/P DC / 32 # Active area [mm²] * ITRS FOM [W.GHz²] 161,671 1,988 1,198 6, / 2,832 13, ,038 ITRS FOM = P SAT.PAE max.gain.freq² * : with pads # : estimated [A. Larie et al., ISSCC2015] Fully WiGiG compliant (linearity and frequency range) New PA architecture: continuously reconfigurable power cells Continuous operation class tuning thanks to body bias with 2 extreme modes: High gain mode: Highest ITRS FOM 10X better than previous SoA High linearity mode: Break the linearity / consumption tradeoff ULV high efficiency operation (Vdd_min = 0.8V) Integrated in ST 28nm FD-SOI CMOS

48 Advantages in MS Design 48 Variability Switch performance Lower capacitance Vth (mv) 28lp bulk 28FDSOI Slow Typ Fast Slow Typ Fast Tighter process corners and less random mismatch than competing processes Benefits: Gate lenght (m) Simpler design process, shorter design cycle Improved yield or improved performance at given yield Improved gate control allows smaller VTH Backgate bias allows for VTH reduction by tuning Results is an unprecedented quality of analog switches Compounding benefits: smaller R -> smaller switch -> compact layout -> lower parastics -> even smaller switch Key for high performance data converters and other Switched-Cap. Circuits Lower juction capacitance makes a substantial difference in high-speed circuits Drastic reduction of self-loading in gain stages Drastic reduction of switch selfloading Two-fold benefit: Leads to incremental improvements Allows the designer to use circuit architectures that would be infeasible/inefficient in bulk technologies Courtesy, S. Le Tual, STMicroelectronics; B. Murmann, Stanford Univ.

49 High-Speed Time Interleaved-ADC example 49 Lower Vth, less variability Better switch: R ON & linearity Faster logic Reduced S/D capacitances Increased comparator BW Reduced switch parasitics [S. Le Tual et al., ISSCC2014] Verma ISSCC 2013 Tabasy VLSI 2013 Kull VLSI 2013 This Work Technology 40nm CMOS 65nm CMOS 32nm SOI 28nm FD-SOI Architecture TI-FLASH TI-SAR TI-SAR TI-SAR Power Supply (V) / Sampling Rate (GS/s) Resolution (bits) Power Consumption (mw) Nyquist (db) Active Area (mm 2 ) Nyquist (fj/conv) Max Input Frequency (GHz) Gain/Skew Calibration Yes Yes Yes No Energy efficient operation Integrated in ST 28nm FD-SOI CMOS O : 28FD-SOI or 32nm SOI Courtesy, B. Murmann, Stanford Univ.

50 SleepTalker - 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC [G. de Streel, D. Bol et al., VLSI2016] IR-UWB BPSK and BPM RF transmitter operated at 0.55V IEEE a compliant GHz channels reconfiguration Configurable Data Rate: 0.11, 0.85, 1.7, 6.81, 27.24Mb/s RF SoC: digital and RF transmit path, frequency synthetizer, DC-DC (1.2V to 0.55V) and Body Bias Generator (up to +/-1.8V, for variable output voltage) SoC architecture innovation: Extremelly low power PLL-free architecture with aggressive duty cycling, compensated by on chip adaptive FBB for Local Oscillator tuning and trimming upon the requested transmit frequency Digital Power Amplifier with programmable pulse shaping enabled by body biasing control, meeting FCC spectral regulation for all channels High speed ultra low voltage digital implementation enabled by FBB Record energy efficiency improving by 16 the State of the Art (Tx: 14pJ/bit, SoC: 24pJ/bit) 50

51 Ultra Low Power in IoT technology scaling 51 SoC Architecture 34 mw* Power Supply Loss SoC Power Consumption RF Analytics RF CPU & Memories Power Management Analytics CPU & Memories Other Previous Generation (40LP) <10 mw* X3 to X6 Power Consumption Improvement with FD-SOI See also paper and demo 26.5, ISSCC 2016, K. Yamamoto et al. A 0.7V 1.5-to-2.3mW GNSS Receiver with 2.5-to-3.8dB NF in 28nm FD-SOI FD-SOI 28nm <5 mw** FD-SOI 28nm optimized design * Measured on Silicon / Product Simulation ** Projection

52 Takeaways for Analog/RF/mixed-signal 52 ST 28nm FD-SOI CMOS arguments: For Analog/RF design: FBB as VT tuning knob ultra large tuning range for VT Very good analog performance lower power consumption and operate at L>Lmin for design margin For RF/mmW design, operate at Lmin and add: Efficient Flexible Simple Deep submicron technology features: Front-end: performant f T, f max Back-end + FD-SOI features: performant passive devices For mixed-signal/high-speed design: Improved variability Switch performance Reduced parasitic capacitance

53 Take-aways charts per field

54 Analog/RF design in FD-SOI 54 FD-SOI arguments: FBB as VT tuning knob ultra large tuning range for VT Very good analog performance lower power consumption and operate at L>Lmin for design margin Consequences on analog/rf design: Operate amplifiers at constant Gm Employ new tuning strategies Competitive noise and linearity behavior Obtain strong design independence with respect to PVT variations New robust design oportunities

55 RF/mmW design in FD-SOI 55 FD-SOI arguments: FBB as VT tuning knob ultra large tuning range for VT Very good analog performance lower power consumption Deep submicron technology: Front-end: performant f T, f max Back-end + FD-SOI features: performant passive devices Consequences on RF/mmW design: New family of reconfigurable topologies; new design architectures Power efficient solutions State of the art implementations with concomitent optimisation for each system-level parameter New robust design oportunities

56 FD-SOI arguments: Improved variability Switch performance Reduced parasitic capacitance Mixed-signal / High-speed design in FD-SOI 56 Consequences on MS design: State of the art HS Data Converters Drastic improvement of the Nyquist FOM (FOM=P/(f s *2 ENOB ) ) New robust design oportunities and new design architectures enabled

57 Thank You