Performances of recent outstanding 28FDSOI circuits and systems taped out through the CMP services

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Cathelin, fellow STMicroelectronics, Crolles andreia.

1 Performances of recent outstanding 28FDSOI circuits and systems taped out through the CMP services Andreia Cathelin, fellow STMicroelectronics, Crolles CMP, Annual Users Meeting Paris, January 25th, 2018

2 Fully depleted Silicon-on-Insulator (FD-SOI) 2 High k / metal gate FBB 0 1.1V Power and energy efficiency Elevated SD Total dielectric isolation Analog performance for mixed signal and RF design No channel doping Thin silicon film No pocket implant Robustness for mission critical applications Thin buried oxide <100> substrate FD-SOI is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance

3 Addressing Power Sensitive Markets 3 FinFet High-end Servers Consumer Multimedia Laptops Networking Infrastructure Internet of Things, Wearables Tablet PC Smartphone Automotive Ultimate Digital Density Ultimate Digital / Analog & Mixed-Signal / RF Integration

ST 28nm FD-SOI Transistor Flavors Low VT (LVT) CMOS in FD-SOI; flipped-well VBBN D NMOS G BOX N Well PMOS S P Sub D PMOS G BOX NMOS S P Well VBBP LVT NMOS LVT PMOS Nominal VBB GND GND Biasing mode 3

4 ST 28nm FD-SOI Transistor Flavors Low VT (LVT) CMOS in FD-SOI; flipped-well VBBN D NMOS G BOX N Well PMOS S P Sub D PMOS G BOX NMOS S P Well VBBP LVT NMOS LVT PMOS Nominal VBB GND GND Biasing mode FBB FBB 3 VBBN Bulk type CMOS 4 VBBP D G BOX N Well S P Sub D G S BOX P Well VBBN RVT PMOS RVT NMOS VDD GND RBB RBB 3 3 VBBP+0.3 Vth (V) RBB FBB FBB RBB NLVT NRVT PLVT PRVT Regular VT (RVT) CMOS in FD-SOI VB (V)

5 for Simpler Analog Integration ST 28nm FD- SOI makes analog/rf/hs designer s life easier 5 Improved Analog Performance Improved Noise Efficient Short Devices Very large V T tuning range High performance frequency behavior Speed increase in all analog blocks Higher gain for a given current density Lower gate and parasitic capacitance Lower noise variability Better matching for short devices and efficient design with L>L min Analog parameters wide range tuning via a new independent tuning knob (back-gate) f T / f max >300GHz for LVTNMOS and high performance passives enabling RF/mmW/HS integration with technology margin Higher bandwidth Lower power Smaller designs Improved design margins wrt PVT variations Novel flexible design architectures

6 Advantages in Analog Design 6 Efficient Short Devices Improved Analog Perf. Improved Noise DC gain-lin (Gm/Gds) 28FDSOI 28LP bulk Gm/Id (1/V) 28FDSOI 28LP bulk Input ref. voltage For NLVT W=1µm/L=1µm 28LP bulk Gate lenght (m) Gate lenght (m) 28FDSOI Avt (mv.µm) Curves for W=1µm 28LP bulk 28FDSOI Gate lenght (m) Efficient use of short devices : High analogue Low L Low Vt mismatch (Avt ~ 2mV.µm) Performance example: A 1µm/100nm device has a DC gain of 80 & a Vt of only 6mV Higher Gm for a given current density Cgg (ff/µm) 28LP bulk 28FDSOI Lower gate capacitance Gate lenght (m) Higher achievable bandwidth or lower power for a given bandwidth Input ref. voltage For NLVT W=1µm/L=120nm 28FDSOI 28LP bulk For NLVT MOS 1µA drain current, get 1.5dB lower 1/f noise in FDSOI Idrain/W (µa/µm) Idrain/W (µa/µm)

LVT NMOS (typical) +3V FBB V T [mv] Bulk

7 Advantages in Analog Design-II 7 Very large V T tuning range by FBB ST 28nm LVT NMOS (typical) +3V FBB V T [mv] Bulk FD-SOI P-Sub 0V VBBN Forward body bias [V] VBBP Flip-well devices: Large Forward Body Bias (FBB) range Negligible control current FD-SOI (flip-well flavor/lvt devices) -3V P-sub Use back-gate as «VT tuning knob»: Unprecendented ~250mV of tuning range for FD-SOI vs. ~ 10 s mv in any bulk

Advantages in RF/mmW Design 8 Active devices high frequency performance Performant passive devices Few passive devices examples: Inductor L=0.

~ 0.5dB @ 10GHz Work @ current density: 125 µa/µm For mmw operation frequency (intrinsic models): Work @ Lmin MAG = 12dB @60GHz NFmin ~ 1.

8 Advantages in RF/mmW Design 8 Active devices high frequency performance Performant passive devices Few passive devices examples: Inductor L=0.5nH 8ML For ST 28nm FD-SOI LVTNFET: f T / f max >300GHz For RF operation frequency : Work with L = 100nm MAG = NFmin ~ 10GHz current density: 125 µa/µm For mmw operation frequency (intrinsic models): Lmin MAG = NFmin ~ 60GHz current density: 200 µa/µm 33% less power than in 28LP bulk Varactor C=50fF Tline: Zc=50 Ohm, 8ML

Advantages in Mixed Signal Design 9 Variability Switch performance Lower capacitance Vth (mv) 28lp bulk 28FDSOI Slow Typ Fast Slow Typ Fast Gate lenght (m) Tighter process corners and less random

allows for VTH reduction by tuning Results is an unprecedented quality of analog switches Compounding benefits: smaller R -> smaller switch -> compact layout -> lower parastics -> even smaller switch

9 Advantages in Mixed Signal Design 9 Variability Switch performance Lower capacitance Vth (mv) 28lp bulk 28FDSOI Slow Typ Fast Slow Typ Fast Gate lenght (m) Tighter process corners and less random mismatch than competing processes Benefits: Simpler design process, shorter design cycle Improved yield or improved performance at given yield Improved gate control allows smaller VTH Backgate bias allows for VTH reduction by tuning Results is an unprecedented quality of analog switches Compounding benefits: smaller R -> smaller switch -> compact layout -> lower parastics -> even smaller switch Key for high performance data converters and other Switched-Cap. Circuits Lower junction capacitance makes a substantial difference in high-speed circuits Drastic reduction of self-loading in gain stages Drastic reduction of switch selfloading Two-fold benefit: Leads to incremental improvements Allows the designer to use circuit architectures that would be infeasible/inefficient in bulk technologies

The FBB Advantage for Digital Design 10 A very reasonable effort for extremely worthwhile benefits Forward Body Biasing: An extremely powerful and flexible concept in FD-SOI 0 1.

10 The FBB Advantage for Digital Design 10 A very reasonable effort for extremely worthwhile benefits Forward Body Biasing: An extremely powerful and flexible concept in FD-SOI 0 1.1V Performance boost Reduce power consumption at a given performance requirement Process compensation reducing the margins to be taken at design Comparatively easy to implement If you ve ever done DVFS you ll have no difficulty with Body Biasing Seamless inclusion in the EDA flow

11 Boost performances Body Bias Advantages Enable area reduction 11 Improve power efficiency Reduce process dispersion Enable leakage reduction Allow compensation techniques

12 Process Compensation Through FBB Leakage 1.0V/125C (mw) 10 1 Speed/Leak Vt distribution across process corners SS +10nm +16nm TT +4nm FF Lmin SS TT FF Compensated design Leakage 1.0V/125C (mw) Compensated Worst Case Speed/Leak Vt distribution WC +17% +10nm +16nm Lmin +4nm SS FBB 500mV TT FBB 250mV FF 0FBB WC 0,1 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 0.8V/WC_temp (GHz) 1 0,9 1 1,1 1,2 1,3 1,4 1,5 1,6 1,7 0.8V/WC_temp (GHz) Process compensation through FBB allows Masking SS-FF process spread Recovering +17% speed in 28nm FD-SOI, at no dynamic power expense

13 Design examples in 28nm FD-SOI - from building blocs to SoC s

data rate Total delay >10ns Granular delay < 500ps A Digital Delay Line with Coarse/Fine tuning through gate/body biaising in 28FDSOI 14 FDSOI specific unity delay

14 [I. Sourikopoulos et al., ESSCIRC2016] Novel low power design architectures for 60GHz receivers enabled by FDSOI: DFE with un-clocked delay feedback, search minimum delay spread at 2GS/s data rate Total delay >10ns Granular delay < 500ps A Digital Delay Line with Coarse/Fine tuning through gate/body biaising in 28FDSOI 14 FDSOI specific unity delay cell (thyristor revisited): Body bias control for rising/falling edge delay fine tuning Gate control for coarse delay tuning Complementary input scheme for reduced power consumption State of the art results: ultra wide range linear control, fs/mv sensitivity and energy efficiency Gate control Body control

202GHz 15 The oscillation frequency depends

transistor inverting properties around Fosc

15 [R. Guillaume at al, RFIC2017] 28FD-SOI Distributed Oscillator at 134 GHz and 202GHz 15 The oscillation frequency depends on: The electrical Tline parameters The transistor inverting properties around Fosc (Fmax) The highest Fosc topology proposed so far in a 28nm node Phase noise optimization through body bias tuning Oscillation frequency measurements, histogram over 8 locations on a wafer: <0.1% variation simulation vs measurements Very small on wafer dispersion Oscillation frequency (Fosc) Measurement average Simulation : = GHz Theory : = 134.2GHz Top View Gate Drain Cross Section Source U -20dB/dec Drain Source Gate H21 mmw transistor integration example and freq. parameters

A 128 kb Single-Bitline 8.4 fj/bit 90MHz at 0.

architecture with new: single clock cycle and low area booster,

efficiency achieved by keeping the storage-elements at ULV, whereas

the art performance: 90MHz read speed at 300mV, dissipating 8.

16 A 128 kb Single-Bitline 8.4 fj/bit 90MHz at 0.3V 7T Sense-Amplifier-less SRAM in 28nm FD-SOI 16 7T SRAM architecture with new: single clock cycle and low area booster, decoding scheme and read architecture (no senseamplifier) Energy efficiency achieved by keeping the storage-elements at ULV, whereas critical nodes are boosted Intensive body biasing design State of the art performance: 90MHz read speed at 300mV, dissipating 8.4 fj/bit-access the minimum operating voltage is 240mV the retention voltage is 200mV [B. Mohammadi et al., ESSCIRC2016]

Pixel Pitch-Matched Ultrasound Receiver in

proof-of-concept pitch-matched fully-digital

Highest per-channel SNR with ~7x area reduction

density Immune to latch-up allow the use of

cascaded inverters Low V th devices provide

17 Pixel Pitch-Matched Ultrasound Receiver in 28FDSOI Inverter-based amplifier in SC M First proof-of-concept pitch-matched fully-digital subarray beamformer IC for 3D ultrasound Highest per-channel SNR with ~7x area reduction FDSOI Technology Enabler: High integration density Immune to latch-up allow the use of slewing-based amplifier using minimum length cascaded inverters Low V th devices provide area-efficient low R on switches [M-C. Chen et al., ISSCC2017 and JSSC Dec2017]

SleepTalker - 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC 18 IR-UWB BPSK and BPM

5GHz channels reconfiguration Configurable Data Rate: 0.11, 0.85, 1.7, 6.81, 27.

55V) and Body Bias Generator (up to +/-1.

power PLL-free architecture with aggressive duty cycling, compensated by on chip adaptive FBB for

with programmable pulse shaping enabled by body biasing control, meeting FCC spectral regulation

18 SleepTalker - 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC 18 IR-UWB BPSK and BPM RF transmitter operated at 0.55V IEEE a compliant GHz channels reconfiguration Configurable Data Rate: 0.11, 0.85, 1.7, 6.81, 27.24Mb/s RF SoC: digital and RF transmit path, frequency synthetizer, DC-DC (1.2V to 0.55V) and Body Bias Generator (up to +/-1.8V, for variable output voltage) SoC architecture innovation enabled by FDSOI: Extremelly low power PLL-free architecture with aggressive duty cycling, compensated by on chip adaptive FBB for Local Oscillator tuning and trimming upon the requested transmit frequency Digital Power Amplifier with programmable pulse shaping enabled by body biasing control, meeting FCC spectral regulation for all channels High speed ultra low voltage digital implementation enabled by FBB Record energy efficiency improving by 16 the State of the Art (Tx: 14pJ/bit, SoC: 24pJ/bit) [G. de Streel, D. Bol et al., VLSI2016 and JSSC2017]

A 128x8 Massive MIMO Precoder-Detector in 28FDSOI Flexible solution wrt to classical

Hardware reuse, clockgating, body biasing Uses FBB and RBB for performance-power

reported energy efficiency @lowest reported area cost Uplink detector shows the

19 A 128x8 Massive MIMO Precoder-Detector in 28FDSOI Flexible solution wrt to classical 4x4 MIMO implementations, improves by 12dB array and 2X spatial multiplexing gains Hardware reuse, clockgating, body biasing Uses FBB and RBB for performance-power tradeoff and fine tuning of PVT The donwlink pre-coder QRD unit has the highest reported energy reported area cost Uplink detector shows the highest reported energy efficiency and area efficiency detection 19 [H. Prabhu et al., ISSCC2017]

20 ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy- Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI Energy efficient FDSOI-enabled processor for deep neural network inference Local processing in connected objects Complete processor with state-of-the-art energy efficiency Up to 10TOPs/Watt Approximate computing techniques exploiting body biasing Scaling 2-16bit accuracy, for >10x efficiency improvement with different bias settings for each accuracy level 18% energy efficiency gains due to body bias [B. Moons et al., ISSCC2017] * + o 1x16b 2x8b 4x4b 30-60% Sparse 4x3-4b Eff. [TOPS/W]Voltage [V] BB nom 0.61V 8.2 TOPS/W8.2 TOPS/W Throughput [GOPS] BB opt 0.63V 10 TOPS/W Throughput [GOPS]

Fine-Grained AVS in 28nm FDSOI Processor SoC Energy-efficient FDSOI-enabled processor SoC featuring: Intensive deployment of body biasing

8 DP GFLOPS/W with integrated regulators Integrated power management Low-overhead power estimation Programmable PMU Sub-µs adaptive voltage

, ESSCIRC2016 and JSSC2017] SC-DCDC Unit Cells Rocket Processor and Vector Accelerator Power Measurement Counters Adaptive Clock Generator

4 mm 2 ) DCDC toggle Back-Bias Generator NWELL PWELL 48 switched-capacitor DC-DC unit cells FSM.

07 mm 2 ) Rocket Core Branch Prediction Scalar RF int Set body bias Set DC-DC V out 16KB Scalar Inst.

.. (16KB Vector RF uses eight custom 8T SRAM macros)... int int int int int Crossbar Functional units (64-bit Int. Mul.

21 Fine-Grained AVS in 28nm FDSOI Processor SoC Energy-efficient FDSOI-enabled processor SoC featuring: Intensive deployment of body biasing techniques Integrated voltage regulation 82-89% system efficiency with adaptive clocking Fully-featured processor (RISC-V Rocket Processor) 41.8 DP GFLOPS/W with integrated regulators Integrated power management Low-overhead power estimation Programmable PMU Sub-µs adaptive voltage scaling (AVS) Up to 40% energy savings Compact implementation: Core area: 1.07mm² 568k Std Cells Boots Linux [B. Keller et al., ESSCIRC2016 and JSSC2017] SC-DCDC Unit Cells Rocket Processor and Vector Accelerator Power Measurement Counters Adaptive Clock Generator SC-DCDC Unit Cells SC-DCDC Control PMU To scope 1.8V 1.0V To scope 1.0V VOLTAGE AND CLOCK GENERATION (0.4 mm 2 ) DCDC toggle Back-Bias Generator NWELL PWELL 48 switched-capacitor DC-DC unit cells FSM... + DC-DC controller V out V ref POWER MANAGEMENT (0.1 mm 2 ) Toggle Counter Clock Counter CORE (1.07 mm 2 ) Rocket Core Branch Prediction Scalar RF int Set body bias Set DC-DC V out 16KB Scalar Inst. Cache (Custom 8T SRAM Macros) Z-scale PMU 8KB Scratchpad Vector Accelerator Vector Issue Unit... (16KB Vector RF uses eight custom 8T SRAM macros)... int int int int int Crossbar Functional units (64-bit Int. Mul., SP/DP FMA) 32KB Shared Data Cache (Custom 8T SRAM Macros) Vector Memory Unit 8KB Vector Inst. Cache (Custom 8T SRAM Macros) core clk Arbiter Async. FIFO/Level shifters Adaptive clock between domains generator Digital IO pads to wire-bonded chip-on-board UNCORE To/from off-chip FPGA FSB and DRAM FPU SRAM BIST INTEGRATED MEASUREMENT Programmable current mirror load I V out waveform load reconstruction 21 I ref

22 Conclusion

Takeaways for Analog/RF/mixed-signal body biasing 23 Unprecedented very wide V T tuning range of ~250mV for FDSOI vs ~10mV for bulk New tuning knob with no parasitic effects on the signal path

23 Takeaways for Analog/RF/mixed-signal body biasing 23 Unprecedented very wide V T tuning range of ~250mV for FDSOI vs ~10mV for bulk New tuning knob with no parasitic effects on the signal path (control under the BOX) Enhanced switches performances for all type of mixed-signal circuits Efficient revisited tuning/trimming strategies: Process/Temperature compensation Circuit reconfiguration Flexible and energy saving SoC solutions Simpler circuits revisit State of the Art Efficient Flexible Simple

Cloud Datacenter Core Network Backhaul Mobile Network Performant Ft / Fmax, Performant passive devices Improved noise, Lower parasitic capacitances Adapt power

24 FD-SOI will Enable the Ultimate Integration 5G for Tomorrow s Connected World 24 Ultra low voltage operations with high performance. Easy and efficient analog integration (ADC/DACs, RF, LDOs, ) FBB for dynamic power/ leakage/ frequency tuning Smart City Smart Industrial Smart Home Enterprise & Cloud Datacenter Core Network Backhaul Mobile Network Performant Ft / Fmax, Performant passive devices Improved noise, Lower parasitic capacitances Adapt power consumption to load Excellent reliability and soft-error performances Smart Car Healthcare Access Network Radio Access Network Performance and power efficiency The Internet of Things Network infrastructure

25 . and in BiCMOS55

B55 Design of Low-Power Active Tags for Operation with 77-81 GHz FMCW Radar [M.S.

450fF 450fF 450fF 70fF TL 300pH:100pH 20fF OUT Activate 450fF 450fF 450fF 270fF 270fF 0.

5mA 30pH : 30pH 100fF 1.5mA 100fF 1.5mA IN 100fF 320pH 50µA 70pH : 250pH 25fF V bias 2.

5mA 450fF G C V det G C2 450fF 2kΩ 450fF 2kΩ 450fF 2kΩ V bias V bias V bias 640fF IN

26 B55 Design of Low-Power Active Tags for Operation with GHz FMCW Radar [M.S. Dadash et al., IMS2017 and MTT2017] 2.5 V 2.5 V V mod OUT POUT N 2.5 V 2.5 V V mod G C1 130pH 450fF 130pH 450fF 500Ω Modulator VGA 220pH 220pH RF out V DET 450fF 450fF 450fF 70fF TL 300pH:100pH 20fF OUT Activate 450fF 450fF 450fF 270fF 270fF 0.45mA 0.45mA 320pH V bias 2.5 V 3-Stage LNA SiGe SOI Detector VGA RF in 110fF 1.5mA 30pH : 30pH 100fF 1.5mA 100fF 1.5mA IN 100fF 320pH 50µA 70pH : 250pH 25fF V bias 2.5V 450fF 2.5 V 450fF 150pH : 450pH 1.5mA 450fF G C V det G C2 450fF 2kΩ 450fF 2kΩ 450fF 2kΩ V bias V bias V bias 640fF IN 450fF IN 450fF LNA Detector Modulator VGA 20mm x 23 mm 1st low power W band activetag in 55nm SiGe BiCMOS 19dB gain, 9GHz BW, and NF 50 < 9 db Wake up function with 62dB sensitivity 25/10.8mW in active/stand by mode from 2.5/1.8 V supplies mm x 0.88 mm

AiP Chip PCB AiP Chip PCB Fully-Packaged System Antenna- in- Package TX RX 3D-Printed Lens PCB (1.62x1.

Data In RX RF In OOK TX Buffer 1:1 VCO Current Switching LNA V b,lna 1.

7V 2:1 Biasing Buffer OOK Transceiver Performance: A low-cost, energy efficient, high-capacity, scalable,

Measurement results verify 12.5Gbps OOK data transmission over 5m.

Enabled by high gain antenna, efficient and low-cost packaging, and efficient TRX design.

27 AiP Chip PCB AiP Chip PCB Fully-Packaged System Antenna- in- Package TX RX 3D-Printed Lens PCB (1.62x1.98mm 2 ) IC A Compact 130 GHz Fully-Packaged Point-to-Point Wireless System with 3D-Printed 26dBi Lens Antenna Achieving 12.5Gbps at 1.55 pj/bit/meter TX Data In RX RF In VCOtune OOK TX Buffer 1:1 VCO Current Switching LNA V b,lna 1.5V 40mm OOK RX 1:1 V b,ed PA ED 2.7V 2:1 Biasing Buffer TRX Power Consumption <100mW TX RF Out RX Data Out TX 0 RX OOK Signal TX Data In RX RF In OOK TX Buffer 1:1 VCO Current Switching LNA V b,lna 1.5V VCOtune OOK RX 1:1 V b,ed PA ED 2.7V 2:1 Biasing Buffer OOK Transceiver Performance: A low-cost, energy efficient, high-capacity, scalable, easy-to-deploy, and fullypackaged point-to-point wireless link using OOK modulation. Measurement results verify 12.5Gbps OOK data transmission over 5m. Energy/bit/range FoM is improved >40x compared to the state-of-the-art. Enabled by high gain antenna, efficient and low-cost packaging, and efficient TRX design. TX RF Out RX Data Out BGA Package Stack-Up Aperture-coupled patch antennas Prepreg (75μm) feed RO4003 (200μm) B55 Technology Enablers: - High integration density. - Combined RF/baseband solutions using BiCMOS technology. - High f T /f max enabling high-frequency operation. - High output power enabled by high performance and efficient BJTs. [Nemat Dolatsha, et al. ISSCC 2017] Antenna-in-Package Prepreg (75μm) RF Pads IC Footprint Bottom Feed Top Ring Cavity 1mm 7x7mm 2 Patches

28 ST and the CMP 28 A continued collaboration since almost 30 years Win-win operation Recognized by ST as best service unit for SME and research institutes Supports ST s customers for small volume business Creating ecosystem in advanced More Moore and More Than Moore Silicon technologies The CMP: a professionnal team dedicated to their Users best experience in designing and prototyping IC s

29 29

Technology Advantages for Analog/RF & Mixed-Signal Designs

Technology Advantages for Analog/RF & Mixed-Signal Designs Andreia Cathelin STMicroelectronics, Crolles, France SOI Consortium Forum, Tokyo, January 21 st, 2016 Agenda 2 At a glance ST 28nm UTBB FD-SOI