Designing Analog and RF Circuits for Ultra-Low Supply Voltages. Peter Kinget
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1 Designing Analog and RF Circuits for Ultra-Low Supply Voltages Peter Kinget
2 Motivation Past 4 decades in electronics: IC Technology Progress! Device Scaling IC Design Progress! More Integration Sub 100nm technologies (c) 2007 Peter Kinget 3
3 Nano CMOS : Supply Voltage Thick oxide V DD Thin oxide V DD [ITRS'05] Thin oxide V T O High Perf.! Low Standby V Low Power Technology node [nm] (c) 2007 Peter Kinget 4
4 World is Analog *^%&*$ ;-) Analog/RF Interfaces Digital Core SOC Analog & RF bring the bits to life (c) 2007 Peter Kinget 5
5 Lower Cost Less Leakage Less Power V DD Scaling SCALE!! Do NOT Scale!! Less SNR, Less Accuracy, More Power D A (c) 2007 Peter Kinget 6
6 Lowest Energy Digital V DD Energy per instr. (a.u.) V V DD [Hanson 2006] 8-bit microprocessor in 0.13um CMOS (c) 2007 Peter Kinget 7
7 System on a Chip D Digital: Scale!! 80-95% Do NOT Scale!! A Analog: 5-20% (c) 2007 Peter Kinget 8
8 Of course There are thick oxide devices; There are DC-DC converters or custom supplies; Heterogeneous technologies can be combined with system in a package,. (c) 2007 Peter Kinget 9
9 Disappearing Electronics E.g., pico nodes in wireless sensor nets Scavenge energy with one solar cell V DD 0.4 to 0.5V [Rabaey 2006] (c) 2007 Peter Kinget 10
10 Analog Assist for Digital Digital Gates Supply Noise Monitor Embed analog monitors in digital circuits to monitor temperature, V TH, V DD, substrate interference, signal integrity,. Need to be fully compatible to digital (layout, VDD, technology, ) [Petrescu 2006] (c) 2007 Peter Kinget 11
11 So, let s explore, how we can design ultra-low voltage analog & RF ICs? (c) 2007 Peter Kinget 12
12 Outline Motivation The Challenges The Opportunities Device Sizing & Biasing Building Block Topologies System Level Solutions Outlook & Conclusions (c) 2007 Peter Kinget 13
13 MOST Biasing: CS or VCCS r o,n //r o,p 90nm W=2u V GS,p r o,p V out r o,n Swing V V GS,n Transconductor or Current Source V DS > 0.1V to 0.15 V (for V GS -V TH! 0.2 V) V out [V] Moderate to Strong Inversion (V GS -V TH ) " 0.15 V & V TH = 0.35V! V GS = 0.5V V TH = 0.15V! V GS = 0.3V (c) 2007 Peter Kinget 14
14 Ultra-LV Challenges in OTAs V out+ 0.25V " V casp V casn " 0.5V 0.15V 0.3V 0.15V " " " V in+ V in- 0.15V 0.15V V casn V casp 0.15V V out- 0.25V 0.15V " 0.3V CMFB (c) 2007 Peter Kinget V
![Gate Leakage Gate Current Density [A/cm 2 ] Gate Voltage [V] [Taur 1999] Gate](/docs-images/89/99997209/images/15-2.jpg "current decreases exponentially with decreasing oxide voltage (c) 2007 Peter")
15 Gate Leakage Gate Current Density [A/cm 2 ] Gate Voltage [V] [Taur 1999] Gate current decreases exponentially with decreasing oxide voltage (c) 2007 Peter Kinget 16
![Reliability Time to Breakdown (63%) [s]](/docs-images/89/99997209/images/16-2.jpg "Gate Voltage [V] [Stathis 2002] Time to")
16 Reliability Time to Breakdown (63%) [s] Gate Voltage [V] [Stathis 2002] Time to Breakdown increases exponentially with decreasing gate voltage (c) 2007 Peter Kinget 17
17 RSCE V T as L Device Level Solutions V TH 400mV 270mV 150mV 180nm 130nm 90nm Forward Body-Bias 4 L/L min deep n-well NMOS V TH V BS =0.5V #V T ~ -50mV V DD V BS (c) 2007 Peter Kinget 18
18 Building Block Solutions Rethink your topologies!! Examples: 0.18um OTAs V T = 500mV = V DD 90nm OTAs V T = mV (c) 2007 Peter Kinget 19
19 OTAs: CM Level Shifting 0.5 V 0.4 V R b = 2/3 R i R f 0.25 V 0.25 V 0.4 V [Bult 2000] 0.5 V [Karthikeyan 2000] (c) 2007 Peter Kinget 20
20 0.5V Gate-Input OTA Stage V out- 0.5 V V out+ Local Common- Mode Feedback Common-Mode Feed Forward Cancellation Neg. G Gain Boost V bn V NR V in+ V in- (c) 2007 Peter Kinget 21
21 0.5V Two-Stage OTA in 0.18um V T,nom =0.5V; CM in 0.4V 62dB DC gain; 10MHz GBW; 10pF C L,diff ; 75uW (c) 2007 Peter Kinget 22
22 On-Chip Biasing Circuits Error amp. bias Gain bias OTA replica OTA (one stage) Level shift bias DC CM bias (c) 2007 Peter Kinget 23
23 0.5V Two-Stage OTA in 90nm 0.5 V I LS V in+ V in- V out+ V out- I NR I TAIL V T,nom =0.3V; CM in 0.25V 8dB -G gain boost 1 st stage; 45dB DC gain; 175MHz GBW; 4pF C L,diff ; 625uW Bias circuits not shown FBB not shown (c) 2007 Peter Kinget 24
24 THA, ADCs System Functions Floating switch problem RF Receivers & Synthesizers Continuous-time filters Tuning challenge (c) 2007 Peter Kinget 25
25 Floating Switch Challenge 0.5V Conductance NMOS 2u/80n PMOS 4u/80n V in NMOS 4.4u/180n 10k$ PMOS 9u/180n 0 V in nm: V TH = 0.3V 180nm: V TH = 0.55V (c) 2007 Peter Kinget 26
![+V ON % 1 [Crols 1994] Switched](/docs-images/89/99997209/images/26-2.jpg "R-C % 2 0 % 2 % 1 - + - + % 2 % 2")
![- + % 1 [Nakagome 1991][Abo 1999]](/docs-images/89/99997209/images/26-4.jpg "[Ahn 2005] (c) 2007 Peter Kinget")
26 Addressing Floating Switches Low V TH switch Switched Opamp % 1 % 2 - % 2 % 1 + % 2 % 2 % CLK Boost or Bootstrap 2V DD or V in +V ON % 1 [Crols 1994] Switched R-C % 2 0 % 2 % % 2 % % 1 [Nakagome 1991][Abo 1999] [Ahn 2005] (c) 2007 Peter Kinget 27
27 Addressing Floating Switches Low V T switch devices Clock boosting or bootstrap Switched opamp Switched R-C RTO signaling for CT!" ADCs Cascaded sampling to reduce low-v TH switch leakage Common-mode level shift (c) 2007 Peter Kinget 28
28 3 rd order CT!" Modulator Using Active RC integrators % DAC + Vin - Q Q Digital Output % DAC (c) 2007 Peter Kinget 29
29 RZ Challenge: Switches at V DD /2 0.5V VCM 0V D0 % RZ D V RZ DAC_n v 2 V cm,ota V 1 Rdac C v 1 Switch Conductance 0.25 V + Vin Ri 0.25 V V 2 Rdac C D1 % RZ 0.5V VCM 0V D0 RZ DAC_p 0.25 V (c) 2007 Peter Kinget 30
30 Solution: Return-to-Open When RZ: (Q=1) Problem switches removed 0.5V 0V D0 v 1 D1 Rdac RTO DAC_n C v 2 V cm,ota 0.25 V + Vin Ri v 1 Rdac C RZ v 2 D1 0.5V 0V D0 RTO DAC_p (c) 2007 Peter Kinget 31
31 0.5V 74 db SNDR 25kHz!" Modulator 1mm Operation for V DD = 0.45V to 0.8V Return-to-open architecture, body-input gate-clocked circuits 74dB SNDR, 25kHz, 64x OSR, 300#W, 0.18um CMOS [Pun, Chatterjee, Kinget, ISSCC 06, JSSC 07] (c) 2007 Peter Kinget 32
32 CM Level Shift & Switches 0.5V Differential Track and Hold TRACK Phase 0.4V CM virtual short no signal swing across Switch: clk gate & body! (c) 2007 Peter Kinget 33
33 CM Level Shift & Switches 0.5V Differential Track and Hold HOLD Phase 0.4V CM Switch: no signal swing across Switch: clk gate & body! (c) 2007 Peter Kinget 34
34 0.5V 1Msps 60dB T/H amplifier Biasing circuits SNDR Track-and-holds True low voltage No CLK boosting [Chatterjee, Kinget, VLSI 06, JSSC07] Input amplitude [dbv] 0.25!m CMOS V TH = 0.6V 60dB SNDR 1Msps 0.6mA at 0.5V (c) 2007 Peter Kinget 35
35 Low V TH switch leakage: W/L=12/0.36 V TH =0.15V 0.01mV/ns 0.12mV/ns 35 (c) 2007 Peter Kinget 36
36 0.5V 8bit 10Msps Pipelined ADC 100kHz 10MHz No internal voltage or clock boosting; regular devices; cascaded sampling technique. Aux. S/H for the sub-adc to eliminate front-end SHA. 10Msps: SNDR 2.4mW in 90nm CMOS [Shen, Kinget, VLSI07]. (c) 2007 Peter Kinget 37
![[Yoshizawa 2002] CM Level Shift Switched](/docs-images/89/99997209/images/37-2.jpg "Tuning Variable Duty Cycle Switched-R V")
![LS V LS V IN V IN [Huang 2001] V V OUT](/docs-images/89/99997209/images/37-3.jpg "OUT [Kurahashi 2006] (c) 2007 Peter")
37 Tuneable Lossy RC Integrator MOSFET-C V TUNE >> V DD V IN V TUNE V OUT V IN V OUT [Yoshizawa 2002] CM Level Shift Switched Tuning Variable Duty Cycle Switched-R V LS V LS V IN V IN [Huang 2001] V V OUT OUT [Kurahashi 2006] (c) 2007 Peter Kinget 38
38 Low-voltage tunable integrator using varactor V DD 0.25 V + V in V - V out + V DD C gs / C ox 0.4 V V tune [V] (c) 2007 Peter Kinget 39
39 0.5V Fully Integrated 5th Order LPF 1mm 135 khz Filter PLL 1mm Gain [db] OTAs Biasing circuits Operation at 0.45 V to 0.6 V 1.1 mw power dissipation 57 db dynamic range Frequency [Hz] [Chatterjee, Tsividis, Kinget, ISSCC05, JSSC05] (c) 2007 Peter Kinget 40
40 A 0.5V 2.4GHz Receiver ISM band applications Sliding IF topology: only 1 RF Mixer LNA, Mixers, VGA + on chip RF, IF & BB filtering (c) 2007 Peter Kinget 41
41 LNA, IMR, & RF Mix IMR Filter IF Filter LNA Mixer Switched Gm Mixer [Klumperink 2004] (c) 2007 Peter Kinget 42
42 A 0.5V 2.4GHz Receiver Gain 30dB; NF 18dB; IIP3-22dBm 90nm CMOS 8.5mW [Stanic, Balankutty, Kinget, Tsividis, RFIC07] (c) 2007 Peter Kinget 43
43 0.65V/0.5V GHz Fractional-N Synthesizer in 90nm CMOS VCO swing within the supply rails for reliability. Fractional-N DSM dithering shifted to later divider stages to prevent noise injection into forward biased body. Staggered clock to prevent jittering caused by simultaneous switching. ISM Band applications: 3MHz for 6mW [Yu, Kinget, ISSC07] (c) 2007 Peter Kinget 44
44 Outlook
45 Where do we go from here Other nanoscale challenges: Smaller g m /g o. Gate & subthreshold leakage. Reduced body effect: g m,b # for L #. Opportunities: Device speed significantly improves. Calibrate using abundant digital gates. FinFETs, dual gate devices,. (c) 2007 Peter Kinget 47
46 Nanoscale Opportunities FinFETs, dual gate devices,. V GATE2 =-1.2 to 1.2V GATE 2 V GATE1 GATE 1 [Mathew 2005] (c) 2007 Peter Kinget 48
47 LV Challenge: Interfaces V CKT out Z Transf. 4dBm 1.0Vpp -2dBm 0.5Vpp 50" Filt./Z Match in CKT 50" (c) 2007 Peter Kinget 49
48 Power Dissipation Limits Noise limited circuits [Vittoz90]: Mismatch limited circuits [Kinget96]: ideal class B (c) 2007 Peter Kinget 50
49 Low Voltage Power Penalty Finite V DSsat : V DSsat (c) 2007 Peter Kinget 51
50 ADC FOM vs V DD pj/conv. V DD Most data taken from B. Murmann, A/D Converter ISSCC Performance Data (c) 2007 Peter Kinget 52
51 Ultra-low Voltage Analog & RF Design Techniques Exploit full device characteristics RSCE, Body-bias Rethink your topologies Eliminate stacks, LCMFB, CMFF, Neg. G Revise your architectures Eliminate switches, address leakage, revise tuning paradigms Plenty of open opportunities!! (c) 2007 Peter Kinget 53
52 Acknowledgments Collaborators: Y. Tsividis, K. P. Pun (City Univ. Hong Kong), S. Chatterjee (now IIT Delhi), A. Balankutty, Y. Feng, J. Shen, N. Stanic, S. Yu. U.K. Moon (Oregon State Univ.) for technical discussions. Analog Devices, Bell Labs, Intel, Realtek, Silicon Labs, for financial support. Europractice, Philips (now NXP) and UMC for fabrication support. Integrand Software for EMX software. (c) 2007 Peter Kinget 54
53 0.5V Analog Roadmap Complexity 90nm 180nm 250nm Thank you for your attention! 135kHz LPF + Tuning CT 74dB 25kHz #" A/D 2.4GHz RCV 2.4GHz Synth. 8b 10Ms A/D DT "# ADC Body-input OTA Gate-input OTA & Biasing 0.5V Varactor 10b 1Ms THA Comparators 900MHz RF Front-end Basic blocks (c) 2007 Peter Kinget 55
54 References [Rabaey 2006]: J. Rabaey et al., The roadmap to disappearing electronics and ambient intelligence, IEEE Circuits and Devices Magazine, pp , July/August [Hanson 2006]: S. Hanson et al., Ultralow-voltage, minimum-energy CMOS, IBM J. Research & Development, Vol. 50, No. 4/5, pp , July/september [Mathew 2004]: L. Mathew et al., CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET), IEEE International SOI Conference, [Stathis 200]: J.H. Stathis, Reliability limits for gate insulator in CMOS technology, IBM J. Research & Development, Vol. 46, No. 2/3, pp , March/May [Karthikeyan 2000] S. Karthikeyan, S. Mortezapour, A. Tammineedi, and E. Lee, Low-voltage analog circuit design based on biased inverting opamp configuration, IEEE Trans. Circuits Syst. II,vol. 47, no. 3, pp , March [Bult 2000] K. Bult, Analog design in deep sub-micron CMOS, in European Solid- State Circuits Conference (ESSCIRC), September 2000, pp (c) 2007 Peter Kinget 56
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