Designing Analog and RF Circuits in Nanoscale CMOS Technologies: Scale the Supply, Reduce the Area and Use Digital Gates.

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1 Designing Analog and RF Circuits in Nanoscale CMOS Technologies: Scale the Supply, Reduce the Area and Use Digital Gates. Peter Kinget Université Catholique de Louvain (Belgium) On sabbatical from: Columbia University (New York)

2 4 Decades of Exponential Growth Moore s Law G. Moore, No Exponential is forever, but we can delay forever, ISSCC 2003 IC Technology Progress! Device Scaling IC Design Progress! More Integration Analog, RF, digital on a Chip = System on Chip Next, highly scaled technologies

3 Lowest Energy Digital V DD Energy per instr. (a.u.) V V DD [Hanson 2006] 8-bit microprocessor in 0.13um CMOS

4 V DD Scaling for Nanoscale CMOS V]! ITRS 09 Technology node [nm] Year

5 Reduce Area: Motivation Number of DFFs within an area of 200um x 200um

6 Design Techniques to Keep Analog & RF Compatible with Nanoscale CMOS Scale the Supply Voltage of Analog/RF Circuits Reduce the Area of RF circuits Use Digital Gates to Improve Analog/RF Performance

7 System on a Chip Scale!! Physical World is Analog Sound Image Digital: 80-95% Radio Do NOT Scale!! Energy Analog: 5-20%

8 Systems Columbia s V Analog & RF Roadmap Analog V DD scaling, Sure we can 2.4GHz RCV+Synth Functions 90nm 180nm 250nm CT 74dB 25kHz!" A/D 2.4GHz LO Synth. 2.4GHz RCV Blocks Body-input OTA 135kHz LPF + Tuning Gate-input OTA 10b 1Ms THA 900MHz RF Front-end 8b 10Ms A/D 0.6V V DD V-Reference

9 MOST Biasing: CS or VCCS r o,n //r o,p 90nm W=2u V GS,p r o,p V out r o,n Swing V V GS,n V Transconductor or Current Source out [V] V DS > 0.1V to 0.15 V (for V GS -V TH! 0.2 V) Moderate to Strong Inversion (V GS -V TH ) " 0.15 V & V TH = 0.35V! V GS = 0.5V V TH = 0.15V! V GS = 0.3V

10 Ultra-LV Challenges in OTAs " 0.5V V casp " V casp V in+ V " in- V casn V casn V out+ 0.25V " V out- 0.25V simple anim. " CMFB

11 Ultra-low Voltage Analog & RF Design Exploit full device characteristics RSCE, Body-bias Rethink your circuit topologies Eliminate stacks, LCMFB, CMFF, Neg. G Address leakage (cascaded switches), MOS or Schottky based references Revise your architectures Eliminate switches in signal path (e.g., RTO), RF front end: Current mode operation/interfaces RF Baseband: Optimize structure True low voltage design: no voltage boosting, no special devices

12 RSCE V T as L Device Level Solutions V TH 400mV 270mV 150mV 180nm 130nm 90nm Forward Body-Bias 4 L/L min deep n-well NMOS V TH V BS =0.5V #V T ~ -50mV V DD V BS

13 0.5V Gate-Input OTA Stage V out- 0.5 V V out+ Local Common- Mode Feedback Common-Mode Feed Forward Cancellation Neg. G Gain Boost V bn V NR V in+ V in-

14 0.5V Two-Stage OTA V T,nom =0.5V; CM in 0.4V, 0.18um CMOS 62dB DC gain; 10MHz GBW; 10pF C L,diff ; 75uW

15 On-Chip Biasing Circuits Error amp. bias Gain bias OTA replica OTA (one stage) Level shift bias DC CM bias

16 0.5V Fully Integrated 5th Order LPF 1mm 135 khz Filter PLL 1mm Gain [db] OTAs Biasing circuits Operation at 0.45 V to 0.6 V 1.1 mw power dissipation 57 db dynamic range Frequency [Hz] [Chatterjee, Tsividis, Kinget, ISSCC05, JSSC05]

17 Floating Switch Challenge 0.5V Conductance NMOS 2u/80n PMOS 4u/80n V in NMOS 4.4u/180n 10k$ PMOS 9u/180n 0 V in nm: V TH = 0.3V 180nm: V TH = 0.55V

18 3 rd order CT ΣΔ Modulator Using Active RC integrators % DAC + V i n - Q Q D i g i t a l O u t p u t % DAC

19 RZ Challenge: Switches at V DD / V V C M 0 V D0! R Z D V R Z D A C _ n Vdac 0.5V v 2 V cm,ota V 1 R d a c C 0V v 1 Ts t Switch Conductance 0.25 V + V i n R i 0.25 V V 2 R d a c C D1! R Z 0. 5 V V C M 0 V D0 R Z D A C _ p 0.25 V

20 Solution: Return-to-Open When RZ: (Q=1) Problem switches removed 0.25 V 0. 5 V 0 V D0 + V i n v 1 D1 R d a c R i R T O D A C _ n C Vdac 0.5V 0V v 2 v 1 Ts V cm,ota t # Lower Noise R d a c v 2 D1 D V 0 V C R T O D A C _ p D1 D0 Q RZ Ts Ts Ts t t t

21 0.5V 74 db SNDR 25kHz ΣΔ Modulator 1mm Operation for V DD = 0.45V to 0.8V Return-to-open architecture, body-input gate-clocked circuits 74dB SNDR, 25kHz, 64x OSR, 300μW, 0.18um CMOS [Pun, Chatterjee, Kinget, ISSCC 06, JSSC 07]

22 V in 12u 0.36u 12u W/L=12/0.36 V TH =0.15V Low V TH switch leakage: Cascaded Sampling (Sim.) 0.36u!1!1 S1 1pF C1 Vout V in 12u 0.36u 12u 0.36u!1!1d d S2 S1! 1 V 1 250fF C2!1 12u 0.36u 12u 0.36u 1pF C1 V out 0.01mV/ns 0.12mV/ns 27

23 0.5V 8bit 10Msps Pipelined ADC B d kHz 10MHz 20 SFDR 10 SNR SNDR Sample Rate (MHz) 8 10 No internal voltage or clock boosting; regular devices; cascaded sampling technique. Aux. S/H for the sub-adc to eliminate front-end SHA. 10Msps: SNDR 2.4mW in 90nm CMOS [Shen, Kinget, VLSI07, JSSC08].

24 [90nm CMOS] ULV Schottky Reference V DD = V Vdd OTA REFERENCE STARTUP Rb 10k W=10u W=10u Ro L=0.2u L=0.2u P4 P5 P6 Rc Cc W=50u L=0.08u W=40u L=0.3u P1 W=40u L=0.3u P2 W=40u L=0.3u P3 W=2u L=0.3u Ps1 W=4.8u L=0.6u M3 M1 W=100u W=100u L=0.08u L=0.08u M4 W=7u L=0.6u M2 M5 W=2.4u L=0.6u R2a R1 1k 2.13k 1 N R2b 2.13k R3 Vref 1.17k Ms1 W=20u L=0.3u Ms2 W=20u L=0.08u V REF =250mV

25 0.6V 2.4GHz ZIF/LIF RCV + Synth. 2.9 mm 2-90nm RVT CMOS - 64-pin QFN package GHz 0.6V & 32mW 16dB NF, -10.5dBm IIP 3, 67dB Gain PN 3MHz offset Fully functional 0.55V to 0.65V V DD

26 Design Techniques to Keep Analog & RF Compatible with Nanoscale CMOS Scale the Supply Voltage of Analog/RF Circuits Reduce the Area of RF circuits Use Digital Gates to Improve Analog/RF Performance

27 Use f T for VCO Area Scaling Scaled CMOS $ higher f T $ N x higher frequency $ divide by N D A D/2 A/4 D/4 A/16 D/8 A/64 L, Rs, 0 L/2, Rs, 0 L/4, Rs, 0 L/8, Rs, 0

28 VCO Area Scaling FoMA = FoM -10log(A/1mm 2 ) +18dB Area/64 [Yu, Kinget, TCASII 09] [Sim. in 45nm]

29 PLL and Area Scaling Scale to 4 x f 0 Circuits that scale easily with feature size pf needs ~13000um 2 of inversion-mode MOS capacitor

30 Stacked MOS Cap-Inductor (EM Simulation) $ no Q degradation, even improvement (shielding)

31 0.042mm2 Fully Int. PLL Loop Filter Capacitor C2 Area Saving 30% [Yu, Kinget, Esscirc 08] Fully Integrated PLL, on-chip loop filter under VCO inductor 45nm LP CMOS; VDD=0.85V; 10GHz VCO; 2.5GHz o/p

32 All-Digital PLLs LC-DCO. DCO ADPLL DCO ADPLL [Weltin-Wu, 2008] [Staszewski, 2004]

33 Area & Performance Comparison!"#$%&!'()**++,-(./01(234556(5+(7+8( Silicon Area [mm 2 ] <LCC"TB%P()**++,-6()%;'=QLC&BALM"&)+( UFD&GFU/01(5+(7+8(L%#J( IJ#JBKLM()**++,D(,FE&-/01(234556(IN%O(8P=6( 3B#Q()**++,G( 9,/01(3+8(L%#J6(5+(7+8( /"ABCB()**++,D( EFG&9-/01(24556(5+7+8( VWNP(XLCK( :FE/01(24556(5+(7+8( 10x Technology Node [nm]

34 Design Techniques to Keep Analog & RF Compatible with Nanoscale CMOS Scale the Supply Voltage of Analog/RF Circuits Reduce the Area of RF circuits Use Digital Gates to Improve Analog/RF Performance

35 Use Digital Gates In RF How? For RF, improvement of linearity using digital gates has many opportunities The signals generating the errors are out-of-band interferers, which do not reach the baseband In contrast to mixed signal digital assistance we need to address problem in the front-end for RF!! Use digital assistance to self-calibrate RF front-end

36 Digital Self-Calibration of RCV IIP2 Block Diagram Measured Results Receiver >40dB IIP2 improvement! [ISSCC 2010] Performance very stable w.r.t. any changes (VDD, freq., ) Simpler, lower power RF circuits can be used taking advantage of calibration engine Low Power, no extra power consumption for RF operation!

37 ULV RCV with FF In-band Interf. Cancel. Front-end Interferer Cancellation significantly reduces baseband linearity requirements resulting in a significant performance improvement >20dB of attenuation for out of channel blockers Digital calibration of LO phase ( ) and alt. path gain is key enabler to automatically tune the position of the cancellation notch Measured

38 0.6V GSM Receiver 55dB Gain, 6dB NF, -15.5dBm IIP 3, [VLSI, 2010] 0.6V (LNA, Mixers, Cancellers, Baseband, LO Buffers) 65nm CMOS

39 Review & Outlook

40 Fundamentals: Power Limits Noise limited circuits [Vittoz90]: SNR = V RMS v 2 n,rms = kt v 2 C I DC = 2f C 2V RMS n,rms Acc = V RMS 3"(V os ) P " 8 kt f SNR2 " 2 (V os ) = C ox A 2 VT C V DD = 2 2V RMS Mismatch limited circuits [Kinget96]: P " 24 C ox A 2 VT f Acc 2 I DC = 2f C ideal class B 2V RMS

41 Low Voltage Power Penalty Finite V DSsat : V DD = 2 2V RMS + 2V DSsat V DSsat

42 ADC FOM vs V DD FOM = 2 "BW "2 P SNDR# pj/conv. V DD Most data taken from B. Murmann, A/D Converter ISSCC Performance Data

43 Receiver FOM vs V DD FOM 2 = IIP 3 NF " P

44 End of Moore s Law? (as we know it) [ITRS 2007]

45 ITRS After Moore? Half-Pitch; Gate-Length [nm] 10?

46 Conclusions Scaling is driving semiconductor technology and will continue for another decade, but with significant design challenges. Future Analog/RF in nanoscale CMOS Reduce supply voltage Reduce area Exploit digital gates Design is becoming a prime differentiator Plenty of open opportunities!!

47 Acknowledgments Collaborators: Y. Tsividis, K.P. Pun (Chinese Univ. Hong Kong), S. Chatterjee (now IIT Delhi), F. Zhang (now TI), B. Hung and T.L. Li (UMC), A. Balankutty (now Intel), Y. Feng (now MHI Consulting), J. Shen (now ADI), N. Stanic (now SiLabs), C. Vezyrtzis, and S. Yu (now MaxLinear). Analog Devices, Bell Labs, Broadcom, Intel, Marvell, Silicon Labs and Toshiba for financial support. Europractice, Philips (now NXP), Toshiba, ST Microelectronics and UMC for fabrication support. Integrand Software for EMX software.

48 Complexity 90nm 180nm 250nm Analog V DD scaling, Sure we can Thank you CT 74dB 25kHz!" A/D 2.4GHz LO Synth. 2.4GHz RCV for your attention! 2.4GHz RCV+Synth 135kHz LPF + Tuning 8b 10Ms A/D Body-input OTA Gate-input OTA 10b 1Ms THA 900MHz RF Front-end 0.6V V DD V-Reference

49 ULV Analog & RF Selection of References P. Kinget, "Designing Analog and RF Circuits for Ultra-low Supply Voltages,", plenary talk, IEEE European Solid-State Circuits Conference, pp , September S. Chatterjee, Y. Tsividis and P. Kinget, "0.5 V Analog Circuit Techniques and Their Application in OTA and Filter Design," invited, IEEE Journal of Solid-State Circuits, vol. 40, no 12, December 2005, pp K.P. Pun, S. Chatterjee, and P. Kinget, "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-to-Open DAC," IEEE Journal of Solid-State Circuits, Vol. 42, no 3, pp , March J. Shen and P. Kinget, "A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS," invited, IEEE Journal of Solid-State Circuits, Special issue on the 2007 Symposium on VLSI circuits, vol. 43, no. 4, pp , Apr N. Stanic, A. Balankutty, P. Kinget and Y. Tsividis, "A 2.4-GHz ISM-Band Sliding-IF Receiver with a 0.5 V Supply," invited, IEEE Journal of Solid-State Circuits, Special issue on the 2007 Radio Frequency Integrated Circuits Conference, vol. 43, no. 5, pp , May A. Balankutty, S.-A. Yu, Y. Feng, and P. Kinget, " A 0.6V 32.5mW Highly Integrated Receiver for 2.4GHz ISM-Band Applications,", IEEE International Solid-State Circuits Conference (ISSCC), pp , 620 February P. Kinget, C. Vezyrtzis, E. Chiang, B. Hung and T.L. Li, "Voltage References for Ultra-low Supply Voltages," invited, IEEE Custom Integrated Circuits Conference, pp , Sept S.A. Yu and P. Kinget, "A 0.65-V 2.5-GHz Fractional-N Synthesizer with 2-Mbps GFSK Modulation", IEEE Journal of Solid- State Circuits, Reducing Area See F. Zhang and P. Kinget, "Design of Components and Circuits Underneath Integrated Inductors," IEEE Journal of Solid- State Circuits, Oct. 2006, pp S.A. Yu and P. Kinget, "A mm2 Fully Integrated Analog PLL with Stacked Capacitor-Inductor in 45nm CMOS," European Solid-State Circuits Conference, pp , Sept S.A. Yu and P. Kinget, "Scaling LC Oscillators in Nanometer CMOS Technologies to Smaller Area but with Constant Performance," IEEE Transactions on Circuits and Systems II, May Digitally-assisted RF Y. Feng, G. Takemura, S. Kawaguchi, N. Itoh and P. Kinget, "A Low-power Low-noise Direct-Conversion Front End with Digitally Assisted IIP2 Background Self Calibration," IEEE International Solid-State Circuits Conference, accepted, A. Balankutty and Peter Kinget, 0.6V, 5dB NF, -9.8dBm IIP3, 900MHz Receiver with Interference Cancellation, submitted to the IEEE Symposium on VLSI circuits, 2010.