Summary last lecture

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1 EE247 Lecture 7 Summary last lecture Automatic onchip filter tuning (continued from last lecture) Continuous tuning Reference integrator locked to a reference frequency Error due to integrator DC offset and cancellation method DC tuning of resistive timing element Periodic digitally assisted tuning Systems where filter is followed by ADC & DSP, existing hardware can be used to periodically update filter freq. response Continuoustime filters High pass filters Bandpass filters Lowpass to bandpass transformation Example: 6 th order bandpass filter EECS 247 Lecture 7: Filters 2006 H.K. Page Summary last lecture Continuoustime filters Opamp MOSFETC filters Opamp MOSFETRC filters C filters Frequency tuning for continuoustime filters Trimming via fuses Automatic onchip filter tuning Continuous tuning Utilizing VCF built with replica integrators Use of VCO built with replica integrators Reference integrator locked to reference frequency EECS 247 Lecture 7: Filters 2006 H.K. Page 2

2 MasterSlave Frequency Tuning Reference Integrator Locked to Reference Frequency Replica of main filter C Vin Vref I=*Vref C Vout V tune Replica of main filter integrator e.g. C building block used Utilizes the fact that a DC voltage source connected to the input of the cell generates a constant current proportional to the transconductance and the voltage reference I =.Vref EECS 247 Lecture 7: Filters 2006 H.K. Page 3 Reference Integrator Locked to Reference Frequency Consider the following sequence: Integrating capacitor is fully t=0 At t=0 the capacitor is connected to the output of the cell then: Vin Vref I=*Vref Vout V tune Q = V = V ref T V = V ref T V T V = V ref T If V =V ref then: t=0 time C = T = N fclk EECS 247 Lecture 7: Filters 2006 H.K. Page 4

3 Reference Integrator Locked to Reference Frequency Replica of main filter Vref S2 S3 S A Three clock phase operation To analyze study one phase at a time Ref: A. Durham, J. Hughes, and W. Redman White, Circuit Architectures for High Linearity Monolithic ContinuousTime Filtering, IEEE Transactions on Circuits and Systems, pp , Sept EECS 247 Lecture 7: Filters 2006 H.K. Page 5 Reference Integrator Locked to Reference Frequency P high S closed Vref S2 S3 S A discharged V =0 retains its previous charge EECS 247 Lecture 7: Filters 2006 H.K. Page 6

4 Reference Integrator Locked to Reference Frequency P2 high S2 closed Vref S2 I=*Vref S3 A charged with constant current: I=*Vref retains its previous charge P2 V V = V ref T2 T T2 EECS 247 Lecture 7: Filters 2006 H.K. Page 7 Reference Integrator Locked to Reference Frequency P3 high S3 closed Vref S2 S3 ΔV A T T2 charge shares with Few cycles following startup Assuming A is large, feedback forces: ΔV 0 V = Vref EECS 247 Lecture 7: Filters 2006 H.K. Page 8

5 Reference Integrator Locked to Reference Frequency P3 high S3 closed Vref S2 S3 A T T2 V = V = Vref since: V = V ref T2 then: Vref = V ref T2 or: = T2 = N / fclk EECS 247 Lecture 7: Filters 2006 H.K. Page 9 Summary Replica Integrator Locked to Reference Frequency Vref S2 S3 A Tuning Signal To Main Filter Integrator time constant locked to an accurate frequency Tuning signal used to adjust the time constant of the main filter integrators Feedback forces to assume a value so that : τintg = = N /fclk or intg ω 0 = = fclk / N EECS 247 Lecture 7: Filters 2006 H.K. Page 0

6 Issues Loop Stability Vref S2 S3 A Tuning Signal To Main Filter Note: Need to pay attention to loop stability chosen to be smaller than tradeoff between stability and speed of look acquisition Lowpass filter at the output of amp. A helps stabilize the loop EECS 247 Lecture 7: Filters 2006 H.K. Page Issues 2GMCell DC Offset Induced Error Problems to be aware of: Vref S2 S3 A To Main Filter intg ω 0 = = fclk / N Tuning error due to master integrator DC offset EECS 247 Lecture 7: Filters 2006 H.K. Page 2

7 Issues Cell DC Offset What is DC offset? Simple example: For the differential pair shown here, mismatch in input device or load characteristics would cause DC offset: Vo = 0 requires a nonzero input voltage V in Vos M M2 Offset could be modeled as a small DC voltage source at the input for which with shorted inputs Vo = 0 Vtune Example: Differential Pair EECS 247 Lecture 7: Filters 2006 H.K. Page 3 Simple Cell DC Offset Mismatch associated with M & M2 DC offset Δ Vos = ( Vth Vth2 ) Vov,2 2 ( W L ) ( ) M,2 W L M,2 Vos V in M M2 Assuming offset due to load device mismatch is negligible Vtune Ref: Gray, Hurst, Lewis, Meyer, Analysis & Design of Analog Integrated Circuits, Wiley 200, page 335 EECS 247 Lecture 7: Filters 2006 H.K. Page 4

8 Cell Offset Induced Error Voltage source representing DC offset Vref Vos S2 S3 I=(Vref Vos) A Effect of cell DC offset: V = V = Vref Ideal: V = Vref T2 ( ref os) with offset: V = V V T2 V or: = T2 os V ref EECS 247 Lecture 7: Filters 2006 H.K. Page 5 Cell Offset Induced Error Vref Vos S2 S3 I=(VrefVos) A Example: V = T2 os f critical V ref for Vos = /0 Vref 0% error in tuning! EECS 247 Lecture 7: Filters 2006 H.K. Page 6

9 Cell Offset Induced Error Solution Assume differential integrator Add a pair of auxiliary inputs to the input stage for offset cancellation purposes Aux. Input Main Input V aux. in V main in M M3 C int g M4 M2 Vo EECS 247 Lecture 7: Filters 2006 H.K. Page 7 Simple Cell AC Small Signal Model V in M 2C intg V in C GS g M V in M M3 M M3 g m Vin g m Vm Vin2 in gm Vin2 r o 2C intg AC half circuit Small signal model ( M ) Vo = r m in o g V s 2Cint g r o is parallel combination of roof M & current source M gm ro M Vo = V in & gm ro = a Integrator finite DC gain s 2Cint gro M a g V m o = Vin Note: a, Vo = V a s 2C in int g s 2C int g M gm EECS 247 Lecture 7: Filters 2006 H.K. Page 8

10 Simple Cell Auxiliary Inputs AC Small Signal Model V in V in2 M 2C intg M3 V in V in2 C GS C GS3 M M3 M M3 g m Vin g m Vm Vin2 in gm Vin2 r o 2Cintg AC half circuit Small signal model ( ) V M M3 o = r m in m in2 o g V g V s 2Cint g r o parallel combination of roof M, M3, & current source M M3 gm ro gm r o = Vin Vin2 s 2Cint gro s 2Cint gro a a3 Vo = Vin V a s 2C in2 intg a3 s 2C intg M M3 gm gm EECS 247 Lecture 7: Filters 2006 H.K. Page 9 Cell DC Model Aux. Input Main Input V aux in = Vin2 C int g V aux. in ( V V ) Vo = a in os a2vin2 Vos M V main in = V in M3 M4 M2 EECS 247 Lecture 7: Filters 2006 H.K. Page 20

11 Reference Integrator Locked to Reference Frequency Offset Cancellation Incorporated P2 P3 Vref/2 Vcm Vref/2 P2B P2B C3a C3b P P2 P2 P P3 P3 P2 P3 Vtune cell two sets of input pairs Aux. input pair C3a,b Offset cancellation Same clock timing EECS 247 Lecture 7: Filters 2006 H.K. Page 2 Reference Integrator Locked to Reference Frequency P3 High (Update & Store offset) Vref/2 Vcm Vref/2 C3a s C3b Vout = Vos Vtune cell Unity gain configuration via aux. inputs Main inputs shorted, Charge sharing EECS 247 Lecture 7: Filters 2006 H.K. Page 22

12 Reference Integrator During Offset Cancellation Phase 0 ( V V ) Vo = a in os a2vin2 Vin2= Vo Vo = a Vos a2 Vo a Vo = Vos a2 Assuming a = a2 >> Vo = s & Vin2= Vos V C3a,b = Vos C3a C3b s Vout = Vos C3a,b Store main cell offset EECS 247 Lecture 7: Filters 2006 H.K. Page 23 Reference Integrator Locked to Reference Frequency P3 High (Update & Store offset) Vref/2 Vcm Vref/2 V C3a,b = Vos C3a s C3b Vout = Vos Vtune cell Unity gain configuration via aux. inputs Main input shorted C3a,b Store cell offset, Charge sharing EECS 247 Lecture 7: Filters 2006 H.K. Page 24

13 Reference Integrator Locked to Reference Frequency P High (Reset) Vref/2 Vcm Vref/2 V C3a,b = Vos C3a s C3b cell Reset. Discharge Hold Charge C3a,b Hold Charge Offset previously stored on C3a,b cancels gmcell offset Vtune EECS 247 Lecture 7: Filters 2006 H.K. Page 25 Reference Integrator Locked to Reference Frequency P2 High (Charge) Vref/2 Vcm Vref/2 V C3a,b C3a C3b = Vos V os I=gm(V ref s )( gm3s ) I=gmxVref Vtune cell Charging C3a,b Store/hold cell offset Hold charge EECS 247 Lecture 7: Filters 2006 H.K. Page 26

14 Summary Reference Integrator Locked to Reference Frequency Vref/2 Vcm Vref/2 C3a s C3b Vout = Vos Vtune Key point: Tuning error due to cell offset cancelled *Note: Same offset compensation technique can be used in many other applications EECS 247 Lecture 7: Filters 2006 H.K. Page 27 Summary Reference Integrator Locked to Reference Frequency Tuning error due to gmcell offset voltage resolved Advantage over previous schemes: Vref S2 S3 A f clk can be chosen to be at much higher frequencies compared to filter bandwidth (N >) Feedthrough of clock attenuated by filter Feedback forces to vary so that : τintg = = N /fclk or intg ω 0 = = fclk / N EECS 247 Lecture 7: Filters 2006 H.K. Page 28

15 DC Tuning of Resistive Timing Element replica of used in filter I Vtune Rext used to lock or onchip R Feedback forces =/Rext I Issues with DC offset Account for capacitor variations in the gmc implementation by trimming Rext. Ref: C. Laber and P.R. Gray, A 20MHz 6th Order BiCMOS Parasitic Insensitive Continuoustime Filter and Second Order Equalizer Optimized for Disk Drive Read Channels, IEEE Journal of Solid State Circuits, Vol. 28, pp , April 993 EECS 247 Lecture 7: Filters 2006 H.K. Page 29 Digitally Assisted Frequency Tuning Example:Wireless Receiver Baseband Filters A/D RF Amp IF Stage ( 0 to 2 ) Osc. π 2 A/D Digital Signal Processor (DSP) Systems where filter is followed by ADC & DSP Take advantage of existing digital signal processor to periodically update the filter critical frequency Filter tuned only at the outset of each data transmission session (offline/periodic tuning) EECS 247 Lecture 7: Filters 2006 H.K. Page 30

16 Example: Seventh Order Tunable LowPass OpAmpRC Filter EECS 247 Lecture 7: Filters 2006 H.K. Page 3 Digitally Assisted Filter Tuning Concept Assumptions: System allows a period of time for the filter to undergo tuning (e.g. for a wireless transceiver during idle periods) An AC (e.g. a sinusoid) signal can be generated onchip whose amplitude is a function of an onchip DC source AC signal generator outputs a sinusoid with peak voltage equal to the DC signal source AC Signal Power =/2 DC signal the input of the filter V P AC =V DC EECS 247 Lecture 7: Filters 2006 H.K. Page 32

17 Digitally Assisted Filter Tuning Concept V P AC =V DC AC a frequency on the rolloff of the desired filter frequency response (e.g. 3dB frequency) desired VAC = VDC sin( 2π f 3dB t) Provision can be made during the tuning cycle, the input of the filter is disconnected from the previous stage (e.g. mixer) and connected to:. DC source 2. AC source under the control of the DSP EECS 247 Lecture 7: Filters 2006 H.K. Page 33 Digitally Assisted Filter Tuning Concept V P AC =V DC EECS 247 Lecture 7: Filters 2006 H.K. Page 34

18 Practical Implementation of Frequency Tuning Filter Vref Vref CHOP 625kHz TUNE FREQ. CONT. Register Digital Signal Processor DSP66 40MHz A/D 4bit 0MHz Δ DC Measurement Δ 2Δ AC Measurement EECS 247 Lecture 7: Filters 2006 H.K. Page 35 Practical Implementation of Frequency Tuning AC Signal Generation Clock=high ClockB=low Δ Vout= Δ Clock ClockB Clock=low ClockB=high Δ Vout= Δ Δ 0 Δ Vout AC Measurement Δ 2Δ Vout EECS 247 Lecture 7: Filters 2006 H.K. Page 36

19 Practical Implementation of Frequency Tuning AC Measurement Δ 2Δ () 4 Vout t = Δ sin( t) π ω 2 () 4 Δ Vin t = sin( n t) π ω n n=,3,5,.. Input signal chosen to be a square wave due to ease of generation Filter input signal comprises a sinusoidal the fundamental frequency its odd harmonics: Key Point: The filter itself attenuates the unwanted odd harmonics Inaccuracy incurred by the harmonics negligible EECS 247 Lecture 7: Filters 2006 H.K. Page 37 Simplified Frequency Tuning Flowchart EECS 247 Lecture 7: Filters 2006 H.K. Page 38

20 Digitally Assisted Offset Compensation EECS 247 Lecture 7: Filters 2006 H.K. Page 39 Filter Tuning Prototype Diagram EECS 247 Lecture 7: Filters 2006 H.K. Page 40

21 EECS 247 Lecture 7: Filters 2006 H.K. Page 4 Chip Photo EECS 247 Lecture 7: Filters 2006 H.K. Page 42

22 Measured Tuning Characteristics EECS 247 Lecture 7: Filters 2006 H.K. Page 43 Offline Digitally Assisted Tuning Advantages: No reference signal feedthrough since tuning does not take place during data transmission (offline) Minimal additional hardware Small amount of programming Disadvantages: If acute temperature change during data transmission, filter may slip out of tune! Can add fine tuning cycles during dead periods of data transmission Ref: H. Khorramabadi, M. Tarsia and N.Woo, Baseband Filters for IS95 CDMA Receiver Applications Featuring Digital Automatic Frequency Tuning, 996 International Solid State Circuits Conference, pp EECS 247 Lecture 7: Filters 2006 H.K. Page 44

23 Summary: ContinuousTime Filter Frequency Tuning Trimming Expensive & does not account for temperature and supply etc variations Automatic frequency tuning Continuous tuning Master VCF used in tuning loop Tuning quite accurate Issue reference signal feedthrough to the filter output Master VCO used in tuning loop Design of reliable & stable VCO challenging Issue reference signal feedthrough Single integrator in negative feedback loop forces timeconstant to be a function of accurate clock frequency More flexibility in choice of reference frequency less feedthrough issues DC locking of a replica of the integrator to an external resistor DC offset issues & does not account for integrating capacitor variations Periodic digitally assisted tuning Requires digital capability minimal additional hardware Advantage of no reference signal feedthrough since tuning performed offline EECS 247 Lecture 7: Filters 2006 H.K. Page 45 Integrator Based HighPass Filters st Order Conversion of simple highpass RC filter to integratorbased type by using signal flowgraph technique V in C R Vo s RC = Vin s RC EECS 247 Lecture 7: Filters 2006 H.K. Page 46

24 st Order Integrator Based HighPass Filter C SGF V in V in R sc R V in Note: Addition of an integrator in the feedback path High pass frequency shaping EECS 247 Lecture 7: Filters 2006 H.K. Page 47 Addition of Integrator in Feedback Path Let us assume flat gain in forward path (a) Effect of addition of an integrator in the feedback path: V in a /sτ Vo a = Vin af Vo a sτ = = Vin a/ sτ sτ /a zero@dc & a intg ω= = aωo τ for alarge long time constant without need for largecorr Note: Addition of an integrator in the feedback path DC axω 0 intg This technique used for offset cancellation in systems where the low frequency content not important EECS 247 Lecture 7: Filters 2006 H.K. Page 48

25 Bandpass Filters Bandpass Filters: Q < 5 Combination of lowpass & highpass Lowpass H( jω) ω Highpass H( jω) ω H( jω) Q<5 ω H( jω) Q > 5 Direct implementation Q>5 ω EECS 247 Lecture 7: Filters 2006 H.K. Page 49 Direct Implementation NarrowBand Bandpass Filters Lowpass Freq. Mask Bandpass Freq. Mask s ω Ωs Ωs2 Ωs Ωc ΩB2 ΩB s = Q c ωc s = Design based on lowpass prototype for narrow band filters Same lowpass tables used EECS 247 Lecture 7: Filters 2006 H.K. Page 50

26 Lowpass to Bandpass Transformation Lowpass pole/zero (splane) Bandpass pole/zero (splane) Pole Zero From: Zverev, Handbook of filter synthesis, Wiley, 967 p.56. EECS 247 Lecture 7: Filters 2006 H.K. Page 5 Lowpass to Bandpass Transformation Table Lowpass filter structures & tables used to derive bandpass filters Q = Q filter LP BP BP Values C C L ' C = QC R ω Rr L = ' QC ω r r r From: Zverev, Handbook of filter synthesis, Wiley, 967 p.57. L L C L C ' ' C &L are normilzed LP values ' Rr = QL ω = ' QC R ω r r r EECS 247 Lecture 7: Filters 2006 H.K. Page 52

27 Lowpass to Bandpass Transformation Lowpass Bandpass Vin Rs L2 C3 RL Vin Rs L L2 L3 C3 RL Each capacitor replaced by parallel L& C Each inductor replaced by series L&C EECS 247 Lecture 7: Filters 2006 H.K. Page 53 Lowpass to Bandpass Transformation ' = Q R ω R L = ω ' Q 2 ' QL2 3 ' QC C = Rω ' R L2 = QL2 ω 0 ' C3 = QC3 Rω R L = ω 0 Vin Where: Rs L L2 L3 C3 RL C, L 2, C 3, normalized lowpass values Q bandpass filter quality factor & filter center frequency ω 0 EECS 247 Lecture 7: Filters 2006 H.K. Page 54

28 Signal Flowgraph 6 th Order Bandpass Filter Vin Rs L L2 L3 C3 RL Vin ut * * R R * Rs sl sc R * R sl2 sc * 2R * R sl3 sc * 3R * R RL Note each C & L in the original lowpass prototype replaced by a resonator Substituting the bandpass L,,.. by their normalized lowpass equivalent previous page The resulting SFG is: EECS 247 Lecture 7: Filters 2006 H.K. Page 55 Signal Flowgraph 6 th Order Bandpass Filter Vin ut * R Rs ' QC ω 0 s ω0 sqc ' ω0 ' sql2 ' QC 3 ω 0 ' QL2ω s 0 s ω 0 ' s QC3 * R RL Note the integrators have different time constants Ratio of time constants for each resonator ~/Q 2 typically, requires high component ratios poor matching Desirable to convert SFG so that all integrators have equal time constants for optimum matching. Scale nodes to obtain equal integrator time constant EECS 247 Lecture 7: Filters 2006 H.K. Page 56

29 Signal Flowgraph 6 th Order Bandpass Filter Vin ' QL 2 ' QL 2 ut ω ' 0 ω0 QC s s ω0 s ω0 s ω0 s ω0 s QC3 QC ' ' QC3 Note: Three resonators All integrator timeconstants are equal Let us try to build this bandpass filter using the simple C structure EECS 247 Lecture 7: Filters 2006 H.K. Page 57