Data Converters. Circuits for Data Converters. Overview. Sample-and-Hold. Diode bridge S&H

Transcription

1 Data Converters Overview Circuits for Data Converters Pietro Andreani Dept. of Electrical and Information Technology Lund University, weden ample-and-hold (&H) Diode bridge &H witched emitter follower BJT &H CMO &H CMO switch with low supply voltage Foldg amplifiers oltage-to-current converters Clock generation Data Converters Circuits for Data Converters ample-and-hold The &H uses two phases one for samplg, one for retag and makg the signal available to the followg circuits ( phase) The put buffer reduces the put load, and the output buffer avoids dischargg the samplg capacitance If the output is available the samplg period, we have a trackand- (T&H) Diode bridge &H chottky diodes very fast multi-ghz rates, medium resolution Durg samplg (trackg, actually), I 1 =I flows to the diode bridge, and is copied onto C s if the current from is small compared to I 1, we can use the small-signal lear circuit of the diode bridge as below if g m /C s is much larger than the signal frequency, (C s )= Durg, no current flows through the bridge, and C s stores the sampled signal a unity-ga buffer is then cascaded as usual g m g m + - g m C s Data Converters Circuits for Data Converters 3 Data Converters Circuits for Data Converters 4

2 Diode bridge non-idealities If I 1 > I current difference flows to the signal source samplg, but brgs I 1 towards triode voltage at B creases, D can enter conduction and corrupt the sampled signal it is important to have I 1 < I, which brgs node B down and does not cause any harm Other non-idealities Aperture distortion error the switchg-off time, caused by the derivative of the put signal a varyg put voltage delivers a current IC = 1 Cs d dt to C s a positive derivative makes the (total) current through D1 and D4 lower than the other pair, leadg to an asymmetrical bridge current non-lear error the switchg stant Track-mode distortion caused by the non-lear impedance of the put buffer drivg the bridge sce the non-lear voltage drop is proportional to the current, i.e. voltage derivative, this distortion creases with frequency Hold pedestal given by the (non-lear) charge jected by the diodes from on to off Hold feed-through caused by parasitic couplg between put and output (diodes are par. caps when off) Data Converters Circuits for Data Converters 5 Data Converters Circuits for Data Converters 6 Improved diode bridge The two extra diodes DA and DB are reverse-biased (by D and D4 conductg) Trackg, but are turned on by the two I x Hold, clampg B and A at ± D ( ±0.7) constant biasg of D1 and D results constant pedestal A and B are biased through the load impedance of the buffer, and the conductg diodes DA and DB have a low impedance of 1/g m R A and R B are much reduced decouplg of put from C much reduced feedthrough implified diode bridge / switched emitter follower Reduced requirements from power supply (0.7 saved); circuit on the right dimishes the put current load by the BJT ga Major drawback requires simultaneous switchg-off of both current sources to prevent spur jection to C (1ps delay with 1pF and 1mA 1m offset) Impossible to align very well the two clock signals elf synchronization required H put current reduction = + A H D = B H D Data Converters Circuits for Data Converters 7 Data Converters Circuits for Data Converters 8

3 Improved version Q E is an emitter follower samplg; when Φ H goes high and Φ low, I bias flows through R b and B is pulled down, but the emitter of Q E is kept high by C Q E is switched off The voltage on C is a shifted replica of the put usually not a problem, as the DC component is not terestg However, C BE Q E causes a pedestal that depends on the reversed BE uncontrolled BE, unpredictable pedestal Improved II Left: Q C replicates the held voltage and clamps B constant BE = constant pedestal; trackg Q C goes off and does not fluence operations Other source of pedestal: charge jection from base and collector of Q and Q H Q matched by dummy transistors Q D1 and Q D (right) driven by complementary phases; back-to-back diode D 1 and D between differential outputs match the non-lear C BE from Q E Data Converters Circuits for Data Converters 9 Data Converters Circuits for Data Converters 10 Input buffers Input buffers must be lear, fast, and capable of switchg quickly from ample to Hold and vice-versa Left: differential buffer with ga=-1 (if equal resistances and BJTs); very fast, but vertg DC level of one output may become close to its put small CB ; the off-state both outputs are pulled down CB can become forward biased collector current from the put, slowg down the next off-on transition Input buffers II Right: pseudo-differential, each buffer is an emitter follower with a shiftup at the output to compensate for the shift-down at the put; avoids the previous problem (but x current for the same f T ) if outputs are pulled down by current larger than I bias /, Q 3 ad Q 4 are switched off, and can quickly be switched on when the circuit goes back to trackg Data Converters Circuits for Data Converters 11 Data Converters Circuits for Data Converters 1

4 Complementary BJT &H If npn and pnp have comparable f T ( not usual!) circuit (a) implements the DC shift the previous slide; (b) push-pull implementation with equal npn (pnp) areas and I 1 =I, bias output current is I 1 ; transients, one output transistor reduces its BE, makg it available for the other; if one goes off, all current through the other transistor flows through the output (class B) (c): switched buffer Q 1 /Q H1 (Q /Q H ) divert I 1 (I ) from the emitter of Q 1 (Q 3 3) (CL clampg block; sources/sks I 1/I Hold) Features of BJT &H Good speed and learity, but limited dynamic range (junctions must be kept reverse-bias the off-state) consider the buffer/&h below: () ( nt) D t () t D ( nt) D Hold Q 4 is reverse; emitter of Q 4 follows the put via Q Maximum change of full-range se wave (at Nyquist) is ref / over the time T/: () t T REF This means that, after T/, may have dropped by ref / T Data Converters Circuits for Data Converters 13 Data Converters Circuits for Data Converters 14 Features of BJT &H II &H non-learity t () t D () ( nt) D ( nt) D Q 4 should never be forward-biased; on the other hand, Hold the C/B voltage of Q 4 is frozen to nt stants period nt D t D < 0 for nt< t< nt+ T () 0 () nt t < t > nt D D t= nt+ T D nt > nt > REF D D REF Thus, the put range is limited to < REF D D I Depends on the non-lear BE I E relation + I I E is the sum of I bias and the current to C s : In a pseudo-differential circuit, we have BE BE0 ln E T bias d IE Ibias+ C dt d 0 ln dt out+ = + BE T ; out = BE 0 T ln I Ibias + C Ibias C resultg the error on the differential output: bias Ibias + δout, d = T ln I bias d C dt d C dt I bias d dt Data Converters Circuits for Data Converters 15 Data Converters Circuits for Data Converters 16

5 &H non-learity II With an put = As( ω t), we obta Ibias + Aω C cos ω t δout, d = T ln I A ω C cos ω t bias odd function only odd harmonics, with amplitude proportional to put amplitude and frequency, and samplg capacitance To mimize bias current should be much larger than current to samplg capacitance Example: if C s = 4pF, f = 00MHz, A = 1 I Cs up to 5mA It can be shown that FDR=100dB requires I bias 8I Cs I bias = 40mA Noise emitter follower Important: this part is wrong the book Channel noise factor γ /3 for ideal MO, 1/ for ideal BJT In (d) below a large R series with switch trades reduced speed for reduced total noise power, which tends to the mimum limit of kt C for g R large (impact of ' and is mimized) m s r bb with Theven r ds r ds i n,0 4kTγ bias, 4kTγ γ vn, = + 4kTr g v m ' bb 4kTγ 4kTγ g + 4kTr + mbias, neq, ' bb v neq, 4kT =γ g m nc, kt γ + Rs = C 1+ g R m s Data Converters Circuits for Data Converters 17 Data Converters Circuits for Data Converters 18 CMO &H Time constant R C much lower than time allowed for chargg on If switched voltage has a large range use nmo and pmo parallel total resistance is ideally constant over a large voltage range Dummy M D clock feedthrough compensation (c) uses a simple source follower for maximizg speed (GHz range) bad learity, even with B= to avoid non-ler bulk effect (max. 70dB, compared to 100dB with BJT for the same current) C Clock feedthrough When MO from on to off, due to: 1) channel charge flowg to C, and ) clock charge jection through C gd. The fraction of Q ch jected to C depends on a) MO parameters, b) slope of the clock phase, c) boundary conditions on both sides of the switch Charge jection studied with simplified RC model for both gate and channel; numerical solutions as function of the switchg parameter B: B= od μ CWL ox αc Q ch L Ron = μc W ox od pseudo differential Q = C WL ch ox od d α = G dt Data Converters Circuits for Data Converters 19 Data Converters Circuits for Data Converters 0

6 Clock feedthrough II low B (i.e. fast switchg) 50% of channel charge flows to samplg capacitance large B depends on ratio between the two capacitances less predictable low B is more predictable preferred Feedthrough compensation Dummy M D jects all its channel charge to C should be approx. half as large as the switch this asymmetry reduces the effectiveness of cancellation to 70-80% In differential A/D differential cancellation of jection common-mode jection is suppressed by the differential topology, as (a) below effectiveness of 80-90% Another approach is to accept a constant jection = constant offset, as (b) not an issue if there is no signal at DC Data Converters Circuits for Data Converters 1 Data Converters Circuits for Data Converters Feedthrough compensation II (b) 3 opens slightly earlier than 1 (and 4 slightly earlier than ), and some of the channel charge flows to C ; however, node A switches between ground and virtual ground, and to the first order the channel charge 3 ( 4 ) is signal dependent DC offset only (canceled a differential implementation), no distortion The channel charge for 1 ( ) is signal dependent, but when 1 opens C is already floatg no signal-dependent charge redistribution on C! The C plate connected to ground determes the actual samplg socalled bottom-plate samplg technique Two-stage OTA as T&H Output of a two-stage OTA unity-ga feedback tracks the put the 1 st stage output is the put divided by the nd stage ga ( (a) below) Compensation capacitor OTA can be used as samplg capacitor as well C C becomes C (b) voltage at the end of Trackg is ( + ) 1 is (almost) zero if A large constant channel charge feedthrough is just an offset 1 st stage not used Hold offset auto-zerog is possible (connect as unity ga buffer, store offset onto a capacitance) ok for medium-speed if bufferg is needed; also, unity-ga configuration requires common-mode range to be the same as the put swg os 1 out 1 1+ AA 1 A nt AA nt nt = nt = 0 out 1 Data Converters Circuits for Data Converters 3 Data Converters Circuits for Data Converters 4

7 irtual ground CMO &H In general, virtual ground relieves the requirement of a large put common mode Charge-transferrg &H below: 1) ample C are charged between and put common mode CM,, C H between put and output common mode CM,out offset cancellation and common-mode shift if needed; ) Hold C are connected (anti) series and loop is closed charge transferred to C H, common-mode put is rejected; ga or attenuation possible irtual ground CMO &H II Flip-around topology more economic implementation: fewer caps, where C are first connected to the put, and then feedback however, only unity ga possible however, feedback factor is 1, while it was ½ the previous circuit flip-around more power efficient (lower open-loop ga-bandwidth-product required for the same samplg frequency) Neither scheme uses the op-amp samplg op-amp is openloop output to dd or ground, long recovery time differential output is shorted and connected to a common-mode voltage samplg Data Converters Circuits for Data Converters 5 Data Converters Circuits for Data Converters 6 Noise analysis of flip-around &H Each switch has on-resistance R on, and a thermal noise voltage (density) of v = 4kTR. The op-amp has an equivalent put noise voltage n on Every noise generator causes a colored noise spectrum across each capacitor; when the switches open, the sampled noise on the capacitor is given by the tegral of the colored spectrum Uncorrelated noise adds power-wise; Correlated adds signal-wise Durg ample, we have the situation (a) two switches series with C sce the tegrated noise is kt/c dependently of R, we have kt n, sample = C v nop, Noise analysis of flip-around &H II Hold a) the sampled noise on C is there also Hold (of course) Hold b) because of the virtual ground, the noise from the switch feedback is found at the output, until it rolls off because of the fite bandwidth of the op-amp A ω s 1 v = v = v = v 1+ A 1+ s 1+ s ω T nout, n n n ωt 4kTR v = = ktr ω on n, out n, out on T 1+ ( ωωt) T signal power sample sample Data Converters Circuits for Data Converters 7 Data Converters Circuits for Data Converters 8

8 Noise analysis of flip-around &H III Hold c) The same analysis applies to op-amp noise, v kt γ kt In total: n, out, flip = + ktronωt + ωt C Assumg ω T =, the total output noise power is CL kt kt γ kt n, out, flip = + Ron + C C C sample L L nop, 4kTγ = g m Noise analysis of flip-around &H I kt kt γ kt = + g R + n, out, flip m on C CL CL The samplg time constant R on C is typically lower than ω, i.e. CL RonC << g m 1 T which means that the second term is practice negligible n, out, flip kt γ kt + C C L sample Data Converters Circuits for Data Converters 9 Data Converters Circuits for Data Converters 30 Noise analysis of charge-transfer &H amplg charge on C is later transferred to C H if the charges on the two caps are correlated, lear (signal-wise) addition assumg C = C H, the transfer function of noise source #3 on both C and C H is 1 1 HC ( s) = H C s = = H 1+ 3R C s 1+ R 3C s on on Considerg that Hold the noise on C adds signal-wise to the noise on C H, and that this is also the output noise caused by source #3, we have out kt kt,#3 = 1+ 1 = 4 3C 3C Noise analysis of charge-transfer &H II amplg noise source #1 (and #) duces a noise voltage across both C and C H, and noise on C is subtracted from noise on C H Hold the relevant transfer function is therefore 1 H ( s) = H ( s) H ( s) = C = C H 1+ R 3C s ( if ) eq C C H on Considerg that the noise contributions from #1 and # add up power-wise, we obta kt kt out,#1 + = ( ) = 3C 3C Hold contributions from #4, #5, and op-amp #4 is found at the output with ga of -1, band-limited by β (-3dB frequency of feedback loop; β = 1) f T samplg samplg Data Converters Circuits for Data Converters 31 Data Converters Circuits for Data Converters 3

9 Noise analysis of charge-transfer &H III Noise source #5 appears directly at the output, also limited by β f T Noise from the op-amp is amplified x, and also limited by β f T Overall assumg the previous expressions for vnop, and ωt, and considerg that β = 1, the total noise is 4kT kt γ kt = + + ktr βω + 4 βω n, out, tot on T T 3C 3C kt kt γ kt kt γ kt = + Ron + + C C C C C L L L Therefore, for low noise large capacitances, low-noise op-amp hardly a surprise! Wrong picture the book! The reference noise transfer function is that of the R on C low-pass filter offset sensitive flip-around &H Example 5.3 samplg Data Converters Circuits for Data Converters 33 Data Converters Circuits for Data Converters 34 CMO pass gate nmo gate to dd, pmo to GND maximum conductance, given by G = β + β = = on n od, n p od, p od, n dd th, n od, p th, p If th, p, the pmo conductance goes to zero, as does that of the nmo for dd. If β th, n n = βp, the conductance when both MO are on is dependent of, and equal to (,, ) G = β on n dd th n th p CMO pass gate II This means that the conductance decreases with the supply voltage, and can become zero if + dd th, n th, p Usually, modern processes offer devices with low th however, this creases the cost of the product because of added process steps; it is also possible to use thick-oxide MO, which allows a (much) higher dd (double supply voltage required, extra process step) Data Converters Circuits for Data Converters 35 Data Converters Circuits for Data Converters 36

10 Flip-around &H witched op-amp technique low is low (close to ground) no problem drivg switch b At the output the whole output op-amp stage is switched off (i.e., the output impedance becomes very high) at nodes close to dd and ground no problem In this way, C can be connected to the put without havg to disconnect the OTA with a switch The only critical element is, whose channel must allocate the whole signal range Bootstrappg In prciple, one could generate high gate voltages with a charge pump, but this is (probably) not possible because of strict maximum voltage limitations today s CMO processes Bootstrappg ensure that the gate-to-source and gate-to-dra voltages are always below the allowed limits. The basic approach is shown below C B (charged to dd ) sustas the G of the samplg switch M through switches 3 and 4 on; off, OFF grounds the gate of M, and d 1 and d charge C B to dd. In reality, because of the par. cap. C p, the voltage at the gate of M becomes CB G = ( + dd) C + C p B Data Converters Circuits for Data Converters 37 Data Converters Circuits for Data Converters 38 G for M becomes Bootstrappg II C = B p G dd Cp + CB Cp + CB which is below dd and (almost) put dependent the on-conductance of M becomes C C B p Gon = β dd th ( ) Cp CB Cp C + + B G on is put-dependent maly through the body effect good for learity Direct-biasg of channel-substrate diodes should be avoided, and protection for dras undergog large voltage swgs should be provided C Bootstrappg III 1) 1 must be able to switch on/off dd ; ) 3 must susta the boosted voltage on; 3) 4 must operate under the same conditions as the ma switch M ; 4) OFF must be able to swg between the boosted voltage and zero A possible circuital solution is shown below (Abo and Gray, JC May 1999) Data Converters Circuits for Data Converters 39 Data Converters Circuits for Data Converters 40

11 Bootstrappg dd generation 1 is nmo control of its gate requires a voltage doubler M d1, M d, C 1, C, Inverter the gate of M 1 is at dd Φ off and at dd Φ on C B charges to dd Φ off ; M 1 is off Φ on Bootstrappg more features M po reduces the ds and gd experienced by M o Φ off Body of M 3 connected to source no latch-up hazard M i3 may take control of g,m3 when M i1 is cut off (i.e., when the put voltage (IN) is so high that (Φ on ) (IN)< th,m1 ) It is easier to implement M1 as an NMO than as a PMO, sce a PMO would start conductg Φ on as soon as IN + dd g,m1 (= dd ) > th,p None of the termal-to-termal device voltages exceeds dd for any device Works better with non-overlappg phases (if overlappg phases C 1 /C may discharge from dd ) Data Converters Circuits for Data Converters 41 Data Converters Circuits for Data Converters 4 oltage-to-current conversion (a): cascodg is often needed; can be simplified as (b), where pmo are used to avoid the body effect; however, the g m of the transistors should be much higher than 1/R; further, it is less lear, although the differential circuits cancels some non-learity. (c): g m is amplified by the op-amp ga (body effect reduced by the same amount) I = R out I = R out, diff + Example 5.4 ±0.5 put range, I B =1mA, od =400m determe R for FDR=85dB and FDR=95dB od od od IB The large-signal resistance is RT = R+ + = R+ ( I + I ) ( I I ) I I The differential put determes (implicitly) the output current as od IBIout Δ = RIout + IB Iout from which we obta I kδ + k Δ + k Δ + k Δ +, and k1δ 4k1 FDR = 1 3 k 3 3Δ k Δ 4 For the above FDR requirements, we need R=1.5kΩ and 18.5kΩ, respectively B out B out B out out Data Converters Circuits for Data Converters 43 Data Converters Circuits for Data Converters 44

12 Improved -I conversion Current through M 1 (M ) kept constant by feedback, together with avoidance of body effect + ( - ) is copied at the source of M 1 (M ) the signal current flows to M 3 (M 4 ), and copied to the output by M 5 (M 6 ) β A More precisely:, R +, where β A is the loop ga of the feedback: 1 β A 1 1 β A 3 Rout, A 3 Rout, A g + R+ g + g g + R m1 ds3 ds7 m1 Al loop ga of f3040db 30-40dB is possible learity it improvement sufficient i many applications Generation of clock phases Usually, at least two non-overlappg (to avoid charge leakage) phases are needed (overlappg may be needed e.g. to keep feedback phase transition) NOR based non-overlappg; NAND-based overlappg, need one more version for non-overlappg Non-overlap time three verter delays, R R out, A Data Converters Circuits for Data Converters 45 Data Converters Circuits for Data Converters 46