IRFR6215PbF IRFU6215PbF

Transcription

1 IRFR625PbF IRFU625PbF P-Channel 75 C Operating Temperature Surface Mount (IRFR625) Straight Lead (IRFU625) dvanced Process Technology Fast Switching Fully valanche Rated Lead-Free Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to.5 watts are possible in typical surface mount applications. D S G D- Pak IRFR625PbF HEXFET Power MOSFET V DSS -50V R DS(on) I D -3 S D G I- Pak IRFU625PbF G D S Gate Drain Source D Base part number Package Type Standard Pack Form Quantity Orderable Part Number IRFU625PbF I-Pak Tube 75 IRFU625PbF Tube 75 IRFR625PbF IRFR625PbF D-Pak Tape and Reel Left 3000 IRFR625TRLPbF bsolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V -0V -3 I T C = 00 C Continuous Drain Current, V -0V -9.0 I DM Pulsed Drain Current -44 P C = 25 C Maximum Power Dissipation 0 W Linear Derating Factor 0.7 W/ C V GS Gate-to-Source Voltage ± 20 V E S Single Pulse valanche Energy 30 mj I R valanche Current -6.6 E R Repetitive valanche Energy mj dv/dt Peak Diode Recovery dv/dt 5.0 V/ns T J Operating Junction and -55 to + 75 T STG Storage Temperature Range C Soldering Temperature, for 0 seconds (.6mm from case) 300 Thermal Resistance Symbol Parameter Typ. Max. Units R JC Junction-to-Case.4 R J Junction-to-mbient ( PCB Mount) 50 C/W R J Junction-to-mbient

2 Electrical T J = 25 C (unless otherwise specified) IRFR/U625PbF Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage -50 V V GS = 0V, I D = -250µ V (BR)DSS / T J Breakdown Voltage Temp. Coefficient V/ C Reference to 25 C, I D = -m R DS(on) Static Drain-to-Source On-Resistance V GS = -0V, I D = V GS = -0V, I D = -6.6 T J =50 C V GS(th) Gate Threshold Voltage V V DS = V GS, I D = -250µ gfs Forward Trans conductance 3.6 S V DS = -50V, I D = -6.6 I DSS Drain-to-Source Leakage Current -25 V µ DS = -50V, V GS = 0V -250 V DS = -20V,V GS = 0V,T J =50 C Gate-to-Source Forward Leakage -00 V I GSS n GS = -20V Gate-to-Source Reverse Leakage 00 V GS = 20V Q g Total Gate Charge 66 I D = -6.6 Q gs Gate-to-Source Charge 8. nc V DS = -20V Q gd Gate-to-Drain Charge 35 V GS = -0V, See Fig. 6 and 3 t d(on) Turn-On Delay Time 4 V DD = -75V t r Rise Time 36 I D = -6.6 ns t d(off) Turn-Off Delay Time 53 R G = 6.8 t f Fall Time 37 R D = 2 See Fig. 0 Between lead L D Internal Drain Inductance 4.5,6mm (0.25in.) nh from package L S Internal Source Inductance 7.5 and center of die contact C iss Input Capacitance 860 V GS = 0V C oss Output Capacitance 220 pf V DS = -25V C rss Reverse Transfer Capacitance 30 ƒ =.0MHz,See Fig. 5 Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions Continuous Source Current MOSFET symbol I S -3 (Body Diode) showing the Pulsed Source Current integral reverse I SM -44 (Body Diode) p-n junction diode. V SD Diode Forward Voltage -.6 V T J = 25 C,I S = -6.6,V GS = 0V t rr Reverse Recovery Time ns T J = 25 C,I F = -6.6 Q rr Reverse Recovery Charge.2.7 C di/dt = 00/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See Fig.) starting T J = 25 C, L = 4mH, R G = 25, I S = -6.6.(See Fig.2) I SD -6.6, di/dt -620/µs, V DD V (BR)DSS, T J 75 C Pulse width 300µs; duty cycle 2%. This is applied for I-PK, LS of D-PK is measured between lead and center of die contact. Uses IRF625 data and test conditions. When mounted on " square PCB (FR-4 or G-0 Material). For recommended footprint and soldering techniques refer to application note #N

3 -I D, Drain-to-Source Current () 00 0 VGS TOP - 5V - 0V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTTOM - 4.5V -4.5V 20µs PULSE WIDTH T c = 25 C V DS, Drain-to-Source Voltage (V) -I D, Drain-to-Source Current () 00 0 VGS TOP - 5V - 0V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTTOM - 4.5V -4.5V 20µs PULSE WIDTH T C = 75 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig. 2 Typical Output Characteristics -I, Drain-to-Source Current () D 00 0 T = 25 C J V, Gate-to-Source Voltage (V) GS T = 75 C J V DS = -50V 20µs PULSE WIDTH Fig. 3 Typical Transfer Characteristics R DS(on), Drain-to-Source On Resistance (Normalized) I = - D V GS = -0V T J, Junction Temperature ( C) Fig. 4 Normalized On-Resistance vs. Temperature

4 C, Capacitance (pf) V GS = 0V, f = MHz C iss = C gs + C gd, C ds SHORTED C rss = Cgd C oss = C ds + Cgd C iss C oss C rss V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage -V GS, Gate-to-Source Voltage (V) I D = -6.6 V DS = -20V V DS = -75V V DS = -30V FOR TEST CIRCUIT 0 SEE FIGURE Q G, Total Gate Charge (nc) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage -I SD, Reverse Drain Current () 00 0 T = 75 C J T = 25 C J V GS = 0V V SD, Source-to-Drain Voltage (V) Fig. 7 Typical Source-to-Drain Diode Forward Voltage -I D, Drain Current () 00 0 OPERTION IN THIS RE LIMITED BY RDS(on) 0µs 00µs ms T C = 25 C T J = 75 C Single Pulse 0ms V, Drain-to-Source Voltage (V) DS Fig 8. Maximum Safe Operating rea

5 4 2 -I D, Drain Current () Fig 0a. Switching Time Test Circuit T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 0b. Switching Time Waveforms 0 Thermal Response (Z ) thjc 0. D = SINGLE PULSE (THERML RESPONSE) 2. Peak T J = P DMx Z thjc + T C t, Rectangular Pulse Duration (sec) Notes:. Duty factor D = t / t 2 P DM t t 2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case

6 Fig 2a. Unclamped Inductive Test Circuit E S, Single Pulse valanche Energy (mj) 800 ID TOP BOTTOM Starting T J, Junction Temperature ( C) Fig 2c. Maximum valanche Energy vs. Drain Current Fig 2b. Unclamped Inductive Waveforms Fig 3a. Gate Charge Waveform Fig 3b. Gate Charge Test Circuit

7 Fig 4. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs

8 D-Pak (TO-252) Package Outline (Dimensions are shown in millimeters (inches)) D-Pak (TO-252) Part Marking Information EXMPLE: THIS IS N IRFR20 WITH SSEMBLY LOT CODE 234 SSEMBLED ON WW 6, 200 IN THE SSEMBLY LINE "" Note: "P" in assembly line position indicates "Lead-Free" "P" in assembly line position indicates "Lead-Free" qualification to the consumer-level INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFR PRT NUMBER DTE CODE YER = 200 WEEK 6 LINE OR INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFR PRT NUMBER DTE CODE P = DESIGNTES LED-FREE PRODUCT (OPTIONL) P = DESIGNTES LED-FREE PRODUCT QULIFIED TO THE CONSUMER LEVEL (OPTIONL) YER = 200 WEEK 6 = SSEMBLY SITE CODE Note: For the most current drawing please refer to Infineon s web site

9 I-Pak (TO-25) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-25) Part Marking Information EXMPLE: THIS IS N IRFU20 WITH SSEMBLY LOT CODE 5678 SSEMBLED ON WW 9, 200 IN THE SSEMBLY LINE "" Note: "P" in assembly line position indicates Lead-Free" INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU PRT NUMBER DTE CODE YER = 200 WEEK 9 LINE OR INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU PRT NUMBER DTE CODE P = DESIGNTES LED-FREE PRODUCT (OPTIONL) YER = 200 WEEK 9 = SSEMBLY SITE CODE Note: For the most current drawing please refer to Infineon s web site

10 D-Pak (TO-252) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. LL DIMENSIONS RE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EI-48 & EI INCH NOTES :. OUTLINE CONFORMS TO EI mm Note: For the most current drawing please refer to Infineon s web site

11 Qualification Information Qualification Level Moisture Sensitivity Level RoHS Compliant D-Pak Industrial (per JEDEC JESD47F) MSL I-Pak (per JEDEC J-STD-020D) Yes Qualification standards can be found at Infineon s web site pplicable version of JEDEC standard at the time of product release. Revision History Date 5/3/206 Updated datasheet with corporate template. dded disclaimer on last page. Comments Trademarks of Infineon Technologies G µhvic, µipm, µpfc, U ConvertIR, URIX, C66, CanPK, CIPOS, CIPURSE, CoolDP, CoolGaN, COOLiR, CoolMOS, CoolSET, CoolSiC, DVE, DI POL, DirectFET, DrBlade, EasyPIM, EconoBRIDGE, EconoDUL, EconoPCK, EconoPIM, EiceDRIVER, eupec, FCOS, GaNpowIR, HEXFET, HITFET, HybridPCK, imotion, IRM, ISOFCE, IsoPCK, LEDrivIR, LITIX, MIPQ, ModSTCK, my d, NovalithIC, OPTIG, Op MOS, ORIG, PowIRaudio, PowIRStage, PrimePCK, PrimeSTCK, PROFET, PRO SIL, RSIC, REL3, SmartLEWIS, SOLID FLSH, SPOC, StrongIRFET, SupIRBuck, TEMPFET, TRENCHSTOP, TriCore, UHVIC, XHP, XMC Trademarks updated November 205 Other Trademarks ll referenced product or service names and trademarks are the property of their respec ve owners. Edi on Published by Infineon Technologies G 8726 Munich, Germany 206 Infineon Technologies G. ll Rights Reserved. Do you have a ques on about this document? erratum@infineon.com Document reference ifx IMPORTNT NOTICE The informa on given in this document shall in no event be regarded as a guarantee of condi ons or characteris cs ( Beschaffenheitsgaran e ). With respect to any examples, hints or any typical values stated herein and/or any informa on regarding the applica on of the product, Infineon Technologies hereby disclaims any and all warran es and liabili es of any kind, including without limita on warran es of non infringement of intellectual property rights of any third party. In addi on, any informa on given in this document is subject to customer s compliance with its obliga ons stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applica ons. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended applica on and the completeness of the product informa on given in this document with respect to such applica on. For further informa on on the product, technology, delivery terms and condi ons and prices please contact your nearest Infineon Technologies office ( Please note that this product is not qualified according to the EC Q00 or EC Q0 documents of the utomo ve Electronics Council. WRNINGS Due to technical requirements products may contain dangerous substances. For informa on on the types in ques on please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a wri en document signed by authorized representa ves of Infineon Technologies, Infineon Technologies products may not be used in any applica ons where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury