Base Part Number Package Type Standard Pack Orderable Part Number

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1 V DSS R DS(on) typ. max. I D 300V 25.5m 32m 70A Applications High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits Benefits Improved Gate, Avalanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche SOA Enhanced body diode dv/dt and di/dt Capability Lead-Free G D S Gate Drain Source Base Part Number Package Type Standard Pack Orderable Part Number Form Quantity TO-247AC Tube 25 D TO-247AC D S G Absolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 70 I T C = 0 C Continuous Drain Current, V V 49 A I DM Pulsed Drain Current 280 P C = 25 C Maximum Power Dissipation 57 W Linear Derating Factor 3.4 W/ C V GS Gate-to-Source Voltage ± 20 V T J Operating Junction and T STG Storage Temperature Range -55 to + 75 Soldering Temperature, for seconds (.6mm from case) 300 C Mounting torque, 6-32 or M3 screw lbf in (.N m) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy 93 mj I AR Avalanche Current A See Fig. 4, 5, 22a, 22b E AR Repetitive Avalanche Energy mj Thermal Resistance Symbol Parameter Typ. Max. Units R JC Junction-to-Case 0.29 R CS Case-to-Sink, Flat Greased Surface 0.24 C/W R JA Junction-to-Ambient

2 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 300 V V GS = 0V, I D = 250µA V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.29 V/ C Reference to 25 C, I D = 5mA R DS(on) Static Drain-to-Source On-Resistance m V GS = V, I D = 42A V GS(th) Gate Threshold Voltage V V DS = V GS, I D = 250µA 20 V DS = 300V, V GS = 0V I DSS Drain-to-Source Leakage Current µa 250 V DS = 300V, V GS = 0V, Gate-to-Source Forward Leakage 0 V GS = 20V I GSS na Gate-to-Source Reverse Leakage -0 V GS = -20V R G Internal Gate Resistance. (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 80 S V DS = 50V, I D = 42A Q g Total Gate Charge I D = 42A Q gs Gate-to-Source Charge 60 V DS =50V nc Q gd Gate-to-Drain ("Miller") Charge 57 V GS = V Q sync Total Gate Charge Sync. (Q g - Q gd ) 23 I D = 42A, V DS =0V, V GS = V t d(on) Turn-On Delay Time 24 V DD = 95V t r Rise Time 6 I D = 42A ns t d(off) Turn-Off Delay Time 62 R G =.0 t f Fall Time 45 V GS = V C iss Input Capacitance 774 V GS = 0V C oss Output Capacitance 62 V DS = 50V C rss Reverse Transfer Capacitance 93 ƒ =.0 MHz, See Fig. 5 C oss eff. (ER) Effective Output Capacitance pf V 406 GS = 0V, V DS = 0V to 240V, (Energy Related) See Fig. C oss eff. (TR) Effective Output Capacitance (Time Related) 7 V GS = 0V, V DS = 0V to 240V Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 70 A (Body Diode) showing the G I SM Pulsed Source Current integral reverse 280 A S (Body Diode) p-n junction diode. V SD Diode Forward Voltage.3 V, I S = 42A, V GS = 0V dv/dt Peak Diode Recovery 7.3 V/ns, I S = 42A, V DS = 300V t rr Reverse Recovery Time 35 ns 454 V R = 255V, Q rr Reverse Recovery Charge 2520 I F = 42A nc di/dt = 0A/µs 3686 I RRM Reverse Recovery Current 6 A t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) Notes: Repetitive rating; pulse width limited by max. Junction temperature. Limited by T Jmax, starting, L =.2mH R G = 50, I AS = 42A, V GS =V. Part not recommended for use above this value. I SD 42A, di/dt 706A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 400µs; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while V DS is rising from 0 to 80% V DSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while V DS is rising from 0 to 80% V DSS. R is measured at T J approximately 90 C. R JC value shown is at time zero

3 C, Capacitance (pf) V GS, Gate-to-Source Voltage (V) I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 4.75V 0 VGS TOP 5V 2V V 8.0V 7.0V 6.0V 5.5V BOTTOM 4.75V 4.75V V 60µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics 60µs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics I D = 70A V GS = V T J = 75 C V DS = 50V 60µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 4. Normalized On-Resistance vs. Temperature 00 0 V GS = 0V, f = MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd C iss I D = 42A V DS = 240V V DS = 50V V DS = 60V C oss 8.0 C rss V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

4 Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) Drain-to-Source Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) OPERATION IN THIS AREA LIMITED BY R DS (on) 0 T J = 75 C 0 msec 0µsec msec V GS = 0V V SD, Source-to-Drain Voltage (V) 0. Tc = 25 C Tj = 75 C Single Pulse DC 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-to-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area Id = 5mA T C, Case Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Drain-to-Source Breakdown Voltage I D TOP A 20A BOTTOM 42A V DS, Drain-to-Source Voltage (V) Starting T J, Junction Temperature ( C) Fig. Typical Coss Stored Energy Fig 2. Maximum Avalanche Energy vs. Drain Current

5 E AR, Avalanche Energy (mj) D = Thermal Response ( Z thjc ) C/W 0.00 SINGLE PULSE ( THERMAL RESPONSE ) E-006 E t, Rectangular Pulse Duration (sec) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc + Tc Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Case Avalanche Current (A) 0 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 50 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25 C and Tstart = 50 C. 0..0E-06.0E-05.0E-04.0E-03.0E-02.0E-0 tav (sec) Fig 4. Typical Avalanche Current vs. Pulsewidth TOP Single Pulse BOTTOM.0% Duty Cycle I D = 42A Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN-05 at Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = tav f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) P D (ave) = /2 (.3 BV I av ) = T/ Z thjc I av = 2 T/ [.3 BV Z th ] E AS (AR) = P D (ave) t av

6 Q RR (nc) I RRM (A) Q RR (nc) V GS(th), Gate threshold Voltage (V) I RRM (A) I F = 28A V R = 255V I D = 250µA I D =.0mA I D =.0A T J, Temperature ( C ) di F /dt (A/µs) Fig. 6 Threshold Voltage vs. Temperature Fig. 7 Typical Recovery Current vs. di f /dt I F = 42A V R = 255V I F = 28A V R = 255V di F /dt (A/µs) di F /dt (A/µs) Fig 8. Typical Recovery Current vs. di f /dt Fig 9. Typical Stored Charge vs. di f /dt I F = 42A V R = 255V di F /dt (A/µs) Fig 20. Typical Stored Charge vs. di f /dt

7 Fig 2. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform

8 TO-247AC Package Outline Dimensions are shown in millimeters (inches) TO-247AC Part Marking Information Notes: This part marking information applies to devices produced after 02/26/200 EXAMPLE: THIS IS AN IRFPE30 WITH ASSEMBLY LOT CODE 5657 ASSEMBLED ON WW 35, 200 IN THE ASSEMBLY LINE "H" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFPE30 35H PART NUMBER DATE CODE YEAR = 200 WEEK 35 LINE H TO-247 package is not recommended for Surface Mount Application. Note: For the most current drawing please refer to website at

9 Qualification information Industrial Qualification level (per JEDEC JESD47F) Moisture Sensitivity Level TO-247AC N/A RoHS compliant Yes Applicable version of JEDEC standard at the time of product release. Revision History Date Comments Changed datasheet with Infineon logo-all pages 06/2/207 Corrected Package outline on page 8. Added disclaimer on last page. Published by Infineon Technologies AG 8726 München, Germany Infineon Technologies AG 205 All Rights Reserved. IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ( Beschaffenheitsgarantie ). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer s products and any use of the product of Infineon Technologies in customer s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury