Improved Synthesis Tool for Miller OTA Stage Using g m /I D Methodology

Transcription

1 Improved Synthesis Tool for Miller OTA Stage Using g m /I D Methodology THESIS Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University By Yueh-Ching Teng Graduate Program in Electrical and Computer Science The Ohio State University 2011 Master's Examination Committee: Prof. Mohammed Ismail, Adviser Prof. Steven B. Bibyk

2 Copyright by Yueh-Ching Teng 2011

3 ABSTRACT Modern analog integrated circuit design is mainly based on CMOS technology and is wildly used in different applications. Analog circuit designs are often complicated by the choice of design parameters such as channel length, channel width, drain current and biasing voltage that show up in every MOSFET in the circuits. In this thesis, we will focusing on an new interpretation of MOS modeling for analog design problems motivated by the traditional square law models. The design procedure for analog building blocks are based on g m /I d ratio of the device characterization data. The design problem and trade-offs can be synthesized by program functions then later verified by the circuit simulators. ii

4 To my parents, Ying-Mou Teng and Yu-Yeh Lin To Zoe Teng and Pei-Chun Hsieh iii

5 ACKNOWLEDGMENTS I would like to express my deep appreciation to my academic advisor Professor Mohammed Ismail for his guidance and patience. His kindness for letting me use Analog VLSI Lab. and being a teaching assistance for the mixed signal course were invaluable. I am extremely grateful to Professor Steven B. Bibyk for his generous, encouragement and being in my examination committee. Finally, I am grateful to my parents for their unconditional supports and faith they have in me. I would like to thank Pei-Chun Hsieh for providing me love and courage. iv

6 VITA September 03, Born - Chiayi, Taiwan June, B.S. Chung Yuan Christian University January, Graduate Teaching Assistant, the Ohio State University. FIELDS OF STUDY Major Field: Electrical and Computer Engineering v

7 TABLE OF CONTENTS Page Abstract Dedication Acknowledgments Vita List of Tables List of Figures ii iii iv v ix x Chapters: 1. Introduction Object of Thesis Organization of Thesis MOS Models for Design MOS Modeling Why more modeling Levels of abstraction Square law equation Short channel effects Modern MOSFET MOSFET Operating Region g m /I d Deisgn The Problem Design-Driven Small Signal Modeling vi

8 2.2.3 Transconductance Efficiency as Design Parameter Define V* How to choose V* Design Driven Device Characterization General Design Flow Signle Stage Deisgn Example Signle Stage Deisgn Flow Simulation Results Derive Design Specifications for Analog Building Blocks in Pipeline ADC Basic Pipeline ACD Structure Pipeline ADC Topology Pipeline ADC Operation ADC Design Specifications How to Choose the Value of Capacitors What Are the Specs? How to Choose Design Specifications for ADC OTA Design using G m /I d Method OTA Design Considerations Why Using Multi-Stage Amplifier? Design Two-Stage Amplifier Simple Two-Stage Amplifier Model Simplified AC Model using Capacitive Feedback Loop Gain for Two-Stage Amplifier Swing Settling Performance Noise Dynamic Range OTA Design Example Divide and Conquer Design Flow OTA Design Specs Simulation Results Conclusion Appendices: A vii

9 B Bibliography viii

10 LIST OF TABLES Table Page 2.1 Square law model vs. Short channel model V od vs. V ω p2 /ω c vs. P hasemargin Target Specifications for OTA Spectre Simulation Results Compare Matlab and Spectre Simulation Results ix

11 LIST OF FIGURES Figure Page 2.1 Output Resistance Mechanisms Velocity Saturation Modern MOSFET Reverse short channel effect Sub-Threshold Region Moderate Inversion Region The Problem SPICE Monkey Figure of Merit Figure of Merit for NMOS and PMOS Device Scaling f T and g m /I d trade-off f T and g m /I d design case Composite Figure of Merit Device Characterization x

12 2.16 SPICE Netlist for Device Characterization General Design Flow Simple Common Source Amplifier Circuit to Find Gate Biasing Voltage Under Constant Drain Current Common Source Stage Simulation Result Short Channel Device Design Solution Pipeline ADC Topology S/H Circuits Multiplying DAC (MDAC) MDAC Equivalent Model for Noise Calculation Single Stage Amplifier Two Stage OTA Simple Model for Two-Stage Amplifier AC Model using Capacitive Feedback Bode Plots of Two-Stage Amplifier Bode Plots of Two-Stage Amplifier After Narrowbanding Miller Compensation Pole Splitting Typical Gain and Phase Marge with Right Half Plane Zero Miller Compensation and Nulling Resistor Movement Diagram with Varying Nulling Resistor xi

13 4.12 Output Swing of Second Stage Vic=Voc=Vdd/ Low Frequency Gain and Large Signal Characteristic Step Response Closed Loop Amplifier Closed Loop Amplifier with Cload p/z K value vs. ε PM vs. ω p2 ω c Circuit for total integrated noise Dynamic Range Two Stage OTA General Design flow for an OTA Design Flow Used in the OTA Design Current Optimization Plot Input Step and Output vs. Time Settling Error vs. Time Loop Simulation Results Output Swing Results Noise Simulation Results xii

14 A.1 NMOS Transit Frequency A.2 PMOS Transit Frequency A.3 NMOS Intrinsic Gain A.4 PMOS Intrinsic Gain A.5 NMOS Composite FoM A.6 PMOS Composite FoM A.7 NMOS Current Density A.8 PMOS Current Density xiii

15 CHAPTER 1 INTRODUCTION With advancing technologies in modern semiconductor fabrication, device shrinking and supply voltage lowering posing challenges for circuit designers. Demand for accurate device models for design using deep submicron transistors is high [1]. Unlike digital circuit design, the level of abstraction in analog design can not be easily defined and synthesized by the softwares. Analog circuit design is challenging because the design process targets complex design specs [2]. The parameters of the transistor models used in analog design procedure are technology dependent, therefore, migrating any existing designs to the new processing technologies is slow and costly, every design must be customized and optimized separately. Nowadays, due to the shrinking supply voltage and other constraints, operating transistor near moderate or weak inversion regions is attractive for low power circuit design because it provides good trade-offs between speed and power [3]. The idea of g m /I d methodology is to based on a unified treatment of all the operation regions of MOSFET [3]. The g m /I d methodology is based on the ratio of transconductance over the drain current, a pure DC metrics that cover all the short channel effects [4, 3, 5]. The g m /I d metric is a universal characteristics for transistors in different processing technologies. The idea proposed in [1] is the combination of V design 1

16 method and g m /I d design methodology. Using V in the design process helps the designer using pre-existing analog design instincts of square law equations to design circuits in submicron technologies. The advantages of V method/modeling are: first, it is easy to learn, unlike g m /I d based on EKV modeling contains lots of equations that can not be transferred into design intuitions, the V modeling equations are mainly adopted from the square law equations. We can use the analogy of V dsat, V od, V ov to design circuits in submicron technologies, second, as shown in the thesis, the design procedure using g m /I d methodology can be realized through simple pre-simulated charts and Matlab scripts, therefore, it is easy to maintain, modify and customize for any design targets. 1.1 Object of Thesis The g m /I d methodology adopted in this thesis is to help us designing analog circuits in submicron technologies. The work is motivated by basic circuit design challenges: sizing up the transistors in modern processing technologies. By understanding basic characteristics of modern MOSFET, a simple and new design equation based on transconductance efficiency has been utilized in the design process. A complex design problem without close form solution can be iterated efficiently by using Matlab design script based on g m /Id method. 1.2 Organization of Thesis The following chapters of the thesis are organized as follows: a brief introduction to the modern MOSFET devices and short channel effects will be presented in Chapter2. A single transistor design example will be shown in the last part of Chapter 2. 2

17 In Chapter 3, we will discuss the basic building blocks of pipeline ADC and discuss how to derive design specs. In Chapter 4, we will apply the g m /I d design method on the two-stage OTA design. We will go trough various design considerations of the two-stage OTA and discuss the design trade-offs that been used in the design scripts. An design flow for two-stage OTA is shown in Chapter 4. The last part of Chapter 4 is a two-stage design example using Matlab script based on g m /I d method. Finally, Chapter 5 concludes the work in the thesis and discusses how to extend the usage of synthesis tool. 3

18 CHAPTER 2 MOS MODELS FOR DESIGN In this chapter, we will introduce modelings of the MOSFET and the general g m /I d design method. In the modeling section, we will discuss the reason to use new modelings and will briefly discuss the short channel effects and operation regions of the modern MOSFET. In the g m /I d design section, we will discuss gaps between design equations and the actual implementations. A design driven small signal modeling will be introduced. We will define a new design parameter called V* and discuss its role in the design process. Last but not least, we will introduce the design driven characterization of the modern MOSFET. A simple SPICE netlist was given and the simulation results could be found in the Appendix A. 2.1 MOS Modeling Why more modeling In digital circuit design, we can create some kind of margin, such as noise margin to simplified the design problems. As long as the circuit meet these constraints, circuits will behave well within the desired specs. That is, digital circuits have larger margin of errors to play with[5]. However, in analog circuit design, the circuit performance is usually rely on precise currents, voltages, etc [5]. In other words, analog 4

19 circuits are more sensitive to the transistor behaviors [5]. There is no way for a circuit designer to design analog circuits consider every details in physical devices and process parameters. A design engineer needs good abstraction and design intuitions. Therefore, models and simulators such as SPICE provide tools for thinking/verifying how circuits might behave during the design process. Doing experiments with simulator is much cheaper and easier to do than waiting for the IC tape-out results Levels of abstraction Derive proper abstraction for any circuit design is crucial. The best abstraction usually depends on what goals that the designer wants to achieve [5]. In digital circuit design problem such as digital delay, a MOS can be treated as a current source and a switch driving some load capacitors. We can create levels of abstraction based on digital functionality and digital performance [5]. However, creating analog abstraction is not as simple as digital abstraction. A modern MOSFET device described by BSIM models contains hundreds of parameters. Therefore, the analog characteristics described by models are too complicated to come up with simple abstractions for different analog circuits. Designing analog circuits based on measurement results is not possible, because there is no way for designers to remember every device I-V characteristics or physical details in the element during the design process Square law equation We can find the MOSFET square law equation in almost all microelectronics textbooks and analog circuit design books. The square law model is well known: I D,sat = 1 2 µ n C ox W L (V GS V th ) 2 (2.1) 5

20 the equation is based on charge and velocity assumptions. That is, the equation is base on Q v, charge times velocity. We assumed that the charge Q is only related to the V gs and the velocity v is only proportional to the V DS or µ E. The square law model is good approximation for long channel devices but totally inadequate to describe short channel behaviors [5, 6]. In short channel devices, due to velocity saturation, the velocity v is no longer proportional to µ E in all operation conditions. The charge Q is not only related to the V gs but is also a function of V DS, Q f(v gs, V DS ). It turns out that the velocity v is also a function of V gs, the vertical field. Square Law Model Short Channel Model Charge density only determined by vertical field Q f(v gs, V DS ) Drift velocity only set by lateral field velocity (verticalf ield, lateralf ield) Neglect diffusion currents V th varies with biasing Constant mobility Mobility reduction Table 2.1: Square law model vs. Short channel model [5] Short channel effects The Channel length modulation(cml) is one of the common second order approximations for MOSFET equation. The change of V DS cause the depletion region to vary and also change the effective channel length. If the change of channel length is small, then [5]: I 1 L δl(v DS ) 1 L (1 + δl(v DS) ) I ds = (1 + λv ds ) (2.2) L I ds0 One other observation from modern MOSFET device is that the V th goes down with the increasing of drain voltage. This is called the drain induced barrier lowering 6

21 (DIBL) effect. Because the drain region of the MOSFET imaged some charges on the channel, the gate node need less voltage to mirror the charge onto the channel, therefore, the effective V th is lower. It can be modeled as [5]: V th = V th0 ηv DS (2.3) The source and substrate of the MOSFET formed a P-N diode. At high electric field, some moving electrons may have enough energy(hot electrons) and will knock off electrons of Si lattice(impact ionization) to create currents and may eventually cause junction to break down(avalanche breakdown). This is called substrate current body effect(scbe) [5]. In other words, if we push drain voltage to high enough level, the drain current I D (not I DS ) and substrate current will suddenly increase. In modern devices the brake down voltage may not be high, usually between 1.5 2V [5]. If device operated in SCBE dominated region for a long time, the electrons may be trapped in the gate oxide and create defects and cause long term problem. From the analog circuit designers stand point, the SCBE may lower the output resistance so operating MOSFET in SCBE region is probably not a good choice. Fig. 2.1 shows the drain current and output resistance with different V DS. All effects are active simultaneously. Regions on the Fig. 2.1 indicate what effect dominate at that voltage range. The cure formed by circles is the drain current curve, output resistance curve is represented by squares. As we can see from the Fig. 2.1, the CML kicks in at relatively low fields, the DIBL dominates the high field and the SCBE happens at very high fields. From Fig. 2.1 we can clearly see that the output resistance is not constant after the MOSFET device left triode region. Instead of showing sharp transition between triode region and the saturation region that square law model predicted, Fig. 2.1 shows gradual transition for the output resistance curve 7

22 in different operation regions. One may suggest that in order to get more gain from the device, we need higher output resistance. Therefore, biasing the transistor in the region where the DIBL effect dominates seems to be a good idea. However, in most analog circuits design require some finite swing, biasing transistor in the DIBL region is not a good idea. In fact, most modern analog circuits design will biasing transistors in the CML region, the output resistance has big variation in the CML region. Figure 2.1: Output Resistance Mechanisms [5] Every material have speed limit, compared to GaAs and other materials, the speed limit of silicon (Si) is higher. In Fig. 2.2, we can see the drift velocity increase 8

23 linearly with the field in the beginning. As the filed gets higher, the carriers reach the speed limit and the I D (V GS -V th ) [5]. Another effect is vertical field mobility reduction. As the gate voltage increases, it not only change the charges on the channel but also affect how fast the channel charges can move, as a result, mobility depends on gate (vertical) field. The reason is that the electric filed pushes carriers toward the surface and the additional scattering lower the mobility of the charge [5]. Both velocity saturation and mobility reduction caused by vertical field will cause g m to vary, we will discuss it later. Figure 2.2: Velocity Saturation [5] 9

24 2.1.5 Modern MOSFET Fig. 2.3 shows cross section of modern MOS transistor. As we can see in Fig. 2.3 (a), the depth of source or drain junction is roughly equal to the length of the channel. The p-substrate is not uniformly doped, instead, it usually uses highly non-uniform doping called retrograde doping to reduce the body effect. The doping level near the channel is lower. The high doping level on the substrate makes the depletion region smaller, therefore, the device behaves better. The pocket (halo) implements under the drain and source area prevent drain and source depletion regions to connect together(punch trough). The increased doping level in the channel will cause output impedance to increase, junction capacitance will increase too. The gate oxide is very thin so that some of the electrons can tunnel directly trough the barrier, in many cases, it is not characterized by device models. If the circuit is sensitive to the gate input current, care must be taken to ensure that the gate leakage current will not degrade the circuit performance. 10

25 (a) A real transistor (b) Side view Figure 2.3: Modern MOSFET [5] In Fig. 2.4 (a), the transistor without halo doping has constant V th, as the channel length shrinks, two depletion regions eventually touch each other and cause the V th to go down. With halo doping, the V th is higher when channel length is shorter. This is 11

26 because the effective doping level in the channel is higher, larger V th means the device needs more voltage to image charges on the channel. For modern process with halo doping, if we want V th of the transistor to be lower, we can use transistor with longer channel length. As shown in Fig. 2.4 (b), the effective doping level in the channel of longer device is lower, therefore, the V th is lower than short channel devices. (a) Vth vs. Channel Length (b) Figure 2.4: Reverse short channel effect MOSFET Operating Region In real MOSFET operation, when V GS V th, the current does not go to zero, the device is in the sub-threshold region. The current in or near the sub-threshold region have exponential behavior as shown in Fig. 2.5, this is because the transistor itself forms a lateral BJT [5]. The sub-threshold or weak inversion current is dominate by the diffusion current. The current equation is similar to the BJT current equation: 12

27 I ds = W L I ds,0 e q(vgs V T ) nkt (1 e qv DS kt ), n > 1. (2.4) The base of this lateral BJT is controlled by the capacitive divider (see Fig. 2.5). The non-ideal factor of channel control n varies with bias, the typical number for n is about 1.5. Because tiny current driving large capacitor C gs, operate MOS device in weak inversion region is usually slow. However, some modern sub-micron processes, device can get relative high speed even operate in the weak inversion region, some low power circuits usually operate in the weak inversion region. In the weak inversion region, the V th matching is poor and the model is not well defined [5]. Figure 2.5: Sub-Threshold Region [5] 13

28 Operating transistors in strong inversion region cost more power, operating transistors in weak inversion region is slow. Why can t we operate devices in the region between weak and strong inversion regions? The region between weak and strong inversion regions is called moderate inversion region Fig In moderate inversion region, the current is composed of both drift and diffusion current. With the shrinking supply voltage, operating transistors in moderate region is attractive. However, no closed form equation exist for the moderate inversion region [5, 6]. Some models such as EKV uses weak and strong inversion equations to interpolate the moderate inversion region. The EKV models or BSIM models are too complicated to generate any close form equations for traditional hand analysis. From the designer s stand point, simple and effective hand analysis model to build design intuitions is necessary. Often times, question such as what channel width should I use to get certain g m is what a circuit designer cares most. Figure 2.6: Moderate Inversion Region [5] 14

29 2.2 g m /I d Deisgn The Problem Once we learn some neat circuit design theories and hand analysis techniques by taking courses and reading books. Given a set of design specifications, we may start our design by using simple hand analysis equations such as MOSFET square law equation. However, when we open the modern device models such as BSIM model, usually we can t find µ C ox, λ or any parameters that we are familiar with. The equations used in BSIM models or any other models are too complicated for hand analysis. From a designer s stand point we need something to gain useful intuitions, not a pile of equations. Furthermore, from previous sections we already know that there is a huge discrepancy between modern CMOS models and traditional square law equations. All these discrepancies posing a challenge for modern circuit designer, as shown in Fig Figure 2.7: The Problem [6] 15

30 The lack of good hand analysis models to design circuits forcing many designers to give up hand calculation/analysis, they iterate their design problem in the simulators until they somehow meet the design specs. Even the circuit meet the design targets, usually, the design is not guarantee to be optimal. In other words, this issue or challenge turns many designers into SPICE Monkey, Fig. 2.8 [6]. Normally, any design should be based on a systematic analysis and reasonable considerations, the simulator is just a calculator to check the design meet the specs or not. Figure 2.8: SPICE Monkey [6] Design-Driven Small Signal Modeling Circuit designer, unlike layout designer care mostly about W and L, they care about gain, bandwidth, noise, power, swing and etc [5]. We need something that tells us critical parameters such as g m, r o, C GS, C GD without resorting to the actual 16

31 equations in the modern device models. The idea is simple, we want to use circuit simulators as a lookup table to design circuits [5] [6]. The transconductance g m of MOSFET using square law model operating in the saturation region have the following equations: g m = µc ox W L g m = 2I ds W µc ox L 2µC ox W L I ds I ds (2.5a) (2.5b) g m = 1 2 µ n C ox W L (V GS V th ) (V gs V th ) (2.5c) g m = 2 I ds (V gs V th ) = 2 I ds V od (2.5d) The overdrive voltage V od or so called V dsat found in equation (2.5d) tells us two things, swing and transconductance efficiency. The lower the the V od, the higher the swing and more g m you get per unit current you spent. The MOSFET operating in the weak inversion region have I ds and g m : I ds W L I ds,0 e q(vgs V T ) nkt (2.6) g m = I DS V GS = W L I ds,0 e q(vgs V T ) nkt n kt q (2.7a) g m = I DS n kt q I DS (2.7b) 17

32 Therefore, if we simulated the MOSFET and plot g m vs. V GS. In the weak inversion region, g m is proportional to V GS following the exponential behavior described in (2.7b). In strong inversion region, g m is linearly proportional to the V GS as described in equation (2.5c). Comparing the transconductance g m of BJT and MOSFET, where g m BJT = I C Vt and g m F ET = 2I ds V od. We found that for the given I D, BJT has larger g m. In other words, for a given current, BJT has better transconductance efficiency. This is because V od is much larger than V t = kt q 26mV. What if we make V od close to V t? This will cause MOSFET to operate in the sub-threshold region and give out better g m efficiency. However, the operation speed in sub-threshold region is slow [5, 6] Transconductance Efficiency as Design Parameter We can always determine the gm I D ratio of any MOSFET. All we have to do is take the device and measure it s current. To get g m, we take the derivative of that drain current with respect to gate voltage. By using simulator, we can always determine the g m I D regardless of any short channel effect or complex modeling equations. As shown in Fig. 2.9, we can drive the simulator to give us the answer that we care about: gm I D. We can always plot g m vs. I D of MOSFET for any process technology because it is a pure DC metric. From Fig. 2.9 we known that before the moderate inversion or sub-threshold regions, the curve can be approximated by gm I D = 2 (V gs V th ) = 2 V od. The equation used in the sub-threshold region is gm I D = 1 n kt q by 1 n kt q similar to the BJT device. The ideal limit of gm I D The gm I D of MOSFET has extra n factor in 1 n kt q. Notice that the gm I D of BJT is gm I D = 1 kt q is limited 38V 1. of the sub-threshold region, therefore, the MOSFET can never reach the ideal 38V 1 value [5, 6]. The capacitive divider between the oxide and depletion region as shown in Fig. 2.5 reduce the effective 18

33 voltage at the channel of the MOSFET. One interesting discovery is that weak and moderate inversion regions are clearly the most efficient regions to operate in [5]. Form Fig. 2.10, we can see that the transconductance efficiency metric is mostly independent of device types. Figure 2.9: Figure of Merit Figure 2.10: Figure of Merit for NMOS and PMOS 19

34 2.2.4 Define V* After we see that the transconductance efficiency is a good design parameter, we can take equation (2.8a) and define a new parameter called V* [1, 5]. g m I D = 2 (V gs V th ) = 2 V od (2.8a) V 2I D g m g m I D = 2 V (2.8b) In square law model, V = V dsat = V ov = V od = V GS V th as we can see in equation (2.8a). We define V for modern MOSFET not because real device behave like square law device. Because it is simple and useful. It allows us to by analogy, think about how to pick V in the same way as to pick V od for the square law device. We already know that the real MOSFET do not obey square law equations [5]. So how does V work? For example, if we have a V = 200mV, that means we have gm I D = 10V 1. If we lower the V to 150mV, for the same current, we will have better transconductance efficiency and potentially higher swing, we will have larger device, therefore, more parasitic capacitance. V od Overdrive voltage V od Cannot be measured Complex equations Long channel device V = V od = V dsat I d V 2 Boundary between triode and sat. region r o is constant for V DS > V od V V = 2I D /g m Measure(simulate) easily Complex equations Short Channel device All interpretation of V are approximations Except V = 2I D g m (but V V dsat ) Table 2.2: V od vs. V [5] 20

35 Equation (2.9) shows figures of merits for device characterization [3, 6]. Since we can use the analogy between V and V od, these equations can help us determine the V value during the design process. From equation (2.9a) we know that we want high g m but low current. From equation (2.9b) we know that both smaller channel length and higher V lead to higher f T. We want large g m but small C gg. As we will see in Fig. 2.11, the f T goes up substantially with the processing technology. For a given 10GHz target, if we use 0.18µm device to replace the 0.25µm device, the V will goes down and the operation of the transistor is faster, we also scale down the current that we have to spend to get the same f T in 0.25µm device. Transconductance efficiency g m = 2 I D V od (2.9a) Intrinsic gain g m 2 g 0 λv od (2.9b) Transit frequency (f T ) How to choose V* g m 3 µv od C gg 2 L 2 (2.9c) By taking a MOSFET and connect its gate and drain and doing a voltage sweep in the simulator, we can plot V gs vs. f T and g m /I d, as shown in Fig Base on the plot we found that if we make V gs larger, generally we will get more g m (ignore vertical filed degradation) and the f T will go up. Equation (2.9c) predicted these trends. Therefore, if we want fast device, we want large V gs and device with smaller channel length (Fig. 2.11), but if we want a good current efficiency, we want low V gs (low current density region) to operate the device in moderate or weak inversion 21

36 region. To have higher transconductance efficiency, the V gs is lower and the device is larger, which means we have lower g m per unit capacitance, therefore, it is slower. All the trends described above can be seen in Fig Figure 2.11: Device Scaling [1] Figure 2.12: f T and g m /I d trade-off [1] 22

37 If we have a design target ω u = 1GHz, we can set our device f T = 5GHz. Now the question is how to find the g m /I d range. If we choose high g m /I d, the device f T will be lower than 5GHz. On the other hand, if we choose low g m /I d, we will meet the f T target but wasting current. We can see these trade-offs in Fig Figure 2.13: f T and g m /I d design case [1] Because many of the circuit performance parameters that we care about would be directly related to the g m /C gg or f T. We can plot composite figure of merits as f T times g m /I d vs. V od shown in Fig As we can see in the Fig. 2.14, the peak performance choice of the V would be somewhere around 100mV to 200mV in this plot. This magic V voltage range is a nice trade-off between the device f T and 23

38 the current efficiency. For many applications, the biasing point of MOSFETs would probably near or at the moderate inversion region, because in this region we get pretty good efficiency, moderate speed(f T ) and reasonable g m /I D. Notice that the magic voltage range is processing dependent and it is not truly optimal for any particular circuit design. For particular circuit design, if we want high g m /I D, we are going to increase the intrinsic capacitance of the device because the device is larger. Depending on the load capacitance, bandwidth and the intrinsic capacitance, every design is independent and the optimization of that design is based on different considerations, there is a certain ratio between the intrinsic capacitors of the transistor and the load capacitor to get the best result. However, given any processing technology, we can always make this composite figure of merit plots by using different channel lengths to see what would be the magic voltage range. We can use this voltage range in the beginning of the design process. Figure 2.14: Composite Figure of Merit [1] 24

39 2.2.6 Design Driven Device Characterization So far we known that we can always characterize the device by measuring the I d, g m in the simulator and choose V. Therefore, given a device modeling file (e.g BSIM), we can generate plots of parameters in equation (2.9) with respect to the g m /I d [6, 4]. By using simple configuration in Fig. 2.15, we can generate several useful plots for hand analysis. A simple SPICE netlist file shown in Fig demonstrate how to generate these useful plots. All plots generated by the SPICE netlist shown in Fig can be found in Appendix A. Figure 2.15: Device Characterization [6] 25

40 Figure 2.16: SPICE Netlist for Device Characterization General Design Flow Fig shows the general design flow by using pre-simulated plots and the g m /I d design method. Normally, our design target would require certain amount of gain, therefore, we should determine how much g m that we need first. After we found the range of g m that we needed, we can look at the intrinsic gain charts to find what channel length should be used. Based on the unity gain bandwidth or current budget 26

41 we can determine the g m /I d or the f t of the device. Once we determine the L, g m /I d or the f t of the device, we can determine device width based on the current density charts. The above description is just a general design flow using g m /I d design method. The design flow may be changed based on the actual constraints, circuit specs and many other things [4]. Figure 2.17: General Design Flow [4] 2.3 Signle Stage Deisgn Example In this section, we will design a simple common-source amplifier based on the design flow shown in Fig

42 2.3.1 Signle Stage Deisgn Flow Fig shown a simple common source amplifier configuration with C load on its output. The design targets are as follows: DC gain A v0 100 [V /V ] (2.10a) Unity Gain Frequency f u = 100MHz (2.10b) Load Capacitance C load = 5pF (2.10c) Figure 2.18: Simple Common Source Amplifier 28

43 First we need to determine the channel length based on the gain requirement. This can be achieved by looking at the intrinsic gain charts. Once we decided the channel length, we can calculate the g m by using g m 2 π f u C cload which is equal to 3.14mS. Based on the composite figure of merit plots, we choose V to be 200mV in the processing technology that we used here. Using equation (2.8b), we can found that the drain current is equal to 314µA. After we known the channel length, drain current and V value, we can determine the width of the transistor by using the current density charts. Based on the device characterization charts we can derived the device width to be µm Simulation Results After we determined all the parameters of common-mode stage, we can use circuit shown in Fig to find the gate biasing voltage for the V that we choose. The circuit in Fig allow us to sweep the drain voltage of the device under constant basing current. The ideal amplifier form a feedback loop to generate proper gate biasing voltage. 29

44 Figure 2.19: Circuit to Find Gate Biasing Voltage Under Constant Drain Current Fig shows that the simulation result meet both the unity gain frequency and the gain requirement. By using the pre-simulated device characterization charts and g m /I d design methodology, we can bridging the gap between hand analysis and the modern device models, as shown in Fig [6]. The discrepancies between g m /I d design results and the actual simulations results are usually on the oder of 10 20%, mostly due to the assumptions that we made during the g m /I d design procedure [6]. Even we found the discrepancies in the simulation results, we can always look back to our g m /I d derivations to track down the root causes [6]. The square law calculations are based on inappropriate parameters that do not exit or have no significant impacts in the modern spice models [6]. 30

45 Figure 2.20: Common Source Stage Simulation Result Figure 2.21: Short Channel Device Design Solution [6] 31

46 CHAPTER 3 DERIVE DESIGN SPECIFICATIONS FOR ANALOG BUILDING BLOCKS IN PIPELINE ADC In this Chapter, we would like to introduce the structure and basic operation of the pipeline ADC. After we understand the basic ideas of the pipeline ADC, in the second part of this chapter we will discuss how we come up with the basic designing specifications for the ADC. The design specifications used in Chapter 4 are based on the derivation introduced in Chapter Basic Pipeline ACD Structure Pipeline ADC Topology The pipeline ADCs are commonly used in modern electronic applications. The main feature of the pipeline ADC is that it trades accuracy with latency. Fig. 3.1 shows the basic pipeline ADC topology, the basic building blocks are: 32

47 1. Sample and Hold Circuit 2. Multiplying DAC (MDAC) Circuits Sample and Hold DAC Subtractor Gain Amplifier 3. Sub-ADC Circuits 4. Synchronization Circuits 5. Digital Error Correction Circuits Figure 3.1: Pipeline ADC Topology [7, 8] 33

48 3.1.2 Pipeline ADC Operation A generic pipeline ADC consists of N cascade stages, each resolve B-bit. In each stage, the analog input signal is first sampled and held then coarsely quantized by a sub-adc circuit to resolve B-bit. By using a DAC, the quantized value is then subtracted from the original input signal to generate the quantization error. The quantization error is amplified by an amplifier with gain 2 B 1. The resulting residue signal is then feed into the next stage for further quantization on the next clock cycle. The function of DAC, S/H, subtraction and the amplification can be combined into a single stage called multiplying DAC (MDAC) [9], as shown in Fig Because each stage has sample and hold function, each stage works concurrently to achieve high throughput. Fig. 3.3 and Fig. 3.2 show the circuit level implementations of the S/H and MDAC building blocks. Notice that the main building elements in each of these blocks are amplifiers or OTAs, therefore, how to design a good amplifier/ota become a key issue for any pipeline ADC design projects. Designing a high quality OTA is never an easy task, the performance of an ADC is mainly affected by these analog building blocks. As we will see later, the main focus of this thesis is to design these OTAs based on systematic design procedure and also decrease the designing times. 34

49 (a) Single Ended S/H (b) Fully Differential S/H Figure 3.2: S/H Circuits Figure 3.3: Multiplying DAC (MDAC) 35

50 3.2 ADC Design Specifications How to Choose the Value of Capacitors by: The value of the capacitors used in the MDAC and the S/H circuit are determined 1. Capacitor matching issue. 2. The errors created by switches in the network. 3. Noise consideration 4. Switch-capacitor common-mode feedback and other parasitic capacitance. Because we can use various circuit techniques (bottom plate sampling, bootstrap) to reduce the error caused by the non-ideal switches, the noise consideration determine the lower bound value of capacitors. After we estimate the capacitance values, we can add matching and common-mode into design considerations to adjust the final capacitance values that we are going to use in the actual design simulations. Two main sources contribute the total noise are: 1. KT/C noise 2. Noise from the amplifier We can use the equivalent model shown in Fig. 3.4 to determine the capacitance values. During the sampling phase, φ 1 and φ 1a are high, φ 2 are low.the KT/C noise and the input signals are sampled on the capacitors. 36

51 Figure 3.4: MDAC Equivalent Model for Noise Calculation The KT/C noise sampled on the capacitors can be expressed as: V 2 out K T C s + C f + C amp, C amp is the total input capacitance of the amplifier. (3.1) During the hold phase, the input signals and the noise charges sampled on the capacitor will be transferred to the C f, we can derive the output noise to be: V 2 out KT C s + C f + C amp C 2 f = KT 1, β is the feedback factor (3.2) C f β The input referred noise can be derived by dividing the total output noise with the square of the gain: 37

52 V 2 out G 2 in = V 2 = KT 1 2 C f β ( C f ) = KT (C s + C f + C amp ) C f + C s (C s + C f ) 2 (3.3) The noise of the amplifier will be determined by the circuit topology and actual implementation. The main noise source from the amplifier is generated by the drain current noise: i 2 n 4 KT ( 2 3 g m). We can calculate the total noise power from the amplifier by deriving the transfer function and doing the integration. We can derived the input referred noise variance to be: C f σ 2 = V out 2 G = KT 1 β 1 ( ) C Ltot C f + C s 2 where C Ltot = C Load + β (C s + C amp ), C Load is the loading of later stages (3.4) If we assumed the KT/C noise and the noise in the amplifier are uncorrelated, we can found the total input referred noise to be: σtotal,in 2 = 2 KT (C s + C f + C amp ) (C s + C f ) F KT C f ( ) β C Ltot C s + C f where F is noise factor depend on different circuit topology (3.5) 38

53 3.2.2 What Are the Specs? Suppose we want to design a 10-bit ADC with 50MS/s. We can derive the following design specs: Accuracy: ε wrost = (3.6a) Settling time: τ period = 1 50M = 20ns τ half,period = 10ns (3.6b) Dynamic Range: dB (3.6c) Close Loop Gain: 2 for 1.5-bit stage (3.6d) Worst Case V dd : 1.8 ± 10% V (3.6e) Power: as low as possible (3.6f) From equation (3.6a) we can known that the total error budget for the entire ADC. 1 The static error of the amplifier is equal to (DC Loop Gain) = 1 T 0. For a 0.1% accuracy in the first stage of the 10-bit ADC, we need loop gain T 0 > 60dB. Usually, we will make the loop gain larger to get more margins for other defects in the design. From equation (3.6b) we know that the amplifier has less than 10ns to settle within the desired ranges. Typically we want to settle the outputs to 1 8 LSB within 1 2 τ period [8]. The close loop gain in equation (3.6d) is determine by the gain of each stage that been used in the ADC. A large close loop gain is equivalent to the smaller feedback 39

54 factor, which means the loop gain must be large to achieve the desired static error. Usually, we started the design by choosing an OTA topologies that have sufficient gain and less noise [8]. In some circumstances such as high resolution ADC designs, we may use some circuit techniques to compensate the finite gain errors [4, 7] How to Choose Design Specifications for ADC For a 10-bit resolution pipeline ADC, we can derive the input referred noise of single stage as: C s = C f = C, C amp = 1 C, F = 6 :Two stage or folded cascode structures (3.7) 2 Vn 2 in,tot = KT C KT = 4.58 C 6 KT C (3.8) V 2 n in,adc 6 KT 2C + 6 KT C ( KT + ) 6 28 C (3.9) We choose the input referred noise to be a fraction of one LSB, in other words, we don t want the noise to degrade the SNDR of the ADC, here we choose 1 6LSB to be the design value. With full scale voltage V F S at the output to be equaled to 2 volts, we can calculate one LSB is equal to V LSB = 2/ mV. σ in = Vn 2 in,adc = 1 11 KT 6LSB 325µV. By using C = 325µV, we found that C 0.5pF. We can adjust the C value based on the matching and common-mode feedback considerations, we have to derive C Load value from the worst case loading during the circuit operations. Once we decided the C and the C load values, we can use them in the OTA design process. 40

55 CHAPTER 4 OTA DESIGN USING G M /I D METHOD In this chapter, we would like to introduce the basic design flow for the OTA used in pipeline ADC. First, detail design considerations of two stage miller OTA structure will be discussed. In the second part, we will transfer these design ideas into Matlab codes using g m /I d method introduced in the Chapter 2. We will use the circuit simulator to simulate the circuit based on Matlab simulation outputs and compare their simulation results. 4.1 OTA Design Considerations Why Using Multi-Stage Amplifier? A single stage amplifier have direct trade-off between swing and gain. A single stage amplifier can be simplified with two current sources as shown in The Fig. 4.1 [5]. The more V od we put across the current source, the more gain we get (higher output impedance). However, higher V od will reduce the effective swing and may degrade the dynamic range. 41

56 Figure 4.1: Single Stage Amplifier Design Two-Stage Amplifier Two-stage amplifier can decouple the direct trade-off between gain and swing. However, two-stage amplifier also have more poles associate with it so the stability of the amplifier is crucial. Figure. 4.2 shown a two-stage configuration, the first stage use telescopic structure to get more gain, the second stage use simple common source differential pair to increase the output swing. Therefore, the two stage structure can have high gain and high output ranges. With the telescopic structure, the gain is roughly equal to (g m r o ) 3. With 1.8V supply voltage, the common output swing can be as large as 2V p p (differential). 42

57 Figure 4.2: Two Stage OTA Simple Two-Stage Amplifier Model We can use simple two-stage amplifier shown in Fig. 4.3 [5] [4] to analyze the stability issue. As shown in Fig. 4.3, we can use simple R and C to express total resistance and capacitance at the output of each stage. From the simple R,C elements shown at the output, we know that there are at least two poles in this simple twostage model, therefore, at least 180 degrees phase shift. If the two-stage amplifier used in a loop configuration,the phase shift of 180 degrees from these two poles is theoretically stable, but in reality, any tiny parasitic capacitance in the loop could cause the phase shift to be larger than 180 degrees. 43

58 Figure 4.3: Simple Model for Two-Stage Amplifier Simplified AC Model using Capacitive Feedback By adding two capacitors to the circuit shown in Fig. 4.3, we can derive simplified model (Fig. 4.4) with feedback network for two-stage amplifier in Fig Equations (4.1a) and (4.1b) are equivalent output resistance at outputs. The β in equation (4.1c) is the feedback factor. The total equivalent output capacitance C Ltot at output of second stage is shown in (4.1d), total equivalent output capacitance at first stage is C 1. The equivalent input capacitance at the gate of the first stage is C x. Notice that the feedback factor β is not just a function of C s and C f, is is also a function of C x. The C gg values of input transistors will have large impact on the value of C x, therefore, proper sizing the input transistor is crucial get the desired β value. 44

59 R 1 (g m3 r o3 r o4 ) (g m2 r o2 r o1 ) (4.1a) R 2 r o5 r o6 (4.1b) β C f C f + C s + C x (4.1c) C Ltot C L + (1 β) C f + C db5 + C db6 (4.1d) Figure 4.4: AC Model using Capacitive Feedback 45

60 4.1.5 Loop Gain for Two-Stage Amplifier By using the return ratio theory in reference [10], we can derive loop transfer function of the circuit (Fig. 4.4) in equation (4.2). The loop transfer functions T (s) consists of feedback factor and the transfer functions of each stage a 1 (s) a 2 (s) = a(s). Notice that the resistance and capacitance at the output of each stage create two poles in the loop transfer function, therefore, the circuit is potentially unstable. If ω p1 and ω p2 are close to each other we will have small phase margin (Fig. 4.5). In order to make sure the circuit stable and obtain more phase margin, we could make the transfer function smaller. However, the gain accuracy requirement may require certain amount of T (s) value. The other simple solution is narrowbanding which makes the loop behave like first order system [10] [5]. Narrowbanding means we push either ω p1 or ω p2 happen at lower frequency to even lower frequency. Figure. 4.6 shown that by introducing the dominant pole in the system makes ω p2 to be much larger than ω p1. The phase margin of two-stage amplifier with extra dominant pole is determine by the ω p /ω c ratio, where ω p is the pole at the higher frequency and ω c is the unit gain frequency of loop transfer function. The phase margin in Fig. 4.6 is approximately equal to ω p2 /ω c. g m1 R 1 g m5 R 2 T (s) = β (1 s p 1 ) (1 s p 2 ) = β a 1(s)a 2 (s) = β a(s) (4.2a) p 1 = 1 1, p 2 = R 1 C 1 R 2 C Ltot (4.2b) 46

61 Figure 4.5: Bode Plots of Two-Stage Amplifier [4] Figure 4.6: Bode Plots of Two-Stage Amplifier After Narrowbanding [4] [5] 47

62 By introducing dominant pole to the system we can make the circuit stable. In reality, making one of the poles dominate will require large capacitance at the output of the stage. Also, the unit gain frequency would be pretty low. From the circuit designer s stand point, both of them are undesirable. We can make our circuit stable by purposely connect an additional capacitor between the input and output of the second stage, this is called Miller compensation [10, 5, 6, 4, 11]. After adding the Miller capacitor in the circuit (Fig. 4.7), two pole will split apart (pole splitting) and the system can be treated as first order system. Due to the Miller capacitor, the total capacitance (C 1 ) at the output of the first stage is gaining larger, therefore, the pole associate with it moves to the lower frequency. On the contrary, at high frequency, the Miller capacitor look like a low impedance path between the input and output of the second stage, as a result, the pole moves to higher frequency. Figure 4.8 shown the result of adding Miller capacitor. Figure 4.7: Miller Compensation 48

63 Figure 4.8: Pole Splitting [10] We can derive the transfer function of vo v x and the result is shown in equation (4.1.5). The result of transfer function is messy and complicated. In order to better analyzing and designing the circuit, we can use dominant pole approximation to simplify the results. a(s) = v o v x = (4.3) g m1 R 1 g m5 R 2 (1 s Cc g m5 ) 1 + s [(C Ltot + C c ) R 2 + (C 1 + C c ) R 1 + g m5 R 1 R 2 C c ] + s 2 R 1 R 2 (C 1 C Ltot + C c C Ltot + C c C 1 ) 49

64 We can use dominant pole approximation and assume p 2 p 1, we can write denominator D(s) and simplified it as [4]: D(s) = (1 s ) (1 s ) = 1 s ( ) + p 1 p 2 p 1 p 2 p 1 p 2 s2 (4.4a) s2 1 s ( 1 ) + p 1 p 1 p 2 (4.4b) Compared coefficients in equation (4.4) with equation (4.1.5), we can find identify p 1 and p 2. We can derive the following results [4]: a(s) a 0 (1 s z ) (1 s p 1 ) (1 s p 2 ) (4.5a) z = + g m5 C c (4.5b) 1 p 1 g m5 R 2 R 1 C c (4.5c) p 2 g m5 C 1 + C Ltot + C LtotC 1 C c (4.5d) As expected, equation (4.5) shows that the circuit have a right half plane zero. Usually, connection between input and output will create zero in the circuit. Here, the Miller compensation capacitor create a low impedance path between input and output at high frequency. The right half plane zero is problematic because it can reduce the phase margin if occurs before the cross over frequency. [10, 5, 4]. As shown in Fig. 4.9, the right half plane zero happens before the loop cross over frequency and flatten the gain, therefore, causing the circuit to be unstable. 50

65 Figure 4.9: Typical Gain and Phase Marge with Right Half Plane Zero [10] We may want to push the right half plane zero way higher than the cross over frequency, but what can we do? We can derive loop cross over frequency (ω c ) as gain (T 0 ) times bandwidth (ω p1 ) [4]: ω c ω p1 T 0 = β g m1r 1 g m5 R 2 g m5 R 2 R 1 C c = β g m1 C c (4.6a) ω z = g m5 C c (4.6b) 51

66 and we can derive the ratio between the right half plane zero and the loop cross over frequency to be: ω z ω c = 1 β g m1 g m5 (4.7) Since ω c is usually fixed and the g m1 is also fixed, the only thing we can play around is the g m5 [6]! Besides, pushing right half plane zero beyond crossover frequency requires g m5 > β g m1 is sometimes undesirable or impossible [4]. There are two commonly seen methods to mitigate the right half plane issue [6] [4]. The first one is to make the feedback path of C c unilateral. One practical realization is by adding source follower. However, using source follower the circuit will consume more power and degrade the swing. The other way to create unilateral path is to use cascode compensation. The drawbacks of cascode compensation is that the circuit became third order system and is difficult to design. The second method is to use nulling resistor as shown in Fig We can derive new transfer function : a(s) a 0 1 sc c ( 1 g m5 R z ) (1 s p 1 ) (1 s p 2 ) (1 s p 3 ) (4.8) 52

67 Figure 4.10: Miller Compensation and Nulling Resistor From equation (4.8), we know that by adding the nulling resistor, the transfer function now has three poles and a tuning knob to mitigate the zero. Fig shown the movement of zero position as the nulling resistor changes. We can move zero to infinity by making R z = 1/g m5. The nulling resistor can be realized using poly resistors or triode region transistors [4] [5]. Some may suggest that we can set the nulling resistor equal to cancel out the second pole. Theoretically the idea is good but not piratical in real design. Due to process variation, the nulling resistance may not cancel the desired pole and create the pole-zero doublet which will slow down the circuit transient response [5] [4]. 53

68 Figure 4.11: Movement Diagram with Varying Nulling Resistor [10] By using the Miller capacitor and the nulling resistor, we found that the loop crossover frequency depends on the C c and the non-dominant pole (high frequency) is set by the C Ltot [4]. We can summarized two design equations ω c β g m1 C c (4.9a) p 2 g m5 C 1 + C Ltot + C LtotC 1 C c (4.9b) that used in the Matlab design script. Notice that unlike the single stage amplifier, the increasing of the load capacitance will cause ω p2 move to lower frequency and hence reduces the phase margin [4] Swing The output swing of the second stage shown in Fig. 4.2 is critical to many design specs. Often time the circuit is noise limited, therefore, the circuit require large output swing range. For the common mode differential pair output stage, the available swing depends on both input and output common mode. That is, we can t decouple the 54

69 input common mode from output swing. Generally, we would choose folded cascode structure to avoid input common mode set the output swing. As shown in Fig. 4.12, the out put swing is limited by the active load or the input device. We found that [4]: V xx = V in,cm V gs,in = V ic (V ov + V th ) (4.10a) V o,max = V dd V minp (4.10b) V o,min = V xx V minn (4.10c) Assumed all devices operate in the edge of saturation region (long channel model),by adjusting the overdrive voltage and the common mode range, we can get maximum available output swing. In real life, we may not have the freedom to choose the common mode level because it is determined by the previous stage circuits [4]. 55

70 Figure 4.12: Output Swing of Second Stage [4] If both input and output common mode level are half of the supply voltage. By assuming the output swing limited by V minn, we found that the available output differential peak to peak swing is around 4 V th shown in Fig [4]. 56

71 Figure 4.13: Vic=Voc=Vdd/2 [4] Because usually the OTA is used in some feedback configuration, the large signal gain characteristic is what we really care about. By plotting the the large signal gain versus the output differential range, we can found the available swing at the output. Using A V 0 = V out / V in we can plot Fig The plot shows that for a given deviation at the input, how much deviation show on the output. 57

72 Figure 4.14: Low Frequency Gain and Large Signal Characteristic [5] We known from the early section, the transition between triode and saturation region is gradual, not abrupt. So how can we find the exact output swing of the circuit? We can plot the large signal characteristic and define output range as the full scale swing (differential) that causes no more than 30% variation drop in the gain [4]. The output range in Fig is roughly around 2V. 58

73 4.1.7 Settling Performance The settling performance is about how long it take to get the right result out of amplifier. For a switched capacitor OTA used in ADC, we care about two things: what is the residue error you can tolerate and how much time the output take to reach the final value. For a 10-bit ADC with 200Ms/s, the non-overlap clock period is 5ns each and we have half clock period(2.5ns) for our circuit to settle. As shown in Fig. 4.15, after putting in a step, the output will rise and settle. Because the step is relatively broadband, applying input with a step and check the output response is best way to approximate what really happen to the circuit [5]. Figure 4.15: Step Response [5] There are two types of settling errors, the static error and the dynamic error [5]. The static error is related to the finite gain of the amplifier and the mismatch of the 59

74 capacitors setting the feedback loop, no matter how long we wait, the static error is always there. If we tie the amplifier with capacitors shown in Fig. 4.16, we can derive: V o V i = c β A v0, T 0 = β A v0 (4.11a) β C f C f + C s + C x, feedback factor (4.11b) c = C s C f, closed loop gain (4.11c) where the equation (4.11a) can be approximated as: V o V i = c β A v0 c (1 1 β A v0 ) (4.12) From equation (4.12) we found that the loop gain T 0 will change the closed loop gain c and causing gain error. The input capacitance C x will cause the feedback factor to change. For a given error spec, if the feedback factor deviated from the ideal value too much, we will need large open loop gain. For example, if we want error to be smaller than 0.1% and the close loop gain c = 4 with C s = 500fF, C x = 500fF and C s = 2pF. The feedback factor β = 1/6, therefore, we need A V 0 grater than 6000 over the required output range! 60

75 Figure 4.16: Closed Loop Amplifier [5] Dynamic errors are set by many dynamic effects such as: finite bandwidth, feedforward zero, non-dominant pole, doublets and slewing [5]. Figure shows a closed loop amplifier with load capacitor. By using single time constant approximation, we can find useful linear settling results. 61

76 Figure 4.17: Closed Loop Amplifier with Cload [5] From Fig we can derive: V o V i = c 1 s C f G m 1 + s C load+(1 β) C f β G m (4.13) Notice that because the feedforward created from the feedback loop, it will create zero in settling response. If we apply input with a step V i,step = V step /s, the output step response is V o,step (s) = c 1+s/z 1+s/p V step/s. By taking inverse Laplace transform or using initial and final value theorems, we can derive time domain response at the output is [5]: V o,step (t) = V step c [1 (1 p z ) e p t ] (4.14) where V step c is the ideal response and 1 p/z is the initial error caused by feedforward. If p/z < 0 then there is extra swing that we need to spend as shown in Figure

77 Figure 4.18: p/z [5] For p/z 1, equation (4.14) can be rewritten as: V o,step (t) = V step c [1 e t/τ ], τ = 1/p (4.15) we can derive relative settling error to be: ε = e t/τ (4.16a) t s τ = lnε (4.16b) Equation (4.16b) is critical in the design process: if I have a fixed settling time t s, how many τ do I need to reach the settling error ε that I m interest in. In other words, I know how fast that the circuit is going to operate (t s ), I know what value 63

78 that I want to settle to (ε) then I can calculate the gain bandwidth that I need to hit the design target. The typical number to remember is 2.3τ per decade in the error specs. Notice that the total equivalent output capacitance (C leff ) on the output of Fig is usually set by how much noise we can tolerate in the circuit. Therefore, we can find the required g m value from equation (4.16b) [5]. If p/z is not negligible, equation (4.14) can be rearranged as: V o,step (t) V step c [1 (1 p z ) e t/τ ], τ = 1/p (4.17) and we can derive relative settling error to be: ε = (1 p z ) e t/τ (4.18a) t s τ = ln ( ε ) (4.18b) 1 + β C f /C leff Notice that from equation (4.18b), we can decrease the feedforward by decrease C f or increase C load. We know that to compensate the extra swing shown in Figure. 4.18, the circuit needs longer times to settle. However, the extra time that we need to spend is less than 1τ. Therefore, for dynamic error budget, we can calculate the design value by using 2.3τ per decade rule plus some margin (Appendix.B, line 13). The non-dominant pole in the circuit will impact the settling response. The non-dominant poles can be found in cascode, gain boosting and multistage amplifiers. Here we focus on the non-dominant poles in the multistage amplifier. The equation (4.9) can be used to calculate the ratio of crossover frequency and non-dominant pole frequency. We can define 64

79 ω p2 = K ω c (4.19) If K is smaller than 1, then both the phase margin and bandwidth of the loop are small. In order to lower the dynamic error settling time, we need certain amount of bandwidths and phase margin. Fig shows that the optimum value of K depends on the required ε dynamic (accuracy) [5] [4]. Generally, we don t want the K to be lower than 2. Figure 4.19: K value vs. ε [5] The phase margin can be defined as [4]: 65

80 P M tan 1 ( ω p2 ω c ) (4.20) As shown in Fig. 4.20, if the phase margin is too low, in other words, ω p2 ω c is too small, the overall output response will have ripples and peaking on it. Therefore, it will take more time to settle within the desired accuracy. In the multistage design example, the calculation of the K value can be found in [4]. Figure 4.20: PM vs. ω p2 ω c [10] Noise Fig shows the simplified equivalent circuit of two stage OTA used in noise calculation. The total integrated noise of the circuit shown in Fig is [12]: 66

81 ω p2 ω c P M Table 4.1: ω p2 /ω c vs. P hasemargin [4] V 2 o 1 β KT C c γ n (1 + γ p γ n g m4 g m1 ) + KT C Ltot [1 + γ n (1 + γ p γ n g m6 g m5 )] (4.21a) 1 β KT C c γ n (1 + γ p V 1 γ n V ) + KT [1 + γ n (1 + γ p V 5 4 C Ltot γ n V )] 6 (4.21b) From equation (4.21) we found that in order to reduce the total integrated noise, we want to choose larger V for the loading device. However, the desired swing requirement may force us to use lower V value. We also found that the larger the C c and C Ltot, the smaller the total integrated noise. It seems attractive to use larger capacitors to lower down the total noise. However, there are many limitations for integrated capacitors. Also, to drive larger capacitance means the circuit will consume more power and the transistor is bigger and slower(parasitics, transit frequency and etc). An integrated circuit usually face the trade-off between the design simulation (may or may not be real) and the actual realization (practical stand point). 67

82 Figure 4.21: Circuit for total integrated noise [4] Dynamic Range The available output swing of the second stage in OTA will determine the dynamic range of the circuit. The dynamic range at the output can be calculated using: DR = P signal,max = 0.5 V 2 P noise od,peak V 2 od (4.22) The dynamic range is simply the power of the signal at the output divide by the power of the noise at the output. The available swing of the common source differential pair used in the second stage is shown in Fig We can derive: 68

83 V o,peak 1 2 (V DD V odp V odn V odn ) (4.23a) V od,peak (V DD V odp V odn V odn ) (4.23b) V od,peak (V DD 2 (g m /I d ) P 2 (g m /I d ) N 2 (g m /I d ) N ) (4.23c) V od,peak (V DD V P V N V N ) (4.23d) For worst case corner, the supply voltage V DD =1.6V and the V od,peak =1V, the total budget for all three V would be 0.6V. If we assumed PMOS and NMOS using same V then each V is less than or equal to 200mV. In other words, the g m /I d for NMOS and PMOS should be 10. The above derivation are used during the Matlab simulation setup. In order to lower the noise on the output, the V* of the load device should be larger than the V of the gain device. However, using larger V will reduce the effective swings at the output. Therefore, the designer must choose these ratio or parameters carefully. 69

84 Figure 4.22: Dynamic Range [4] 4.2 OTA Design Example Divide and Conquer Design Flow After we know the design considerations in the previous section, we can start designing an OTA and keep those design equations in mind. Fig shows an two stage OTA used in the 10-bit pipeline ADC. As we can see from the Fig. 4.23, we need to choose sixteen channel lengths and widths plus the compensation capacitor value and the lead resistance value. Obviously, if we just put this circuit in the simulator without any initial calculation, it would be time consuming and painful for any designers to finish it on time. We could spend a lot of time on this and the 70

85 design still don t meet the specs. It is impossible to find a close form solution for such complex circuit design problem, therefore the design must be iterated several times[4]. We can use the basic characterization circuit introduced in Chaper 2 and plots similar charts shown in Appendix A to do our iteration. Instead of using human brain and paper pencil to iterate this problem. We can use the Excel, Matlab or any other software to iterate/design this circuit based on the g m /I d method introduced before. We can use Matlab function and treat these characterization charts as lookup table to help us iterate the circuit during the design process [5, 6, 4, 1, 3]. Figure 4.23: Two Stage OTA 71

86 Once we setup the tool for accessing the characterization charts, we need to analyze the design problem. We need to define primary variables and secondary variables. Primary variables are the tuning knobs for the design, any tiny changes in these variables will cause circuit performance to changed significantly. Secondary variables are those parameters which will not cause serious impact on the critical design trade-offs [4]. There are many possible ways to analyze the design targets and define primary variables. The general design flow for complex circuits such as an OTA is shown in Fig Figure 4.24: General Design flow for an OTA [4] 72

87 We choose C gg1 and C gg2 as main design variables and left others as secondary variables. The iteration loop is shown in Fig. 4.25, the equivalent Matlab codes and function can be found in the Appendix B and [4]. The main calling function has been adopted and modified from reference [4]. In order to create a loop for the design iteration, several lookup functions has been developed at the early stage of the design. The lookup functions and the Matlab design script are crucial in the loop iteration process because entire design method is based on the pre-simulated charts and the Matlab codes. Therefore, the correctness of the device characterization data is very important, we can only verify this through circuit simulators. Notice that even we extracted the wrong data during the device characterization process, the Matlab function may still generate reasonable results. 73

88 Figure 4.25: Design Flow Used in the OTA Design [4] OTA Design Specs The design specs for the OTA shown in Fig is based on 10-bit 50Ms/s pipeline ADC. The clock period is 20ns, therefore, the settling time t s is half of the clock period. The dynamic range requirement is 65dB. The supply voltage is 1.8V and we want to use minimum power. The load capacitance, sampling and feedback 74

89 capacitance is determined by the noise requirement. The static error is set to be 1 1 8LSB and the dynamic error is set to be around 16 LSB. Table 4.2: Target Specifications for OTA V dd C load A v,cl DR t s ε static ε dynamic C s = C f V od,p p Power 1.8V 2.5pF 1 65dB 10ns µV 125µV 0.5pF 2V min The design process started by choosing the channel length to meet the static error requirement. We can choose g m ratios to be equal at the beginning of the design process. For the secondary design parameter such as phase margin, we must choose carefully. If we choose high phase margin(e.g 75), the g m5, the total current consumption will be significantly larger than low phase margin design. However, if we choose the phase margin to be lower than 60, we will see ripples in the output step response and the OTA may not meet the error specs. After we determine the secondary design variables, we need to set the primary variables: C gg1 and C gg5. We may guess some numbers and try to iterate the problem. Since using minimum current is our design goal, one systematic way is to use loop function to find the lower current combinations as shown in Fig The capacitance ratios in the current optimization plot may not be the optimal choice, but it shows the tendency for the design problem. Usually, we want the C gg1 to be small because we want it s impact on feedback factor to be smaller. 75

90 Figure 4.26: Current Optimization Plot Simulation Results The circuit simulations results are summarized in Table.4.3. Device parameters are listed in Table.4.4, the discrepancies between the Matlab simulation results and the circuits simulator results are mainly caused by the assumptions made during the device characterizations. We can see that the circuit simulation basically meet all the 76

91 design specifications. To make the design more robust against processing variations, all we have to do is to change the design parameters in the Matlab scripts to get more margins. After we adjust the design parameters to obtain margins, the next step is to apply and refine the biasing network. We may choose some high swing and constant g m biasing networks. After we finished the biasing network design, the next step is to implement the common mode feedback network and refine the device fingers and multipliers. The last step is to check the design using different processing corners and adjust the design. Table 4.3: Spectre Simulation Results f c T 0 PM t s ε static DR V od,p p Power 203MHz 88.5dB ns 230µV dB 2V 4.9mA 77

92 Table 4.4: Compare Matlab and Spectre Simulation Results m1 (knob) m2 m3 Matlab Simulation Matlab Simulation Matlab Simulation C gg 17f f C dd f 2.012f f 3.3f f 16.88f g m µ 579µ µ µ µ µ f t GHz g m /I d I d 55.73µA 55.5µA 55.73µA 55.5µA 55.73µA 55.5µA I d /W W µm 5.2µm µm 8.84µm µm 51.1µm m4 m5 (knob) m6 Matlab Simulation Matlab Simulation Matlab Simulation C gg f f C dd f 8.7f f f 215f f g m µ µ 22.9m m m m f t GHz g m /I d I d 55.73µA 55.5µA 2.4mA 2.4mA 2.4mA 2.4mA I d /W W 25.91µm 25.9µm µm 81.7µm µm 423µm 78

93 Figure 4.27: Input Step and Output vs. Time Figure 4.28: Settling Error vs. Time 79

94 (a) Loop Phase (b) Loop Gain Figure 4.29: Loop Simulation Results (a) Large Signal Output Range (b) Normalized Output Range Figure 4.30: Output Swing Results 80

95 (a) Noise vs. Frequency (b) Total Integrated Noise Figure 4.31: Noise Simulation Results 81

96 CHAPTER 5 CONCLUSION A design methodology based on the g m /I d characterization was presented in this thesis. The proposed methodology was validated by the design of an two-stage OTA. The results showed excellent matching between the Matlab synthesis results and the circuit simulator results. The synthesis tool can reduce the re-design and optimization times of the critical analog building blocks, it can also be used to synthesis the design targets based on different processing corners. Designing times of complex analog circuits such as pipeline ADC can be significantly reduced because the synthesis tool can speed up the redesigning process. By changing the device characterization data and properly modify the design script, the designer could migrate analog circuits to different processing technologies in a short time. Last but not least, the synthesis tool could be used for educational purpose by adding more circuit configurations and more processing technologies. Instead of directly using circuit simulators to design the circuits and get get frustrated, students can quickly learn the circuit design trade-offs by using the synthesis scripts in the Matlab. 82

97 APPENDIX A T echnology Characterization Charts for T SMC 0.18µm P rocess Figure A.1: NMOS Transit Frequency 83

98 Figure A.2: PMOS Transit Frequency 84

99 Figure A.3: NMOS Intrinsic Gain Figure A.4: PMOS Intrinsic Gain 85

100 Figure A.5: NMOS Composite FoM Figure A.6: PMOS Composite FoM 86