Simucad Model Library Development Environment

Transcription

1 SPICE MODELS

2 Simucad Model Library Development Environment Example: Model Source Files: BSIM3 BSIM4 BSIMSOI HiSIM Gummel-Poon ModelLib Model Development Environment Compiler Model Object Files Linker Documentation Makefiles Scripts Custom Developed Dynamic Model Modularized Simulator Environment Simucad Functional Engine Family of Parsers Family of Solvers The Simucad Model Library Development Environment Includes Examples of Model Source Files for Popular SPICE Models Benefits of Simucad Model Library for Model Developers Convenient and fully independent environment for proprietary model development Sharable different model development teams can share model source code and binaries on commercial circuit simulators Testable easy to rapidly generate and run a complete set of regression tests for an independent and isolated model Traceable slconfig utility enables you to easily determine current model configuration that is also included in simulation output files Accuracy is preserved with no performance penalty

3 ModelLib Dynamically-Linked SPICE Models The Simucad SPICE Model Library (ModelLib) is a collection of all of the models delivered with Simcuad circuit simulators as a dynamically linked library. Individual models are distributed online as pre-compiled, pre-linked, pre-tested binary models that simulator users can easily download and install when a required model update is available. ModelLib enables you to enjoy simple, immediate and reliable access to the most up-to-date high performance SPICE models for: SmartSpice Analog Circuit Simulator SmartSpice-RF Harmonic Balance Based RF Simulator Harmony Analog/Mixed Signal Simulator Twister Full-Chip Hierarchical Analog Circuit Simulator Simulator Family of Solvers C-Language Model Development Environment Verilog-A Model Development Environment Family of Parsers Verilog-A Parser Parser Simulator Functional Engine S1 Direct Solver S2 Direct Solver S3 Direct Solver S4 Iterative Solver S5 Iterative Solver.C.C.h.h Makefile.O Linker.VA.VA.VA.VA VA Compiler.C C-compiler Interactive Debugger C-Interpreter Unix Windows.so or.dll.so or.dll.so or.dll.so or.dll.so or.dll.so or.dll.so or.dll.so or.dll.so or.dll Web-downloadable Simucad Supported Models Your Custom Model Simucad Model Library (ModelLIb) Open Source Verilog-A Model Library MOSFET MODELS ( NMOS and PMOS ) LEVEL = 1, 2, 3 LEVEL = 4, 13* Original Berkeley MOS model BSIM1 LEVEL = 8, 49*, 53* BSIM3v3.2 up to v3.3 LEVEL = 14, 54 LEVEL = 55 LEVEL = 40 BSIM4v4.0 up to v4.5.0 BSIM5 up to v5.0.0 (beta2) Philips MOS40 model LEVEL = 44 EKV Up to v2.6 LEVEL = 30, 31 LEVEL = 88 Philips MOS30 model HV MOS LEVEL = 11, 63* Philips MOS11 up tp v11.02 LEVEL = 9, 111 HiSIMv2.0 up to LEVEL = 20 LDMOS LEVEL = 56 PSP up to v102.1 TFT MODELS (NMOS AND PMOS) LEVEL = 35 MOS15 (a-si:h, RPI ) up to v2.0 LEVEL = 36 MOS16 (poly Si, RPI ) up to v2.0 FRAM MODELS LEVEL = 6 FRMC SOI MODELS (NMOS AND PMOS) LEVEL = 26 LEVEL = 27 LEVEL = 29 LEVEL = 32 LEVEL = 33 BJT MODELS LEVEL = 1 LEVEL = 2 LEVEL = 4 BSIM3SOIFDv2.1 (fully depleted) up to v2.1 BSIM3SOIDDv2.1 (dynamic depleted) up to v2.1 BSIM3SOIPDv2.2.3 (partially depleted) up to v2.2.3 CEA / LETI SOI (partially depleted) BSIM3SOIv3.2 to v4 Modified Gummel Poon model Quasi RC (quasi-saturation) model VBIC model LEVEL = 8 HICUM model up to v2.1 LEVEL= 500 MODELLA model LEVEL = 6, 503 MEXTRAM model LEVEL = 6, 504 MEXTRAM model up to v LEVEL = 20 HBT LEVEL = 20 UCSD-HBT model ( for HBT Technologies) UCSD-HBT model DIODE LEVEL = 1 LEVEL = 2 LEVEL = 3 LEVEL = 9 LEVEL = 500 LEVEL = 4 Standard junction diode model Fowler-Nordheim model Junction diode model that accounts for geometry Philips Juncap model Philips level 500 model RPI VCSEL (LAS1) Laser Diode model MESFET MODELS ( NMF and PMF ) LEVEL = 1 LEVEL = 2 LEVEL = 3 LEVEL = 4 Basic JFET model Statz model Curtice model Curtice-Ettenburg model LEVEL = 5 TriQuint models (versions 1, 2 & 3) LEVEL = 6 Parker-Skellern model JFET MODELS ( NJF and PJF ) LEVEL = 1 LEVEL = 2 Basic Sydney JFET model Modified Sydney JFET model * HSPICE compatibility Rev _11

4 Mextram GENERAL PURPOSE BIPOLAR MODEL Evolution of cut-off frequency with smoothing parameter AXI. New Level 504 Improvements From the older Mextram level 503, the new version has been upgraded regarding the following features : Mextram now includes self-heating, allowing device temperature to be dynamically computed. Self-heating calculations use only analytical derivatives, reducing simulation times (no need to compute numerical derivatives) Modeling of SiGe is now possible, using a dedicated set of parameters The set of parameters has been reviewed to make extraction procedure easier Two constant overlap capacitances have been added First and higher order derivatives have been smoothed, resulting in better accuracy and convergence ability Mature Bipolar Model Mextram provides several features that Gummel-Poon model lacks: Bias-dependent Early effect High injection effects Ohmic resistance of the epilayer Velocity saturation effects on the resistance of the epilayer Hard and quasi saturation (including Kirk effect) Split base-collector and base-emitter depletion capacitance Substrate effects and parasitic PNP Current crowding and conductivity modulation of the base resistance First order approximation of distributed high frequency effects in the intrinsic base (high frequency current crowding and excess-phase shift) Recombination in the base (for SiGe transistors) Early effect in the case of a graded bandgap (for SiGe transistors) Temperature scaling Self-Heating Simucad Implementation Mextram is compatible with VZERO and BYPASS options in order to achieve great speed performance Internal warnings and diagnostics provide valuable information to help finding convergence issues User-friendly parameters checking: user is kept aware of every clipped parameter Device internal variables (currents, conductances, charges...) can easily be accessed like any other parameter Mextram model is part of the SmartLib product-independent model library. It can be accessed within SmartSpice as level 503 or 504 Advanced Applications Mextram s second version is now well suited to high technology: Advanced processes such as double poly or even SiGe can be modeled Mextram can be used for high-voltage power applications Uncommon situations like simulating the NPN device in LDMOS technology behave correctly with Mextram Forward DC characteristics Rev _04

5 HICUM HIGH SPEED BIPOLAR MODEL DC characteristic Ic=f(Vce) Silvaco Implementation HICUM is compatible with VZERO option in order to achieve great simulation speed performance User-friendly parameters checking : user is kept aware of every clipped parameter Device internal variables (currents, conductances, charges...) can easily be accessed like any other parameter HICUM model is part of the SmartLib product-independent model library. It can be accessed within SmartSpice as level 6 SmartSpice implementation has been validated using the reference simulator, Device, developped by the creator of the model A Model Facing High-Speed Requirements The major effects taken into account by HICUM are : High-current effects Distributed high-frequency model for the external base-collector region Emitter periphery injection and associated charge storage Emitter current crowding Two- and three-dimensional collector current spreading Parasitic (bias dependent) capacitances between base-emitter and base-collector terminals Vertical non-quasi-static effects for transfer current and minority charge Temperature dependence and self-heating Weak avalanche breakdown at the base-collector junction Tunneling in the base-emitter junction Parasitic substrate transistor Bandgap differences, occuring in HBTs Lateral scalability Transconductance gm=dic/dvbe at variable bias Cutoff frequency vs. Bias conditions Advanced Applications HICUM provides the designers community with a powerful model, dedicated to high-speed applications. This model has been developed by Prof. M. Schroter at Ruhr-University, Germany. The operating region of the transistor has been developed with an emphasis on high current densities. Expressions used in the model include the effects encountered in short transistors, where emitter length is close to width Rev _03

6 Modella LATERAL PNP BIPOLAR MODEL Dedicated Lateral PNP Model The MODEL-LAteral model developed by Philips N.V. provides an accurate model dedicated to lateral PNP devices. This new model is based on a totally new approach, accounting for the complex bi-dimensional structure of lateral transistors. Modella allows the simulation of lateral devices using real physically based parameters, instead of using less accurate empirically-modified models, such as Gummel-Poon. With Modella, lateral PNP bipolars do not lack an accurate model anymore. Major Improvements Modella benefits from the following improvements with regard to the older Gummel-Poon model : More complex resistive network, using more internal nodes Separation of bottom and sidewall components, describing the 2D structure of the transistor No unphysical parameter (for example, current crowding is modeled, using only one parameter) Symmetry of the equivalent circuit, thanks to a splitted base resistance Equations derived from PNP formulations No iterative process used in equations, resulting in short simulation times Physically-Based Lateral Bipolar Model Modella accounts for the bi-dimensional structure of lateral PNP devices, modeling physical effects such as : Explicit modeling of inactive regions Excess-phase shift for current and storage charges Charge storage Temperature High-injection Built-in electric field in base region Bias-dependent Early effect Low-level non-ideal base currents Hard and quasi saturation Weak avalanche Current crowding and conductivity modulation of the base resistance Hot carrier effects in the collector epilayer Split base-collector depletion capacitance Influence of excess-phase on current gain Simucad Implementation Modella is compatible with VZERO and BYPASS options in order to achieve great speed performance Internal warnings and diagnostics provide valuable information to help finding convergence issues User-friendly parameters checking : user is kept aware of every clipped parameter Device internal variables (currents, conductances, charges...) can easily be accessed like any other parameter Modella model is part of the SmartLib product-independent model library. It can be accessed within SmartSpice as level 500 Ic vs. Vce characteristic Rev _03

7 VBIC GUMMEL-POON REPLACEMENT VBIC and Gummel-Poon VBIC allows accurate simulation, thanks to the following improvements : Improved Early effect modeling Physical separation of Ic and Ib Improved HBT modeling capability Improved depletion and diffusion capacitances Parasitic PNP Modified Kull quasi-saturation modeling Constant overlap capacitances Weak avalanche model Base-Emitter breakdown Improved temperature modeling Self-Heating Parasitic fixed (Oxide) capacitance modeling A Public Model Ic=f(Vce) with and without self-heating VBIC (Vertical Bipolar Inter-Company) has been developed in order to provide a replacement model to Gummel-Poon. It was designed by a group of IC and CAD industry representatives, willing to build a standard reference model. VBIC uses publicdomain code, that is available to the whole design community. The parameter set of VBIC allows the user to degrade the model to a more Gummel-Poon-like model. Simucad Implementation VBIC is compatible with VZERO option in order to achieve great simulation speed performance Device internal variables (currents, conductances, charges...) can easily be accessed like any other parameter VBIC model is part of the SmartLib product-independent model library. It can be accessed within SmartSpice as level 5 Self-heating uses only analytical expressions for derivatives, providing excellent speed and accuracy performance SmartSpice supports the latest version of VBIC, v1.2. Older version is also available through a selector The Goals of VBIC Gummel plot at different temperatures Overcome major deficiencies of Gummel-Poon Provide the complete source code, documentation, and extraction algorithms Maintain maximum compatibility with Gummel-Poon Be C continuous Have a defined keeper Include self-heating Be consistent between AC and transient Be independent of numerical algorithms Rev _03

8 BSIM3v3.2.4 INDUSTRY STANDARD SUB-0.13 MICRON MOSFET MODEL Simulation of ids, gds and gm demonstrates the model accuracy. Advanced MOSFET Model for Low-Voltage Low-Current Circuit Design As device complexity increases and feature sizes shrink into the deep sub-micron region, modern circuit designs require a robust, accurate and computationally efficient MOSFET model. BSIM3v3.2 has been specifically developed for deep sub-micron circuit designs current and future. IC companies and foundries are now rapidly moving past outdated SPICE models and adopting BSIM3v3.2 to meet the challenges of deep submicron designs. As a public domain standard model BSIM3v3.2 facilitates product design and technology exchanges among foundries and companies. Simucad Improvements BSIM3v3.2 MOSFET model is part of the SmartLib productindependent model library Simucad implementation is referred to as MOSFET model LEVEL 8 and is based on the most recent version (3.2.4) released by UC-Berkeley on December, It is also possible to invoke HSpice-compatible implementations by setting LEVEL=49 or 53 Further speed improvements can be gained through the VZERO option and the multi-threading capabilities The diagnostics option EXPERT is supported in BSIM3v3 to help the designer finding convergence problems Parasitic elements are described using SmartSpice Common Equations Usual MOS device variables like currents, conductances, charges and capacitances as well as BSIM3v3.2-specific internal variables can be saved, printed, plotted and /or measured A stress effect model can be used for process-induced stress, based on BSIM4 implementation Advanced Physics-Based Model Equations BSIM3v3.2 uniquely accounts for many of the physical effects present in today s deep sub-micron designs: Short and narrow-channel effects Non-uniform-doping effects Mobility reduction due to vertical field Bulk-charge effect Carrier velocity saturation Drain induced barrier lowering Channel length modulation Source/drain parasitic resistances The BSIM3v3.2 model equations account for all of the physical effects listed. Some of the significant benefits to analog designers include: Improved threshold voltage model to simulate both short and narrowchannel effects more accurately Improved Rds fit provides accuracy and efficiency Improved body bias dependence on narrow width, bulk charge effect, drain-induced barrier lowering effects and mobility Provides geometry dependence of channel length and width reduction factors Includes the drain bias dependence of subthreshold swing Accurate substrate current model Non-quasi static capacitance model As seen from this partial list of physical effects, the extreme complexity of the model requires a deep understanding of device physics for proper implementation. Simucad is the ONLY Spice vendor with this knowledge capable of offering the BSIM3v3.2 model in its full potential to the circuit design community! Unique Features Physical model based on process parameters The physical nature of BSIM3v3.2 provides scaleability and accuracy Single model provides good fit across all geometries and bias conditions with no binning requirements Suitable for both analog and digital applications Superb convergence achieved through continuous first and second derivatives - 6 -

9 BSIM3v3.2 Fundamental Improvement in SmartSpice Channel Length Effects on Impact Ionization Current Partitioning SmartSpice has the most accurate substrate current model available. New parameter (iirat) in the impact ionization current equation in SmartSpice takes into account channel length effects previously ignored in the Berkeley models. Correct Intrinsic Capacitance Model A single capacitance model equation supports effective channel lengths to below 0.2mm. The SmartSpice BSIM3v3.2 implementation eliminates negative capacitance and discontinuity problems found in the Berkeley model. A new parameter (intcap) enables users to choose either the original Berkeley model or Simucad s advanced implementation. Impact ionization currents in BSIM3v3.2 and v3.1 models. Improved Non-Quasi-Static Model A new SmartSpice non-quasi-static capacitance model (inqsmod=5) is physically consistent with the quasi-static model in all operating regions. To model MOSFET devices the nqsmod=5 model, rather than nqsmod=1, is recommended. Negative capacitances present in the Berkeley BSIM3v3 model (upper-left). Industry Leading Performance Simucad s BSIM3v3.2 implementation contains none of the discontinuities and non-physical behavior found in the original Berkeley model. This results in superior convergence and speed performance surpassing Level 8. S-Pisces simulation depicts no negative capacitances (upper-right). SmartSpice BSIM3v3 implementation displays correct model (lower-left). Further speed improvements can be gained through the multi-threading parallelization capabilities available in SmartSpice. TCAD-Based Implementation The advancements made in SmartSpice BSIM3v3.2 were made possibly only by utilizing the physics knowledge gained through years of development of the numerical device simulator S-Pisces. Simucad s BSIM3v3.2 is the only calibrated physical MOS model available! Total gate capacitance for NQSMOD=1 and 5 models only calibrated physical MOS model available! Rev

10 BSIM4v4 INDUSTRY STANDARD SUB-0.13 MICRON MOSFET MODEL Advanced Model Technology for Sub-0.13 Micron and RF High-Speed CMOS Design So far the physical MOSFET device model named BSIM3 version 3.2 and developed at UC Berkeley was considered as the industry standard model for deep sub-micron CMOS circuit design. It was rapidely adopted by IC companies and foundries for modeling devices down to 0.25 µm with a good accuracy. For device scale down to 0.10 µm, some physical mechanisms need to be better characterized. These mechanisms include for instance: The velocity overshoot Better modeling of weak inversion charges Gate bias dependent source and drain series resistance of LDD MOSFETs More physical investigation of narrow width effects Carrier quantization of MOSFET inversion layers Basically, BSIM4v4 is developed to explicitely address the following issues, for which BSIM3v3.2 was found lacking and inaccurate: Accurate modeling of sub-0.13 micron MOSFET devices Accuracy in RF, high-frequency analog and high-speed digital CMOS circuit simulation Model functionality (geometry-dependent parasitics model) As a public domain model BSIM4v4 (like BSIM3v3) is a mean of communication, simplifying technology sharing and improving productivity. BSIM4v4 Fundamental Improvements Over BSIM3v3 Like BSIM3v3, BSIM4v4 accounts for major physical effects: Short-Narrow channel effects on threshold voltage Non-uniform doping effects Mobility reduction due to vertical field Bulk charge effect Carrier velocity saturation Drain induced barrier lowering Channel length modulation Source/Drain parasitic resistances Substrate current induced body effect Quantum mechanic charge thickness model Unified flicker noise model BSIM4v4 has the following major improvements and additions over BSIM3v3.2: Accurate model of the intrinsic input resistance for both RF, high-frequency analog and high-speed digital applications Main DC characteristics Flexible substrate resistance network for RF modeling New accurate channel thermal noise model and noise partition model for the induced gate noise Non-quasi-static (NQS) model, consistent with the Rg-based RF model and consistent AC model, accounting for the NQS effect in both transconductances and capacitances Accurate gate direct tunneling model Comprehensive geometry-dependent parasitics model for various source/drain connections and multi-finger devices Improved model for steep vertical retrograde doping profiles Better model for pocket-implanted devices in Vth, bulk charge effect, and Rout equations Asymmetrical and bias-dependent source/drain resistance, either internal or external to the intrinsic MOSFET Acceptance of either the electrical or physical gate Oxide thickness as the model input at the user s choice in a physically accurate manner Quantum mechanical charge-layer-thickness model for both IV and CV More accurate mobility model for predictive modeling Gate-induced drain leakage (GIDL) current model, available in BSIM for the first time Improved unified flicker (1/f) noise model, smooth over all bias regions and accounting for the bulk charge effect Different diode IV and CV charateristics for source and drain junctions Junction diode breakdown with or without current limiting Gate dielectric constant defined as a model parameter - 8 -

11 Overview of Advanced Physics-Based Model Equations Basic Current-Voltage (IV) Model Including: A new threshold voltage model for pocket/retrograde technologies A Vgsteff formulation, re-derived to achieve better accuracy of gm, gm/id and gm 2/Id in the moderate inversion region A bulk charge model, with a new formulation of Abulk to consider its strong effect on doping profile Three mobility models, MOBMOD=0 and 1 coming from BSIM3v3.2 and the new MOBMOD=2 corresponding to a universal and more accurate model A new output resistance model, especially suitable for longchannel and pocket-implanted devices A Gate-Induced-Drain-Leakage (GIDL) current model, introduced in BSIM4 Two bias-dependent Rds model, corresponding to the BSIM3v3.2 model (internal) or to a new asymmetric model (external), which is more accurate for RF CMOS circuit simulation A quantum-mechanical inversion-layer thickness and high-k gate dielectrics model, accounted for in both IV and CV Trap-assisted tunneling and recombination current model to account for halo-doping technology Scalable stress effect model for process induced stress (STI). Device performance varies with active area geometry and location of the device in the active area RF and High-Speed Model Including: Four options for modeling electrode gate (bias-independent) and intrinsic input (bias-dependent) resistances, also working with multi-finger devices (fig.1) Two different switches to turn on and off the charge-deficit Non-Quasi-Static (NQS) model in transient and in AC analysis, both AC and transient NQS models based on the same fundamental physics A flexible built-in substrate resistance network accounting for the high frequency coupling through the substrate A gate dielectric tunneling current model accounting for a current flowing between gate and substrate and a current flowing between gate and channel region, which is partitioned between the source and the drain terminals Charge-Voltage (CV) Model BSIM4 provides three options for selecting intrinsic and overlap/ fringing capacitance models, all coming from BSIM3v3.2. The following table maps these models in BSIM4 to those in BSIM3v3.2: CAPMOD in Matched Intrinsic CAPMOD Matched Intrinsic Overlap/ fringing BSIM4 in BSIM3v3.2.2 CAPMOD in BSIM3v (default) 3 2 A complete plot of all intrinsic capacitances. Parasitics Modeling A comprehensive and versatile geometry-dependent parasitics model, providing series and multi-finger device layout modeling capabilities Three asymmetrical source/drain junction diode IV models: resistance-free and breakdown-free models coming from BSIM3v3.2 and a new breakdown-and-resistance model Noise Modeling Flicker noise: a simplified model and a unified physical model are available, both coming from BSIM3v3.2 with several improvements in the unified formulation Thermal noise: a long-channel model (coming from BSIM3v3.2) and a new holistic model are available Simucad Implementation BSIM4 MOSFET model is part of the SmartLib product-independent model library. It can be accessed within SmartSpice or UTMOST as level 14. Older versions, 0.0, 1.0, 2.0, 2.1 and 3.0, previously released by UC-Berkeley are also supported and are accessible using the model parameter VERSION The implementation is fully compatible with the most recent model description issued on March 4, 2004 by UC-Berkeley Further speed improvements can be gained through the VZERO option and the multi-threading capabilities The diagnostics option EXPERT is supported in BSIM4 to help the designer finding convergence problems Three selectable STI models : TSMC and Berkeley beta-version models are available in addition to the latest Berkeley model, using the STIMOD selector Rev _04

12 BSIM3SOI v3.2 INDUSTRY STANDARD SOI MODEL Advanced Physics-Based Model Equations BSIM3SOI version 3.2 was released on February An automatic module for the selection of the operation mode (FD or PD) based on the estimation of Vbs0 is proposed. It can be invoked setting the model parameter SOIMOD=3 Flicker noise and thermal noise models are compatible with BSIM4. In addition, gate tunneling induced shot noise and thermal noise due to gate electrode resistance are included BSIM3SOI version 3.1 model was released on February An ideal Full-Depletion (FD) module (SOIMOD=2) was provided for the strongly FD SOI devices (without the floating-body effect) The BSIM RF gate resistance model has been provided for SOI devices operated in the high frequency regime An enhanced binning capability has been added BSIM3SOI version 3.0 model was released on May A new full-depletion (FD) module has been included to provide better fitting to FD SOI devices. It can be invoked setting the model parameter SOIMOD=1 The partially-depletion (PD) module is by default identical to latest version of BSIM3SOI PD version (also supported in SmartSpice with previous versions setting LEVEL=29). It can be invoked setting the model parameter SOIMOD=0 New Gate-to-Channel current (Igc) and new Gate-to-S/D current (Igs and Igd) components were added in this version. By default, these currents are set to 0 in order to stay compatible with previous version but can be accounted setting the new selector IGCMOD to 1 BSIM3SOI version 3 model takes advantages of previous BSIM3SOI version 2 models for partially-depleted and fullydepleted SOI devices. In particular, the following features are supported: Real floating body simulation in both C-V and I-V. The body potential is determined by the balance of all the body current components Enhancements in the threshold voltage and bulk charge formulation of the high positive body bias regime An improved parasitic bipolar current model. This includes enhancements in the various diode leakage components, second order effects (high-level injection & early effect), diffusion charge equation and temperature dependence of the diode junction capacitance An improved impact ionization current model. The contribution from BJT current is also modeled by the parameter FBJTII Drain and Source partitions of gate-to-channel tunneling current. Body/Source Built-in potential lowering

13 Instance parameters (PDBCP, PSBCP, AGBCP, AEBCP, NBC) are provided to model the parasitics of devices with various bodycontact and isolation structures An external body node (the 6th node) and other improvements are introduced to facilitate the modeling of distributed body-resistance Self-heating: an external temperature node (the 7th node) is supported to facilitate the simulation of thermal coupling among neighboring devices A unique SOI low frequency noise model, including a new excess noise resulting from the floating body effect Width dependence of the body effect is modeled by parameters (K1, K1W1, K1W2) Improved history dependence of the body charges with two new parameters (FRBODY, DLCB) An instance parameter vbsusr is provided for users to set the transient initial condition of the body potential The new-charge thickness capacitance model introduced in BSIM3v3.2, CAPMOD=3, is included New gate-to-body tunneling current, a body halo sheet resistance, a minimum width for thermal resistance calculation and higher limit for exponential functions Better temperature dependence of the oxide tunneling current and an instance parameter FRBODY to account for the layoutdependent distributed body RC effect Advanced MOSFET Model for Low-Voltage Low-Current Circuit Design Thin-film Silicon-On-Insulator (SOI) technology is very interesting for low power and low voltage applications such as mobile and portable applications. Due to the growing interest for these applications, SOI becomes increasingly attractive for a future viable VLSI/CMOS technology. 51 stage ring oscillator. Gate-to-Drain/Source tunneling currents. Simucad Implementation BSIM3SOIv3 MOSFET model is part of the SmartLib productindependent model library. It can be accessed within SmartSpice or UTMOST III as level 33 The implementation is fully compatible with the more recent model description issued by Berkeley university Further speed improvements can be gained through the VZERO option and the multi-threading capabilities The diagnostics option EXPERT is supported in BSIM3SOIv3 to help the designer finding convergence problems Parasitic elements are described using SmartSpice Common Equations Usual MOS device variables like currents, conductances, charges and capacitances as well as BSIM3SOIv3-specific internal variables can be saved, printed, plotted and /or measured SmartSpice supports previous Berkeley BSIM3SOI models, BSIM3SOI PD v2.2.3 (Level=29),BSIM3SOI DD v2.1 (Level=27) and BSIM3SOI FD v2.1 (Level=26) Rev _04

14 HV MOS BSIM3-BASED HIGH VOLTAGE COMPANT MODEL Accurate SPICE Simulation of High Voltage Devices Without Using Macro-Models Simucad Level 88 provides a high-voltage compact model and is an extension of the industry standard BSIM3v3 model. This model is suitable to simulate Vertical Double-diffused (VDMOS) and any other high-voltage MOS devices. Features Asymmetric source and drain parasitics Bias dependency of source and drain parasitics Mobility reduction, including reduction due to drain voltage Dependency of velocity saturation on both gate and drain voltages Self-heating Quasi-saturation Velocity saturation Drain-Induced Barrier Lowering (DIBL) Static feedback Channel length modulation Weak avalanche current Level 88 improves on the widely adopted BSIM3v3 model to correctly describe, in a single compact model, the behavior of high voltage MOS transistors. Being a compact model, Level 88 provides much better convergence properties as compared to using a macro-model based approach. Simulation speed is not hampered by increased circuit size as internal macro-model nodes are not required. Schematic cross-section of a VDMOS device. Simucad Implementation Level 88 model is part of SmartLib product-independent models library. It can be accessed within SmartSpice as LEVEL 88 Level 88 is compatible with parallel architecture algorithms Level 88 is compatible with VZERO and BYPASS options in order to achieve greater speed performance Internal warnings and diagnostics provide valuable information to help identify convergence issues Usual MOS device variables like currents, conductances, charges and capacitances as well as MOS Level 88-specific internal variables can be saved, printed, plotted and/or measured

15 Benefits From Simucad Model Improvements Core parameter set is based on a final version of BSIM3v3.2 and ensures good continuity in the drain current equation and stable convergence Easy parameter extractions for modeling engineers who are familiar with BSIM3v3.2 Typical best model fit using BSIM3v3 (top) and Level 88 (bottom) showing bias dependency of velocity saturation. Typical best model fit using BSIM3v3 (top) and Level 88 (bottom) showing self-heating effects. Additional Model Parameters Added to the Core Model Parameter PRWD1 PRWD2 PRWS1 PRWS2 UD PCSE CCSE VSATG VSATB Description First order Vds dependence of external resistance Rds (Forward Mode) Second order Vds dependence of external resistance Rds (Forward Mode) First order Vds dependence of external resistance Rds (Reverse Mode) Second order Vds dependence of external resistance Rds (Reverse Mode) Vds dependence of mobility degradation Subthreshold slope and reverse short channel effect parameter Subthreshold slope and reverse short channel effect parameter Vgs dependence of VSAT Vbs dependence of VSAT Rev _02

16 LDMOS SURFACE POTENTIAL-BASED LDMOS COMPACT MODEL Accurate SPICE Simulation of LDMOS Devices Without Using Macro-Models Philips MOS20 provides a high-voltage-based LDMOS compact model that includes physical effects for both channel region and drift region under the gate. LDMOS model is suitable to simulate Lateral (LDMOS), Vertical Double-diffused (VDMOS) as well as Extendeddrain (EPMOS) devices. Features Surface potential based compact model Single equation set avoids discontinuities between operating regions (no smoothing functions required). Continuous derivatives for fast and accurate simulation convergence Mobility reduction Self-heating Quasi-saturation Velocity saturation Drain-Induced Barrier Lowering (DIBL) Static feedback Channel length modulation Weak avalanche current Philips MOS20 (SmartSpice LEVEL=20) accounts for the channel and drift regions, and computes the voltage at which the transition occurs internally. This provides much better convergence properties than using a macro-model based approach. Simulation speed is not hampered by increased circuit size as internal macro-model nodes are not required. Schematic cross-section of an LDMOS device. Simucad Implementation MOS20 model is part of SmartLib product-independent models library. It can be accessed within SmartSpice as LEVEL=20 MOS20 is compatible with parallel architecture algorithms Advanced analyses, such as Transient Noise (with/without Philips native equations) or RF are available MOS20 is compatible with VZERO and BYPASS options in order to achieve great speed performance Internal warnings and diagnostic provide valuable information to help find convergence issues Usual MOS device variables like currents, conductances, charges and capacitances as well as MOS20-specific internal variables can be saved, printed, plotted and/or measured

17 Benefits From All Philips and Simucad Model Improvements MOS20 model core is based on the SOI-LDMOS model developed at University of Southampton and is based on the computation of surface potential. This critical part of the model formulation was implemented with the experience of MOS11 model. This approach provides only one set of equations for the whole operating range of the model. There is no longer one equation for the subthreshold region, and another for near threshold region with a smoothing function to make a continuous transition between them. The single equation set used is continuous over all modes of operation. MOS20 has all the advantages of the Philips model development expertise, creating a robust model both in term of accuracy, convergence and speed. Typical capacitance vs. bias characteristics. Some example measured data is insert.* Self-heating and Quasi-saturation Device Behavior supported by MOS20. * A Surface-Potential-based High-Voltage Compact LDMOS Transistor Model, A.Aarts et al., IEEE Transactions On Electron Devices, Vol 52, No 5, May Rev _03

18 PSP SURFACE POTENTIAL-BASED MOSFET MODEL The PSP model is a compact MOSFET model which has been jointly developed by Philips Research and Penn State University. PSP is a surface-potential based MOS Model, containing all relevant physical effects (mobility reduction, velocity saturation, DIBL, gate current, lateral doping gradient effects, STI stress, etc.) necessary to model present-day and deepsubmicron bulk CMOS technologies. PSP model characteristics are: Suitable for digital, analog, and RF Suitable for modern and future deep sub-micron bulk CMOS technologies Physics-based Combine the best features of SP model (Penn State University) and MOS Model 11 (Philips) Number of parameters and simulation time comparable to MOS Model 11 Simple parameter extraction The source/drain junction model is an integrated part of the PSP model algorithms General Features of PSP Model Physical surface-potential-based formulation in both intrinsic and extrinsic model modules Physical and accurate description of the accumulation region Inclusion of all relevant small-geometry effects Modeling of the halo implant effects, including the output conductance degradation in long devices Coulomb scattering and non-universality in the mobility model Non-singular velocity-field relation enabling the modeling of RF distortions including intermodulation effects Quantum-mechanical corrections Correction for the polysilicon depletion effects GIDL/GISL model Surface-potential-based noise model including channel thermal noise, flicker noise, and channel-induced gate noise Advanced junction model including trap-assisted tunneling, band-to-band tunneling and avalanche breakdown Stress model ID ( A) 100 IG (A) V DS (V) Output characteristics of 0.36/0.09 µm MOS-FET; V gs varies between 0.5 and 1V, V sb =0. Circles represent measured data, solid lines correspond to PSP V GS (V) Gate tunneling current; V sb =0V, V ds =0.025, 0.042, 0.61and 1V

19 Model Highlights The PSP model is a symmetrical, surface-potential-based model, giving an accurate physical description of the transition from weak to strong inversion. The PSP model includes an accurate description of all physical effects important for modern and future CMOS technologies, such as: Mobility reduction Bias-dependent series resistance Velocity saturation Conductance effects (CLM, DIBL, etc.) Lateral doping gradient effect Mechanical stress related to STI Accurate and physical gate leakage current Gate-induced drain leakage Output conductance of halo-doped devices Gate depletion Quantum-mechanical effects bias-dependent overlap capacitances Most complete noise model, accurately accounting for velocity saturation and channel-induced gate noise In addition, PSP gives an accurate description of charges and currents and their first-order derivatives (transconductance, conductance, capacitances), but also of their higher-order derivatives. This yields to an accurate description of MOSFET distortion behaviour, making the PSP model well suited for digital, analog as well as RF circuit design. Simucad Implementation PSP model is part of SmartLib product-independent models library. It can be accessed within SmartSpice as LEVEL=1000 PSP is compatible with parallel architecture algorithms PSP is compatible with VZERO and BYPASS options in order to achieve greater speed performance Internal warnings and diagnostics provide valuable information to help identify convergence issues Usual MOS device variables like currents, conductances, charges and capacitances as well as MOS PSP-specific internal variables can be saved, printed, plotted and/or measured CGG (pf) ID (A) V GS (V) MOSFET transfer characteristics; V ds =25mV, V sb =0, V V GS (V) Measured (symbols) and modelled (lines) input capacitance C gg as a function of gate bias V gs for W/L=800µm/90nm n-channel MOSFET; V ds =0, V sb =0 Sig, Sid (A 2 /Hz) f 10GHz; V DS 1V S id S ig gds (A/V) V GS (V) Drain (S id ) and gate (S ig ) current noise spectral density versus gate-source bias for an L=90 nm n-channel device. Symbols denote measurements and lines represent modelled results using PSP V DS (V) Output conductance; V gs varies between 0.5 and 1V, V sb = 0 Reference: G.Gildenblat et alii. Introduction to PSP ; (presented at the 2005 Workshop on Compact modeling in Annaheim CA, May 2005; Technical Proceedings, pp ) Rev _02

20 EKV v2.6 LOW POWER MOSFET MODEL Advanced MOSFET Model for Low-Voltage Low-Current Circuit Design As supply voltage of circuits decreases to reduce power consumption, analog designs require a more physical, accurate and continuous compact MOS model. Based on a brand new approach to analytical MOSFET modeling, the Enz-Krummenacher-Vittoz (EKV) model is a good candidate model for low-power analog circuit simulation. As a public domain model, EKV MOSFET model allows product design and technology exchanges among foundries and companies. Requirements for a Good MOSFET Model for Analog Circuit Design and Simulation Provide reasonable I-V characteristic accuracy Give accurate values for all small-signal transconductances gm, gms, and output conductance gds and all capacitances (especially intrinsic capacitances). All of these should be continuous with respect to any terminal voltage Give good results even when the device operates in Non- Quasi-Static (NQS) mode Normalized transconductance: universal behavior, almost independent of technology Give accurate prediction of the white noise (and if possible 1/f noise) in any mode of operation Well behaved above over large bias ranges, including Vsb 0 in all regions of operations Well behaved over the temperature range of interest Well behaved over any combination of channel width and length for a given technology Have as few model parameters as possible which should be linked strongly to device structure and fabrication process variables to allow meaningful worst-case prediction Allow an efficient and as simple as possible parameter extraction methodology Predict matching Be computationally efficient EKV intrinsic capacitances calculated using charge conservation model Advanced Physics-Based Model Equations Basic geometrical and process related variables Non-uniform substrate doping profile Mobility reduction due to vertical field Carrier velocity saturation Short and narrow-channel effects including Reverse Short Channel Effect (RSCE) Impact Ionization current Short distance matching Improved thermal and flicker noise formulation Accuracy of weak inversion slope and substrate effect

21 Unique Features: Substrate node used as the voltage reference point allows the source and drain to be treated symmetrically (suitable for circuits with bi-directional MOS transistors) Pinch-off voltage Vp used to describe both the subthreshold region and the channel saturation characteristics (transitions from weak to strong inversion and from linear to saturation region are treated as the same physical phenomenon) Single expression principle model equation leads to the continuity of simulated currents, charges and related derivatives in all regions of operation Reduced set of core model parameters (only 10 parameters) Built-in charge-conservation and capacitance model Include AC first-order non-quasi-static model Simple temperature scaling Introduction of device series multiplier Simucad Implementation EKV MOSFET model is part of the SmartLib product-independent model library. It can be accessed within SmartSpice or UTMOST III as level 44 The implementation is fully compatible with the more recent model description issued in July 1998 by the EPFL Further speed improvements can be gained through the VZERO option and the multi-threading capabilities The diagnostics option Expert is supported in EKV to help the designer finding convergence problems Parasitic elements are described using SmartSpice Common Equations Usual MOS device variables such as currents, conductances, charges and capacitances as well as EKV-specific internal variables can be saved, printed, plotted and/or measured For more information on the EKV model please visit the EPFL website: Rev _03

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