A CMOS 79GHz PMCW Radar SoC

Transcription

1 A CMOS 79GHz PMCW Radar SoC Jan Craninckx PUBLIC

2 Abstract High-performance, small form factor millimeter-wave radar systems are key enablers for the new smart society. Application for automotive driver assistance and even autonomous cars is obvious, but also many other systems like vital signs monitoring, gesture recognition, self-guided drones, etc are envisioned. The research presented in this talk investigates the use of nanoscale CMOS technology for 79GHz radar systems, which will be a key enabler to open up this market for cost-effective high-volume production, and allows integration of large digital processing in the same System-on-Chip. A new concept of phase-modulated radar detection is also introduced that blends perfectly with the integration capabilities of CMOS. 2

3 Why mmwave radars?

4 mmwave Sensors are Extremely Robust noise & vibration snow & rain fog smoke dust lighting 4 heat dirt

5 mmwave Sensors are Fully Sealed and Invisibly Mounted discreet monitoring perfect aesthetics privacy 5

6 fixed mobile Radar evolution yesterday automotive today tomorrow 79 GHz radar SoC module 140 GHz antenna-on-chip systems? 6

7 Radar resolution (smaller is better) Speed (improves with higher carrier) voxel Range (improves with wider bandwidth) Angle (improves with larger antenna) 24 GHz 77 GHz 79 GHz 140 GHz 7

8 10+ radars per car High-resolution, 360 degree radar coverage Medium Range Radar (MRR) up to 80m Short Range Radar (SRR) up to 30m Long Range Radar (LRR) up to 250m 8

9 79 GHz PMCW Radar System

10 New Paradigm: mmwave CMOS Radar-on-Chip high resolution low power low cost small size leveraging standard foundry technology 10

11 Waveform Possibilities TX PA VCO/PLL Fast chirp FMCW RX LNA In-phase mixer HPF (spillover cancellation, R MIN limit) LPF (R MAX limit) ADC Fast-time FFT Range processing Slow-time FFT Doppler processing Range- Doppler map TX PA Bi-phase mod Binary sequence PMCW RX LNA I,Q Quadrature mixer LO LPF 11 ADC Correlator bank Range processing Slow-time FFT Doppler processing Range- Doppler map

12 High Level Comparison: PMCW vs FMCW PMCW FMCW Ambiguity function, sidelobes + Sensitivity to phase noise, flicker noise + ADC resolution + ADC speed / IF bandwidth +++ PSD + Sensitivity to interference +/- TX orthogonality for MIMO + Communications capability ++ Industrial acceptance +++ easier market entry / limited IP and patents ++ 12

13 PMCW Radar Operating Principle 2 Gbps T chip m T chip 79 GHz LO TX Distance D RX Target G * m 0 0 Target at D = (4 * T chip * C) / 2 C = speed of light in air G = Path Loss m Correlations (multiplication and integration) 13

14 ... and TX-to-RX Spillover 2 Gbps T chip m T chip 79 GHz LO TX RX TX-to-RX spillover Target S * m G * m 0 0 Spillover produces a large response for 0 delay Target at D = (4 * T chip * C) / 2 C = speed of light in air G = Path Loss m Correlations (multiplication and integration) 14

15 PMCW Radar System Radar IC Range Bins T 2 R c Time / Doppler Correlations with delayed version of the PN sequence Determine the delay T the position R Accumulations improve SNR FFTs determine the frequency shift of every range bin the speed of the object found on that range bin (Doppler) Also improves SNR 15

16 System design, Implementation and Verification System design Validation & demonstration IC design Module & antennas 16

17 System design Matlab chain 17

18 PMCW Radar-on-Chip: SISO Block Diagram S antennas RF T C Range resolution L C Ambiguous range M Ambiguous speed N Speed resolution PRN code ADCs High-speed digital front-end Reconfigurable digital baseband ADC PRN code Lc parallel paths Lc parallel Lc parallel Integrate Lc pulses Accumulate M pulses N-point DFT Lc parallel CFAR detection - DoA estimation - Tracking 18

19 S antennas analog front-end MIMO Block Diagram PRN code... PRN code ADCs High-speed digital front-end Reconfigurable digital baseband Lc parallel paths Lc parallel Lc parallel Lc parallel Lc parallel ADC Integrate Lc pulses Accumulate M pulses N-point DFT... ADC PRN code Lc parallel paths Integrate Lc pulses Accumulate M pulses Lc parallel MIMO array synthesis... Nrx*Ntx virtual MIMO antennas Lc parallel Beamforming Peak extraction - DoA estimation - Tracking PRN code N-point DFT 19

20 IC Module - Platform IC module platform integrated circuit containing the core functionality carrier containing antennas and mounted ICs, similar form factor to product 20 carrier containing module, components and connectors, complemented with computation component (PC, FPGA or similar) for demonstration

21 SOC Implementation

22 RX1QP RX1QM VDDBB18 RX1IM RX1IP VSSBB18 PLL_Fref VSSBB18 RX2IM VDDBB18 RX2QM RX2QP NoC SL NoC SL NOC_RST NOC_CLK NOC_DI TRX1_DO TRX2_DO TRX_CLKO TRX_SYNC TRX_DA RX2IP TRX4_DO TRX3_DO NOC_CE VDD18dig VSS18dig PHADAR 2x2 SoC Integrated mmwave PLL, TRX, ADCs, digital front end PLL 2 TX NOC_TE VSSRX1dig VDDRX1dig VDDTX1 TX1P DIG TX NoC MS TXTX DIG NoC SL NOC_DO / PLL_LOCK / PLL_Fdiv VSSRX2dig VDDRX2dig VDDTX2 TX2P TX1M ADC ADC TX2M VSSTX1 PLL RF VSSTX2 MIMO PN-LEAK CANC Δ VGA ADC PRF=1/(Tc*Lc) Fc=1/Tc=2Gbps Prog. Buffer VDDRX1 VSSRX1 VDDPLL RX RX RX RX NoC SL VDDRX2 VSSRX2 VDDLO 2 RX 2 GHz CK PRN Code Prog. Delay-Line VSSPLL NoC SL VSSLO PA LNA IQ MX ILO (x5) Int-N PLL LO-PLL ILO (x5) Modulator PA 2 GHz CK PRN Code Prog. Delay-Line MIMO PN-LEAK CANC VGA ADC Fc=1/Tc=2Gbps PRF=1/(Tc*Lc) Prog. Buffer Δ 2 I/Q ADC 2 Digital Correlator/Accumulator 22

23 LO Architecture: 5x ILO A 5th Subharmonic, Inverter-Based Injection Locked Oscillator Avoid frequency distribution at 79GHz across the IC Frequency multiplication Harmonic based multipliers Wide functional range, but less damping at ω 0 /N Injection locked oscillators Oscillator must be locked 3X or 5X? 3X locks easier, but GHz 5X is only 15.8GHz PLL and frequency distribution Needs lots of 5th order distortion generation Inverters! 23

24 Inverter Based ILO for 79GHz VDD A=450mV VDD ω 0 =15.8GHz * 2π Tuned amplifier A@ω 0 Vb i out e 0 M1 Classical approach A@ω 0 A/3@3ω 0 A/5@5ω Vb Inv based approach i out e 0 M1 A>1V for i out =0.82mA, while VDD in 28nm is 0.9V Also reliability is worse 24 Input i out (ma) Θ( ) ω ω 0,3ω ω 0,3ω 0,5ω Up to 15ω

25 Implementation Inverter chain Oscillator core 20K Q ind =15 Q var =8.5~ VCO+ VCO- [3:0] L mos =35nm 12um 9um 16um 13.5um V inj+ V DC V DC2 M1 M2 M1:M2=5:1 V DC V inj- W P /W N ratio is adjusted to have duty cycle. V DC2 used to enhance self resonance Slice 25

26 Phase Noise (dbc/hz) Oscillation Frequency (GHz) Input Power (dbm) Measurements -1 10GHz Locking Tange GHz Free-running Tuning Range ± 2GHz Varactor bits Locked Phase Noise 14dB±1dB -5 SMR40@15.8GHz -6 VDC2=0.55 V ILO@79GHz VDC2=0 V Frequency (GHz) Offset Frequency 26 (Hz)

27 PLL and LO Distribution Tx_ILO Cartesian combiner Tx_ILO TX In-Phase ILOs Combiner I + I - Q + Q - I bias,i I bias,q Combiner PPF for quadrature phase shifters 2-stage PPF 15.8 GHz distribution 25MHz Subsamplig PLL SS- PD PFD/C P Gm LP F 15.8GHz VCO Poly-phase filters generate quadrature Rx_QILO Div/N (79) Div/8 CP-PLL Integer-N PLL To Dig/ADC GHz Rx_QILO RX QILOs

28 Antenna Path Details TX-to-RX Spillover cancellation Analog BB and ADCs Digital Core Transmitter side-lobe suppression RX Front-End Sub-harmonic Injection Locked Oscillators multiply the PLL frequency by 5 28 Transmitter

29 TX architecture 15.8GHz CMOS BUF IL-VCO (x5) Modulator PA CMOS28 Harmonic Rejection & Pulse shaping BPSK frequency side-lobes at least -17dBc needed! PRN Code Fc=1/Tc=2Gbps PRF=1/(Tc*Lc) No LO quadrature Psat Low side-lobes 29

30 79GHz Phase-Modulator Linear BB X Non-linear LO Lc PRN Code generator 79GHz LO 79GHz LO PRN Code generator GHz Linear LO X Non-linear BB 79GHz LO PRN Code generator Lc Lc GHz Lower 79GHz swing More power efficient 30

31 TX Sidelobe Reduction by Harmonic Rejection 79GHz LO 1 1 Σ Tc=1/Fc Lc PRN Code generator Delay Tc/3 Δ GHz Most effective side-lobe lowest cost 31

32 79GHz Modulator and PA: Schematic Detail LOp VDD LOm HR3 Mixer VSMX BBin Prog. Delay-Line MMX Prog. Buffer Gain Tuner VDD 3-stage PA MPA CnPA VGPA VDD CnPA MPA BBin Balun 32

33 Receiver Implementation Gilbert cell mixer 2dB Gain V DD Mixer I and Q VGA ADC Buffer Output Buffer To IO Pads LO- LO- LO+ 7bits ADCs 2-stage LNA 18dB Gain V DD k V BIAS k VGA stage db in 7 steps V DD R L V B V DD ADC driver -2dB gain V out V in V DD V in V out R S V BIAS k V in 33

34 RX Spillover Cancellation BB BB VDD Weighted copy of BB injected at the mixer outputs to cancel the spillover Mix OUT Mixer R BB C BB W M BB BB LO- LO- LO+ VDD LNA OUT R C W P BB Correlation (multiplication with the TX sequence and integration) In steady state the mixer output is uncorrelated with the TX BB sequence: the spillover is cancelled! C 2 C 2

35 Digital Core Block Diagram Digital core generates the sequence and performs correlation and accumulation of the ADC samples Correlator (Lc) Accumulator (M) D<6:0> (from ADC) Out interface 1+1 Data Out CK CK/4 CK/<prog> I and Q To TX CK (1.975 GHz) 1 m [k] CK gen Clock Out TRX Sync Data Available 35 Other antenna path

36 IC Realization 28nm CMOS Die size 3 x 2.63mm Supply 0.9V/1.8V Flip chip assembly 36

37 IC Floorplan 28nm CMOS Die size 3 x 2.63mm Supply 0.9V/1.8V DIG. CORE TX TX DIG. CORE Flip chip assembly SH - ILOs LO Distr. SH - ILOs ADC RX BB PLL ADC RX BB RX FE RX FE 37

38 IC Photograph 28nm CMOS Die size 3 x 2.63mm Supply 0.9V/1.8V Flip chip assembly 38

39 PLL Measurements 25 MHz reference 16GHz VCO VCO only Phase Noise MHz 2GHz VCO tuning range corresponding to 78 to 88 GHz at TX output 79GHz ILO 10 MHz CP-PLL = Charge Pump PLL SS-PLL = Sub-Sampling PLL Measured at 79 GHz with R&S FS-Z90 and FSU and Agilent E5052 Signal Analyzer 39

40 Transmitter Measurements RBW 3 MHz Marker 1 [T1 ] VBW 10 MHz dbm Ref -17 dbm EXTM IX E SWT 60 ms GHz 1 AP VIEW 2 AP CLRWR GHz BW 1 A Pout > 10dBm 4 GHz BW EXT 3DB BPSK SideLobe Supp Center 80 GHz 1 GHz/ Span 10 GHz Date: 15.DEC :19:49 Measured with SAGE E band WR12 horn antenna, R&S FS-Z90 and FSU 40

41 Receiver Measurements NF < 1 GHz Including module input transition More than 30dB gain control in VGA BW > 1 GHz Measured with NOISE COM 5112 and R&S FSU on a dedicated module with GSG pads instead of antennas Base Band Analog output before the ADC measured 41

42 Indoor Antenna Module and Evaluation Board 2 dies on the back of the module Antennas on the front Panasonic MegTron6 42

43 PMCW Demonstrator Matlab framework for data analysis Radar module (2 chips): 4 TX antennas in azimuth 4 RX antennas in elevation MIMO configuration results in 2x2 and 4x4 array Targets can be localized in both azimuth and elevation FPGA/ARM core platform for data capture and analysis 43

44 Radar Measurements RCS = 20dBs 3 targets in an anechoic environment at different distance, azimuth and elevation RCS = 15dBsm RCS = 10dBsm Radar board with antenna facing the targets 44 Lc = 511 (m-seq), M = 232

45 Range & Speed Measurements 45

46 MIMO 4x4 Measurements Angle of Arrival: 46

47 Conclusions CMOS Radar SoCs area key building block for next-generation (selfdriving) cars And smart homes, buildings, things, etc. PMCW radar system is a feasible alternative for current FMCW architectures Major advantage for large-scale radar imagers IMEC PMCW radar SoCs prototypes show functionality And are used by partner companies in various application experiments The future is still to come; we haven t seen the last innovation in radars yet 47

48 PUBLIC