EE 240B discussion 3. Eric Chang

Transcription

1 EE 240B discussion 3 Eric Chang

2 Outline HW1 design solution. Transistor characterization using BAG. Tips on cascode design.

3 General Amplifier Design Strategy Gain/maximum BW independent of size and load capacitance. BW/noise improves linearity with size. Strategy: design a unit-size amplifier first that meets gain spec and have sufficient maximum BW. Then compute minimize size that meets BW/noise constraint. To minimize power, pick the best unit-size amplifier.

4 CS Amplifier Ignore load cap first, assume 1 finger. What is the minimum number of variables that completely determines amplifier performance?

5 CS Unit Amplifier design Given V "# and V $#, all SS parameters and bias current are determined. Load resistance also determined from KCL and V $$. Thus, given V "# and V $#, we look up SS parameters, and A & = g ) (R, r / ), w )23 = [ R, r / C If w )23 > w :;, then the size is k = = ABCD A EA 78, and bias current is just k F I :H2I.

6 CS Amplifier flow Sweep V "# and V $#, for each combination, do the following: Compute A & and w )23. If either constraints failed, go on to next combination. Compute amplifier size k and final bias current. This is the smallest current we ve seen record bias point. Return the best operating point.

7 BAG: Universal Verification Framework With schematic generators, it is now possible to develop testbenches that work with arbitrary circuits. Complex measurement procedures now only need to be programmed once, then can be re-used everywhere. Transistor characterization is the first testbench developed in this framework.

8 BAG s transistor char. algorithm 1. Determines the range of V "# that corresponds to a range of user-specified current density (ua/finger) a) Designer generally have a better idea on the bounds of current density instead of V "# range b) This gives us finer V "# step size for the same number of points. 2. Simulate Y parameters (at a given frequency) across bias points and extract small-signal parameters. 3. (Optional) Simulate noise, then calculate effective γ from a given integration interval. a) Calculates γ from g ) and total integrated noise assuming white noise spectrum. b) works best for narrow-band noise characterization (or when flicker noise is not dominant). 4. Results save to a database and available as interpolated functions.

9 Transistor characterization specification file Characterization settings specified in specs_mos_char/*.yaml. dut_lib/dut_cell defines the transistor being characterized. schematic_params section defines the schematic parameters of the transistor. measurements sections contains characterization options.

10 Example usage See scripts_char/nch_char_90n.py for how to run transistor characterization. See scripts_char/mos_query.py for how to get small signal parameters given operating point. HW1 solution has examples of how to use this to design your amplifier. See scripts_char/mos_plot.py for how to get the interpolated functions. See MOSDBDiscrete implementation for more details/functionalities.

11 Cascode design notes Why is cascode design hard? Many possible combination of sizes/bias voltages. How you generate the bias voltage can reduce degrees of freedom. Lazy bias: just tie to VDD/VSS. Only possible way in low-voltage processes. Large process/supply variations. Cascode current mirror bias. More stable across variations. Bias voltages function of bias network -> simplifies design. For homework, you get ideal voltage source. Less circuits to build, but harder to design.

12 Cascode design: blind sweeping Vb constant -> draw a black box and think of it as one composite transistor. As long as the pole at Vm is negligible, which is true for most open-loop applications. Can use the same transistor characterization routine to characterize cascode transistors. Have to sweep 5+ variables, but gives the most accurate/optimal design. See nch_char_cas.py and mos_plot_cas.py for examples of how to characterize and use MOSDBDiscrete with cascode transistors.

13 Cascode design: V /A &M based Note that V = 2I :H2I /g ) implies V of the composite transistor = V of the bottom transistor. /V :/O Specify V :/O, V O/P, and A &M,)HR of both transistors. A &M,)HR ensures that both transistors are in saturation, and knowing ratio of V makes designing bias network easy. First find lowest V ) such that V :/O and A &M,)HR specs can be met. This gives largest headroom for top transistor. Then find V S2I from V O/P. Check that cascode transistor meet A &M,)HR spec. If not then the specs are impossible to meet.